* Library of 74F Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights Reserved. * * * $Revision: 1.4 $ * $Author: RPEREZ $ * $Date: 16 Apr 1998 14:27:10 $ * * *$ *--------- * 74F00 Quadruple 2-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/24/89 Update interface and model names * .subckt 74F00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_F00 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F00 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *$ *--------- * 74F02 Quadruple 2-input Positive-Nor Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names * .subckt 74F02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_F02 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F02 ugate ( + tplhty=4ns tphlty=2.8ns + tplhmn=1.7ns tplhmx=6.5ns + tphlmn=1ns tphlmx=5.3ns + ) *$ *--------- * 74F04 Hex Inverters * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names * .subckt 74F04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_F04 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F04 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *$ *--------- * 74F08 Quadruple 2-input Positive-And Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names * .subckt 74F08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_F08 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F08 ugate ( + tplhty=3.8ns tphlty=3.6ns + tplhmn=2.2ns tplhmx=6.6ns + tphlmn=1.7ns tphlmx=6.3ns + ) *$ *--------- * 74F10 Triple 3-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names * .subckt 74F10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_F10 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F10 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *$ *--------- * 74F11 Triple 3-input Positive-And Gates * * The F Logic Data Book, 1987, TI * tdn 06/23/89 Update interface and model names * .subckt 74F11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_F11 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F11 ugate ( + tplhty=3.8ns tphlty=3.7ns + tplhmn=2.2ns tplhmx=6.6ns + tphlmn=1.7ns tphlmx=6.5ns + ) *$ *--------- * 74F20 Dual 4-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names * .subckt 74F20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_F20 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F20 ugate ( + tplhty=3.3ns tphlty=2.8ns + tplhmn=1.6ns tplhmx=6ns + tphlmn=1ns tphlmx=5.3ns + ) *$ *--------- * 74F21 Dual 4-input Positive-And Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names * .subckt 74F21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_F21 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F21 ugate ( + tplhty=4.3ns tphlty=3.8ns + ) *$ *--------- * 74F27 Triple 3-input Positive-Nor Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names * .subckt 74F27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_F27 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F27 ugate ( + tplhmn=1.2ns tphlmn=1ns + tplhty=3.1ns tplhmx=5.5ns + tphlty=2.1ns tphlmx=4.5ns + ) *$ *--------- * 74F30 8-input Positive-Nand Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names * .subckt 74F30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_F30 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F30 ugate ( + tplhty=3.1ns tphlty=2.6ns + tplhmn=1ns tplhmx=5.5ns + tphlmn=1ns tphlmx=5ns + ) *$ *--------- * 74F32 Quadruple 2-input Positive-Or Gates * * The F Logic Data Book, 1987, TI * tdn 06/26/89 Update interface and model names * .subckt 74F32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_F32 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F32 ugate ( + tplhty=3.8ns tphlty=3.6ns + tplhmn=2.2ns tplhmx=6.6ns + tphlmn=2.2ns tphlmx=6.3ns + ) *$ *------------------------------------------------------------------------- * 74F36 Quadruple 2-input Positive-Nor Gate * * The F Logic Data Book, 1987, TI * tdn 08/10/89 Update interface and model names * .subckt 74F36 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_F36 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F36 ugate ( + tplhmn=1.7ns tplhty=4ns + tplhmx=6.5ns tphlmn=1ns + tphlty=2.8ns tphlmx=5.3ns + ) *$ *--------- * 74F38 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * 1988 National Semiconductor. Updated 8/20/90 * .subckt 74F38 A B OBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B OBAR + D_74F38 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_74F38 ugate ( + tplhmn=6.5ns tplhty=9.7ns + tplhmx=13ns tphlmn=1ns + tphlty=2.1ns tphlmx=5.5ns + ) *$ *------------------------------------------------------------------------ * 74F64 4-2-3-2 Input And-Or-Invert Gates * * 1988 National Semiconductor. Updated 8/20/90 * .subckt 74F64 A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 D0 OBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,4) DPWR DGND + A0 B0 C0 D0 + A2 B2 $D_HI $D_HI + A1 B1 C1 $D_HI + B3 A3 $D_HI $D_HI + OBAR + D_F64 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F64 ugate ( + tplhmn=2.5ns tplhty=4.6ns + tplhmx=7.5ns tplhmn=1.5ns + tphlty=3.2ns tphlmx=5.5ns + ) *$ *--------- * 74F74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The F Logic Data Book, 1987, TI * tdn 06/28/89 Update interface and model names * .subckt 74F74 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_F74 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F74 ueff ( + twpclmn=4ns twclklmn=5ns + twclkhmn=4ns tsudclkmn=3ns + tsupcclkhmn=2ns thdclkmn=1ns + tppcqlhmn=2.40ns tppcqlhmx=7.1ns + tppcqhlmn=2.70ns tppcqhlmx=10.5ns + tpclkqlhmn=3.00ns tpclkqlhmx=7.8ns + tpclkqhlmn=3.6ns tpclkqhlmx=9.2ns + ) *$ *--------- * 74F86 Quadruple 2-input Exclusive-Or Gates * * 1988 National Semiconductor. Updated 8/20/90 * .subckt 74F86 A B O + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_74F86_1 IO_F MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_74F86_2 IO_F MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D O + D_74F86_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_74F86_1 ugate ( + tplhmn=2ns tplhty=3ns + tplhmx=5.5ns tphlmn=2ns + tphlty=3.2ns tphlmx=5.5ns + ) .model D_74F86_2 ugate ( + tplhmn=2ns tplhty=3.7ns + tplhmx=7ns tphlmn=2.5ns + tphlty=4.3ns tphlmx=6.5ns + ) .model D_74F86_3 ugate ( + tplhmn=1ns tplhty=1ns + tplhmx=1ns tphlmn=1ns + tphlty=1ns tphlmx=1ns + ) *$ *--------- * 74F109 Dual J-Kbar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The F Logic Data Book, 1987, TI * tdn 06/30/89 Update interface and model names * .subckt 74F109 CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLKBAR J K Q QBAR + D_F109 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + KBAR CLK K CLKBAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} .ends * .model D_F109 ueff ( + tppcqlhmn=2.4ns tppcqlhty=4.8ns + tppcqlhmx=7.1ns tppcqhlmn=2.7ns + tppcqhlty=6.6ns tppcqhlmx=10.5ns + tpclkqlhmn=3ns tpclkqlhty=4.9ns + tpclkqlhmx=7.8ns tpclkqhlmn=3.6ns + tpclkqhlty=5.8ns tpclkqhlmx=9.2ns + twclkhmx=4ns twclklmx=5ns + twclkhty=4ns twclklty=5ns + twpclmx=4ns twpclty=4ns + tsudclkmx=3ns tsudclkty=3ns + tsupcclkhmx=2ns tsupcclkhty=2ns + thdclkmx=1ns thdclkty=1ns + ) *$ *--------- * 74F112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Clear * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names * .subckt 74F112 CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + J K J_BUF K_BUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UB1 bufa(2) DPWR DGND + J_BUF K_BUF J1 K1 + D_F112_1 IO_F MNTYMXDLY={MNTYMXDLY} UB2 bufa(2) DPWR DGND + J_BUF K_BUF J1 K1 + D0_GATE IO_F U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J1 K1 Q QBAR + D_F112_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F112_1 ugate ( + tplhmn=1.5ns tplhmx=1.5ns + ) .model D_F112_2 ueff ( + tppcqlhmn=1.2ns tppcqlhty=4.1ns + tppcqlhmx=7.5ns tppcqhlmn=1.2ns + tppcqhlty=4.1ns tppcqhlmx=7.5ns + tpclkqlhmn=1.2ns tpclkqlhty=4.6ns + tpclkqlhmx=7.5ns tpclkqhlmn=1.2ns + tpclkqhlty=4.6ns tpclkqhlmx=7.5ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=3.5ns tsudclkty=3.5ns + tsupcclkhmx=5ns tsupcclkhty=5ns + ) *$ *------------------------------------------------------------------------- * 74F113 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names * .subckt 74F113 CLK PREBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR $D_HI CLK J K Q QBAR + D_F113 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F113 ueff ( + tppcqlhmn=1.2ns tppcqlhty=4.1ns + tppcqlhmx=7.5ns tppcqhlmn=1.2ns + tppcqhlty=4.1ns tppcqhlmx=7.5ns + tpclkqlhmn=1.2ns tpclkqlhty=3.6ns + tpclkqlhmx=7ns tpclkqhlmn=1.2ns + tpclkqhlty=3.6ns tpclkqhlmx=7ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=5ns tsudclkmn=5ns + tsupcclkhmx=5ns tsupcclkhmn=5ns + ) *$ *------------------------------------------------------------------------- * 74F114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * & Common Clear, & Common Clock * * The F Logic Data Book, 1987, TI * tdn 07/05/89 Update interface and model names * .subckt 74F114 CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_F114 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_F114 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F114 ueff ( + tppcqlhmn=2.2ns tppcqlhty=4.1ns + tppcqlhmx=7.5ns tppcqhlmn=2.2ns + tppcqhlty=4.1ns tppcqhlmx=7.5ns + tpclkqlhmn=2.2ns tpclkqlhty=4.6ns + tpclkqlhmx=7.5ns tpclkqhlmn=2.2ns + tpclkqhlty=5.1ns tpclkqhlmx=8.5ns + twclkhmx=5ns twclkhty=5ns + twclklmx=5ns twclklty=5ns + twpclmx=5ns twpclty=5ns + tsudclkmx=5ns tsudclkty=5ns + tsupcclkhmx=5ns tsupcclkhty=5ns + ) *$ *--------- * 74F138 DECODER/DEMULTIPLEXER 3-8 LINE * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTOR * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F138 E2_I E0BAR_I E1BAR_I A0_I A1_I A2_I + O0BAR_O O1BAR_O O2BAR_O O3BAR_O O4BAR_O O5BAR_O O6BAR_O O7BAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF138LOG LOGICEXP (6,15) DPWR DGND + E2_I E0BAR_I E1BAR_I A0_I A1_I A2_I + E2 E0BAR E1BAR A0 A1 A2 ENABLE + O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR O6BAR O7BAR + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + E2 = { E2_I } + E0BAR = { E0BAR_I } + E1BAR = { E1BAR_I } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + A0BAR = { ~A0 } + A1BAR = { ~A1 } + A2BAR = { ~A2 } + ENABLE = { ~E0BAR & ~E1BAR & E2 } + O0BAR = { ~(ENABLE & A2BAR & A1BAR & A0BAR) } + O1BAR = { ~(ENABLE & A2BAR & A1BAR & A0 ) } + O2BAR = { ~(ENABLE & A2BAR & A1 & A0BAR) } + O3BAR = { ~(ENABLE & A2BAR & A1 & A0 ) } + O4BAR = { ~(ENABLE & A2 & A1BAR & A0BAR) } + O5BAR = { ~(ENABLE & A2 & A1BAR & A0 ) } + O6BAR = { ~(ENABLE & A2 & A1 & A0BAR) } + O7BAR = { ~(ENABLE & A2 & A1 & A0 ) } * UF138DLY PINDLY (8,0,7) DPWR DGND + O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR O6BAR O7BAR + ENABLE E2 E0BAR E1BAR A0 A1 A2 + O0BAR_O O1BAR_O O2BAR_O O3BAR_O O4BAR_O O5BAR_O O6BAR_O O7BAR_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(ENABLE,0) & CHANGED(E2,0) } + ABLEBAR = { CHANGED(ENABLE,0) & (CHANGED(E0BAR,0) | CHANGED(E1BAR,0)) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) } + + PINDLY: + O0BAR_O O1BAR_O O2BAR_O O3BAR_O O4BAR_O O5BAR_O O6BAR_O O7BAR_O = { + CASE ( + ABLEBAR & TRN_HL, DELAY(3.0NS,5.3NS,7.5NS), + ADDR & TRN_LH, DELAY(3.5NS,5.6NS,8.0NS), + ABLEBAR & TRN_LH, DELAY(3.5NS,6.4NS,8.0NS), + ABLE & TRN_HL, DELAY(3.5NS,5.6NS,8.5NS), + ADDR & TRN_HL, DELAY(4.0NS,6.1NS,9.0NS), + ABLE & TRN_LH, DELAY(4.0NS,6.2NS,9.0NS), + DELAY(4.0NS,6.4NS,9.0NS) + ) + } * .ENDS * *$ *-------- * 74F139 DECODER/DEMULTIPLEXER 2-4 LINE * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 8-3-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F139 EBAR_I A0_I A1_I O0BAR_O O1BAR_O O2BAR_O O3BAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF139LOG LOGICEXP (3,7) DPWR DGND + EBAR_I A0_I A1_I + EBAR A0 A1 + O0BAR O1BAR O2BAR O3BAR + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + EBAR = { EBAR_I } + A0 = { A0_I } + A1 = { A1_I } + A0BAR = { ~A0 } + A1BAR = { ~A1 } + ENABLE = { ~EBAR } + O0BAR = { ~(ENABLE & A1BAR & A0BAR ) } + O1BAR = { ~(ENABLE & A1BAR & A0 ) } + O2BAR = { ~(ENABLE & A1 & A0BAR ) } + O3BAR = { ~(ENABLE & A1 & A0 ) } * UF139DLY PINDLY (4,0,3) DPWR DGND + O0BAR O1BAR O2BAR O3BAR + EBAR A0 A1 + O0BAR_O O1BAR_O O2BAR_O O3BAR_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(EBAR,0) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) } + + PINDLY: + O0BAR_O O1BAR_O O2BAR_O O3BAR_O = { + CASE ( + ADDR & TRN_LH, DELAY(3.0NS,5.3NS,8.0NS), + ADDR & TRN_HL, DELAY(4.0NS,6.1NS,9.0NS), + ABLE & TRN_LH, DELAY(3.5NS,5.4NS,8.0NS), + ABLE & TRN_HL, DELAY(3.0NS,4.7NS,7.5NS), + DELAY(4.0NS,6.1NS,9.0NS) + ) + } * .ENDS * *$ *--------- * 74F148 PRIORITY ENCODER 8-3 LINE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F148 IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I + A0_O A1_O A2_O GS_O EO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF148LOG LOGICEXP (9,14) DPWR DGND + IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0 A1 A2 GS EO + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + IN0 = { IN0_I } + IN1 = { IN1_I } + IN2 = { IN2_I } + IN3 = { IN3_I } + IN4 = { IN4_I } + IN5 = { IN5_I } + IN6 = { IN6_I } + IN7 = { IN7_I } + EI = { EI_I } + IN0BAR = { ~IN0 } + IN1BAR = { ~IN1 } + IN2BAR = { ~IN2 } + IN3BAR = { ~IN3 } + IN4BAR = { ~IN4 } + IN5BAR = { ~IN5 } + IN6BAR = { ~IN6 } + IN7BAR = { ~IN7 } + EIBAR = { ~EI } + + A0 = { ~(EIBAR & ((IN1BAR & IN2 & IN4 & IN6) | + (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) } + A1 = { ~(EIBAR & ((IN2BAR & IN4 & IN5) | + (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) } + A2 = { ~(EIBAR & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) } + EO = { ~(IN0 & IN1 & IN2 & IN3 & IN4 & IN5 & IN6 & IN7 & EIBAR) } + GS = { ~(EO & EIBAR) } * UF148DLY PINDLY (5,0,9) DPWR DGND + A0 A1 A2 GS EO + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0_O A1_O A2_O GS_O EO_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATAHI = { IN7=='1 & IN6=='1 & IN5=='1 & IN4=='1 & + IN3=='1 & IN2=='1 & IN1=='1 & IN0=='1 } + ENABLE = { CHANGED(EI,0) } + + PINDLY: + A2_O A1_O A0_O= { + CASE ( + ENABLE & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + ENABLE & TRN_HL, DELAY(3.0NS,5.5NS, 9.0NS), + TRN_LH, DELAY(3.5NS,6.0NS,10.0NS), + TRN_HL, DELAY(4.0NS,6.0NS,12.0NS), + DELAY(4.0NS,6.0NS,12.0NS) + ) + } + GS_O = { + CASE ( + ENABLE & TRN_LH, DELAY(2.5NS,4.5NS, 8.0NS), + ENABLE & TRN_HL, DELAY(3.0NS,5.5NS, 8.5NS), + TRN_LH, DELAY(2.0NS,4.0NS,10.0NS), + TRN_HL, DELAY(2.0NS,6.0NS, 9.0NS), + DELAY(3.0NS,6.0NS,10.0NS) + ) + } + EO_O = { + CASE ( + ENABLE & TRN_LH, DELAY(3.0NS,5.0NS, 8.0NS), + ENABLE & TRN_HL, DELAY(4.5NS,7.0NS,12.0NS), + TRN_LH, DELAY(2.0NS,3.5NS, 7.5NS), + TRN_HL, DELAY(2.5NS,4.5NS, 8.5NS), + DELAY(4.5NS,7.0NS,12.0NS) + ) + } * .ENDS * *$ *--------- * 74F151 MULTIPLEXER/DATA SELECTOR 8-1 LINE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * TC 08/21/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F151 EBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + Z_O ZBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF151LOG LOGICEXP(12,14) DPWR DGND + EBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + EBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 ZBAR Z + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + EBAR = { EBAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + I0 = { I0_I } + I1 = { I1_I } + I2 = { I2_I } + I3 = { I3_I } + I4 = { I4_I } + I5 = { I5_I } + I6 = { I6_I } + I7 = { I7_I } + IS0 = { ~S0 } + IS1 = { ~S1 } + IS2 = { ~S2 } + IE = { ~EBAR } + II0 = { I0 & IS0 & IS1 & IS2 & IE } + II1 = { I1 & S0 & IS1 & IS2 & IE } + II2 = { I2 & IS0 & S1 & IS2 & IE } + II3 = { I3 & S0 & S1 & IS2 & IE } + II4 = { I4 & IS0 & IS1 & S2 & IE } + II5 = { I5 & S0 & IS1 & S2 & IE } + II6 = { I6 & IS0 & S1 & S2 & IE } + II7 = { I7 & S0 & S1 & S2 & IE } + ZBAR = { ~(II0 | II1 | II2 | II3 | II4 | II5 | II6 | II7) } + Z = { ~ZBAR } * UF151DLY PINDLY (2,0,12) DPWR DGND + ZBAR Z + EBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 + ZBAR_O Z_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) | + CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0) } + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0) } + ENABLE = { CHANGED(EBAR,0) } + PINDLY: + Z_O = { + CASE( + SELECT & TRN_LH, DELAY(4NS,7NS,12NS), + ENABLE & TRN_LH, DELAY(5.5NS,8NS,11.5NS), + SELECT & TRN_HL, DELAY(4.5NS,7NS,10NS), + DATA & TRN_LH, DELAY(2.5NS,4.5NS,9NS), + ENABLE & TRN_HL, DELAY(4NS,5.5NS,8NS), + DATA & TRN_HL, DELAY(3NS,4.5NS,7.5NS), + DELAY(5NS,8NS,13NS) + ) + } + ZBAR_O = { + CASE( + SELECT & TRN_LH, DELAY(3.5NS,6.5NS,10NS), + ENABLE & TRN_HL, DELAY(4NS,5.5NS,8NS), + ENABLE & TRN_LH, DELAY(3.5NS,5NS,7.5NS), + SELECT & TRN_HL, DELAY(2NS,4.5NS,7.5NS), + DATA & TRN_LH, DELAY(2NS,4NS,7NS), + DATA & TRN_HL, DELAY(1NS,2.5NS,5NS), + DELAY(4NS,7NS,11NS) + ) + } * .ENDS * *$ *--------- * 74F151A MULTIPLEXER/DATA SELECTOR 8-1 LINE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * TC 08/28/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F151A EBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + Z_O ZBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF151ALOG LOGICEXP(12,14) DPWR DGND + EBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + EBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 ZBAR Z + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + EBAR = { EBAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + I0 = { I0_I } + I1 = { I1_I } + I2 = { I2_I } + I3 = { I3_I } + I4 = { I4_I } + I5 = { I5_I } + I6 = { I6_I } + I7 = { I7_I } + IS0 = { ~S0 } + IS1 = { ~S1 } + IS2 = { ~S2 } + IE = { ~EBAR } + II0 = { I0 & IS0 & IS1 & IS2 & IE } + II1 = { I1 & S0 & IS1 & IS2 & IE } + II2 = { I2 & IS0 & S1 & IS2 & IE } + II3 = { I3 & S0 & S1 & IS2 & IE } + II4 = { I4 & IS0 & IS1 & S2 & IE } + II5 = { I5 & S0 & IS1 & S2 & IE } + II6 = { I6 & IS0 & S1 & S2 & IE } + II7 = { I7 & S0 & S1 & S2 & IE } + ZBAR = { ~(II0 | II1 | II2 | II3 | II4 | II5 | II6 | II7) } + Z = { ~ZBAR } * UF151ADLY PINDLY (2,0,12) DPWR DGND + ZBAR Z + EBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 + ZBAR_O Z_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) | + CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0) } + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0) } + ENABLE = { CHANGED(EBAR,0) } + PINDLY: + Z_O = { + CASE( + SELECT & TRN_LH, DELAY(4NS,6.5NS,11NS), + ENABLE & TRN_LH, DELAY(3.5NS,6.5NS,9.5NS), + SELECT & TRN_HL, DELAY(3.5NS,6NS,9.5NS), + ENABLE & TRN_HL, DELAY(3NS,5NS,7.5NS), + DATA, DELAY(2.5NS,4.5NS,7.5NS), + DELAY(5NS,7NS,12NS) + ) + } + ZBAR_O = { + CASE( + SELECT & TRN_LH, DELAY(3NS,5.5NS,9.5NS), + SELECT & TRN_HL, DELAY(2NS,4.5NS,7.5NS), + DATA & TRN_LH, DELAY(2NS,4NS,7.5NS), + ENABLE & TRN_LH, DELAY(2.5NS,4.5NS,7NS), + ENABLE & TRN_HL, DELAY(1.5NS,3.5NS,6NS), + DATA & TRN_HL, DELAY(1NS,2NS,5NS), + DELAY(4NS,6NS,10NS) + ) + } * .ENDS * *$ *--------- * 74F153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/12/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F153 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF153LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * UF153DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT, DELAY(4.5NS,8NS,12NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(4.5NS,7.5NS,10.5NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(3.5NS,5.5NS,8NS), + DATA1 & TRN_LH, DELAY(2.5NS,4.5NS,8NS), + DATA1 & TRN_HL, DELAY(2.5NS,5NS,8NS), + DELAY(5NS,9NS,13NS) + ) + } + Y2_O = { + CASE( + SELECT, DELAY(4.5NS,8NS,12NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(4.5NS,7.5NS,10.5NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(3.5NS,5.5NS,8NS), + DATA2 & TRN_LH, DELAY(2.5NS,4.5NS,8NS), + DATA2 & TRN_HL, DELAY(2.5NS,5NS,8NS), + DELAY(5NS,9NS,13NS) + ) + } * .ENDS * *$ *--------- * 74F154 DECODER/DEMULTIPLEXER 2-4 LINE * * IC15 FAST TTL LOGIC SERIES, 990, PHILIPS SEMICONDUCTORS * JLS 8-6-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F154 E0BAR_I E1BAR_I A0_I A1_I A2_I A3_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + Y8_O Y9_O Y10_O Y11_O Y12_O Y13_O Y14_O Y15_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF154LOG LOGICEXP (6,21) DPWR DGND + E0BAR_I E1BAR_I A0_I A1_I A2_I A3_I + ENABLE A0 A1 A2 A3 + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + E0BAR = { E0BAR_I } + E1BAR = { E1BAR_I } + ENABLE = { ~(E0BAR | E1BAR) } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A0BAR = { ~A0 } + A1BAR = { ~A1 } + A2BAR = { ~A2 } + A3BAR = { ~A3 } + Y0 = { ~(ENABLE & A3BAR & A2BAR & A1BAR & A0BAR) } + Y1 = { ~(ENABLE & A3BAR & A2BAR & A1BAR & A0 ) } + Y2 = { ~(ENABLE & A3BAR & A2BAR & A1 & A0BAR) } + Y3 = { ~(ENABLE & A3BAR & A2BAR & A1 & A0 ) } + Y4 = { ~(ENABLE & A3BAR & A2 & A1BAR & A0BAR) } + Y5 = { ~(ENABLE & A3BAR & A2 & A1BAR & A0 ) } + Y6 = { ~(ENABLE & A3BAR & A2 & A1 & A0BAR) } + Y7 = { ~(ENABLE & A3BAR & A2 & A1 & A0 ) } + Y8 = { ~(ENABLE & A3 & A2BAR & A1BAR & A0BAR) } + Y9 = { ~(ENABLE & A3 & A2BAR & A1BAR & A0 ) } + Y10 = { ~(ENABLE & A3 & A2BAR & A1 & A0BAR) } + Y11 = { ~(ENABLE & A3 & A2BAR & A1 & A0 ) } + Y12 = { ~(ENABLE & A3 & A2 & A1BAR & A0BAR) } + Y13 = { ~(ENABLE & A3 & A2 & A1BAR & A0 ) } + Y14 = { ~(ENABLE & A3 & A2 & A1 & A0BAR) } + Y15 = { ~(ENABLE & A3 & A2 & A1 & A0 ) } * UF154DLY PINDLY (16,0,5) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + ENABLE A0 A1 A2 A3 + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + Y8_O Y9_O Y10_O Y11_O Y12_O Y13_O Y14_O Y15_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(ENABLE,0) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + Y8_O Y9_O Y10_O Y11_O Y12_O Y13_O Y14_O Y15_O = { + CASE ( + ABLE & TRN_LH, DELAY(1.5NS,4.0NS, 8.0NS), + ABLE & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + ADDR & TRN_LH, DELAY(1.5NS,5.0NS,10.5NS), + ADDR & TRN_HL, DELAY(3.0NS,6.5NS,10.5NS), + DELAY(3.5NS,6.5NS,10.5NS) + ) + } * .ENDS * *$ *--------- * 74F157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F157 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF157LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + G = { ~GBAR } + Y1 = { (1A & SELBAR & G) | (1B & SEL & G) } + Y2 = { (2A & SELBAR & G) | (2B & SEL & G) } + Y3 = { (3A & SELBAR & G) | (3B & SEL & G) } + Y4 = { (4A & SELBAR & G) | (4B & SEL & G) } * UF157DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_LH, DELAY(4.5NS,8NS,15NS), + ENABLE & TRN_LH, DELAY(5NS,7.5NS,11.5NS), + SELECT & TRN_HL, DELAY(3.5NS,6NS,9NS), + ENABLE & TRN_HL, DELAY(3.8NS,5NS,8NS), + DATA & TRN_LH, DELAY(3NS,4.5NS,8NS), + DATA & TRN_HL, DELAY(1.5NS,3.5NS,7NS), + DELAY(6NS,9NS,16NS) + ) + } * .ENDS * *$ *--------- * 74F157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F157A GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF157ALOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + G = { ~GBAR } + Y1 = { (1A & SELBAR & G) | (1B & SEL & G) } + Y2 = { (2A & SELBAR & G) | (2B & SEL & G) } + Y3 = { (3A & SELBAR & G) | (3B & SEL & G) } + Y4 = { (4A & SELBAR & G) | (4B & SEL & G) } * UF157ADLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_LH, DELAY(5NS,7.5NS,11NS), + ENABLE & TRN_LH, DELAY(5.5NS,7.5NS,10.5NS), + SELECT & TRN_HL, DELAY(4NS,6NS,8.5NS), + ENABLE & TRN_HL, DELAY(4NS,5NS,7NS), + DATA & TRN_LH, DELAY(3NS,4.5NS,7NS), + DATA & TRN_HL, DELAY(1.5NS,3.5NS,6NS), + DELAY(6NS,8NS,12NS) + ) + } * .ENDS * *$ *--------- * 74F158 QUAD 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F158 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF158LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + G = { ~GBAR } + Y1 = { ~((1A & SELBAR & G) | (1B & SEL & G)) } + Y2 = { ~((2A & SELBAR & G) | (2B & SEL & G)) } + Y3 = { ~((3A & SELBAR & G) | (3B & SEL & G)) } + Y4 = { ~((4A & SELBAR & G) | (4B & SEL & G)) } * UF158DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_HL, DELAY(3.5NS,5.5NS,10.5NS), + SELECT & TRN_LH, DELAY(4NS,6.5NS,9.5NS), + ENABLE & TRN_HL, DELAY(3.5NS,5.5NS,9.5NS), + ENABLE & TRN_LH, DELAY(4NS,6NS,9NS), + DATA & TRN_LH, DELAY(2.5NS,4NS,7NS), + DATA & TRN_HL, DELAY(1NS,2.5NS,5.5NS), + DELAY(5NS,7NS,11NS) + ) + } * .ENDS * *$ *--------- * 74F158A DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F158A GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF158ALOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + G = { ~GBAR } + Y1 = { ~((1A & SELBAR & G) | (1B & SEL & G)) } + Y2 = { ~((2A & SELBAR & G) | (2B & SEL & G)) } + Y3 = { ~((3A & SELBAR & G) | (3B & SEL & G)) } + Y4 = { ~((4A & SELBAR & G) | (4B & SEL & G)) } * UF158ADLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_LH, DELAY(4NS,6.5NS,9.5NS), + ENABLE & TRN_HL, DELAY(5NS,6NS,8NS), + SELECT & TRN_HL, DELAY(3.5NS,5.5NS,8NS), + ENABLE & TRN_LH, DELAY(4NS,5.5NS,7.5NS), + DATA & TRN_LH, DELAY(2.5NS,4NS,7NS), + DATA & TRN_HL, DELAY(1NS,2.5NS,4.5NS), + DELAY(6NS,7NS,10NS) + ) + } * .ENDS * *$ *--------- * 74F160A Synchronous 4-bit Decade Counters with asynchronous clear * * FAST TTL SERIES, 1990, PHILIPS SEMICONDUCTORS * JSW 7/9/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F160A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF160ALOG LOGICEXP(17,19) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I IQA IQB IQC IQD + IQABAR IQBBAR IQCBAR IQDBAR + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD QA QB QC QD EN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + QA = { ~IQABAR } + QB = { ~IQBBAR } + QC = { ~IQCBAR } + QD = { ~IQDBAR } + LOAD = { ~LOADBAR } ;Logic expressions + EN = { ENP & ENT & LOADBAR } + DA = { (A & LOAD) | ((LOADBAR & IQA) ^ EN) } + IB1 = { IQABAR | IQBBAR | IQCBAR | IQDBAR } + IB2 = { IQABAR | IQB | IQC | IQDBAR } + DB = { ((B & LOAD) | ((LOADBAR & IQB) ^ (IQA & EN))) & IB1 & IB2 } + DC = { (C & LOAD) | ((LOADBAR & IQC) ^ (IQA & IQB & EN)) } + ID1 = { IQABAR | IQB | IQC | IQDBAR } + ID2 = { IQABAR | IQB | IQCBAR | IQDBAR } + ID3 = { IQABAR | IQBBAR | IQB | IQDBAR } + DD = { (D & LOAD) | ((LOADBAR & IQD) ^ (IQA & IQB & IQC & EN)) + & ID1 & ID2 & ID3 } + RCO = { ENT & IQA & IQBBAR & IQCBAR & IQD } * UDFF DFF(4) DPWR DGND $D_HI CLRBAR CLK DA DB DC DD + IQA IQB IQC IQD IQABAR IQBBAR IQCBAR IQDBAR D0_EFF IO_F * UF160ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK LOADBAR ENT CLRBAR ENP A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + CLEAR = { CHANGED_HL(CLRBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & LOADBAR=='1 & TRN_LH, DELAY(2NS,4.5NS,8NS), + CLOCK & LOADBAR=='1 & TRN_HL, DELAY(4NS,7NS,11NS), + CLOCK & LOADBAR=='0 & TRN_LH, DELAY(2NS,4.5NS,8.5NS), + CLOCK & LOADBAR=='0 & TRN_HL, DELAY(4NS,6NS,9.5NS), + CLEAR, DELAY(6.5NS,9NS,13NS), + DELAY(6.5NS,9NS,13NS) + ) + } + RCO_O = { + CASE( + CNTENT & TRN_LH, DELAY(1.5NS,4NS,7NS), + CNTENT & TRN_HL, DELAY(2.5NS,5NS,7.5NS), + CLOCK & TRN_LH, DELAY(4.5NS,8NS,11.5NS), + CLOCK & TRN_HL, DELAY(4.5NS,7.5NS,10NS), + CLEAR, DELAY(5.5NS,8NS,11NS), + DELAY(6NS,9NS,12NS) + ) + } + BOOLEAN: + ENABLES = { CLRBAR!='0 & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) + & CHANGED(EN,11NS) } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_HI = 4NS + MIN_LO = 6NS + WHEN = { LOADBAR=='0 } + WIDTH: + NODE = CLK + MIN_HI = 4NS + MIN_LO = 6.5NS + WHEN = { LOADBAR=='1 } + WIDTH: + NODE = CLRBAR + MIN_LO = 5NS + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 6NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 5NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME_HI = 11NS + SETUPTIME_LO = 7NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME_HI = 11NS + SETUPTIME_LO = 7.5NS + WHEN = { ENABLES } * .ENDS * *$ *--------- * 74F161A Synchronous 4-bit Binary Counter with Direct Clear * * FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTOR * tc 07/02/92 Remodeled using LOGICEXP, PINDLY & CONSTRAINT devices * .SUBCKT 74F161A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CLRBAR CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_F * UF161ALOG LOGICEXP(17,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK ENP ENT CLRBAR LOADBAR A B C D DA DB DC DD RCO IEN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + IPE = { ~LOADBAR } + IA = { (LOADBAR & QA) ^ IEN } + IB = { (LOADBAR & QB) ^ (IEN & QA) } + IC = { (LOADBAR & QC) ^ (IEN & QA & QB) } + ID = { (LOADBAR & QD) ^ (IEN & QA & QB & QC) } + DA = { (A & IPE) | IA } + DB = { (B & IPE) | IB } + DC = { (C & IPE) | IC } + DD = { (D & IPE) | ID } + RCO = { ENT & QA & QB & QC & QD } * UF161ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + LOADBAR CLK ENT CLRBAR ENP A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CLEAR = { CHANGED_HL(CLRBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & LOADBAR!='0 & TRN_LH, DELAY(2NS,4NS,7NS), + CLOCK & LOADBAR!='1 & TRN_LH, DELAY(2NS,4.5NS,7.5NS), + CLOCK & LOADBAR!='1 & TRN_HL, DELAY(3.5NS,5.5NS,9.5NS), + CLOCK & LOADBAR!='0 & TRN_HL, DELAY(4NS,6.5NS,11NS), + CLEAR, DELAY(5.5NS,8.5NS,13NS), + DELAY(5.5NS,8.5NS,13NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0) & TRN_LH, DELAY(1.5NS,3.5NS,7NS), + CHANGED(ENT,0) & TRN_HL, DELAY(2.5NS,5NS,8NS), + CLEAR, DELAY(5NS,8.5NS,11NS), + CLOCK & TRN_HL, DELAY(4NS,7.5NS,11.5NS), + CLOCK & TRN_LH, DELAY(5NS,7.5NS,11.5NS), + DELAY(5NS,7.5NS,11.5NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_LO = 5.5NS + MIN_HI = 4NS + WHEN = { LOADBAR!='1 } + WIDTH: + NODE = CLK + MIN_LO = 7NS + MIN_HI = 4NS + WHEN = { LOADBAR!='0 } + WIDTH: + NODE = CLRBAR + MIN_LO = 4.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 5NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME_LO = 7NS + SETUPTIME_HI = 9.5NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME_LO = 7NS + SETUPTIME_HI = 10.5NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + CLRBAR!='0 & CHANGED(IEN,10.5NS) } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 6.5NS * .ENDS * *$ *--------- * 74F162A Synchronous 4-bit Decade Counters with asynchronous clear * * FAST TTL SERIES, 1990, PHILIPS SEMICONDUCTORS * JSW 7/9/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F162A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF162ALOG LOGICEXP(17,19) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I IQA IQB IQC + IQD IQABAR IQBBAR IQCBAR IQDBAR + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD QA QB QC QD EN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + CLR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + QA = { ~IQABAR } + QB = { ~IQBBAR } + QC = { ~IQCBAR } + QD = { ~IQDBAR } + LOAD = { ~LOADBAR } ;Logic expressions + EN = { ENP & ENT & LOADBAR & CLR } + DA = { (A & LOAD & CLR) | ((LOADBAR & IQA & CLR) ^ EN) } + IB1 = { IQABAR | IQBBAR | IQCBAR | IQDBAR } + IB2 = { IQABAR | IQB | IQC | IQDBAR } + DB = { ((B & LOAD & CLR) | ((LOADBAR & IQB & CLR) ^ (IQA & EN))) + & IB1 & IB2 } + DC = { (C & LOAD & CLR) | ((LOADBAR & IQC & CLR) ^ (IQA & IQB & EN)) } + ID1 = { IQABAR | IQB | IQC | IQDBAR } + ID2 = { IQABAR | IQB | IQCBAR | IQDBAR } + ID3 = { IQABAR | IQBBAR | IQB | IQDBAR } + DD = { (D & LOAD & CLR) | ((LOADBAR & IQD & CLR) ^ (IQA & IQB & IQC + & EN)) & ID1 & ID2 & ID3 } + RCO = { ENT & IQA & IQBBAR & IQCBAR & IQD } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + IQA IQB IQC IQD IQABAR IQBBAR IQCBAR IQDBAR D0_EFF IO_F * UF162ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK LOADBAR ENT ENP CLRBAR A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & LOADBAR=='1 & TRN_LH, DELAY(2NS,4.5NS,8NS), + CLOCK & LOADBAR=='0 & TRN_LH, DELAY(2NS,4.5NS,8.5NS), + CLOCK & LOADBAR=='0 & TRN_HL, DELAY(4NS,6NS,9.5NS), + CLOCK & LOADBAR=='1 & TRN_HL, DELAY(4NS,7NS,11NS), + DELAY(4NS,7NS,11NS) + ) + } + RCO_O = { + CASE( + CNTENT & TRN_LH, DELAY(1.5NS,4NS,7NS), + CNTENT & TRN_HL, DELAY(2.5NS,5NS,7.5NS), + CLOCK & TRN_HL, DELAY(4.5NS,7.5NS,10NS), + CLOCK & TRN_LH, DELAY(4.5NS,8NS,11.5NS), + DELAY(4.5NS,8NS,11.5NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_HI = 4NS + MIN_LO = 6NS + WHEN = { LOADBAR=='0 } + WIDTH: + NODE = CLK + MIN_HI = 4NS + MIN_LO = 6.5NS + WHEN = { LOADBAR=='1 } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 5NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME_HI = 11NS + SETUPTIME_LO = 7NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME_LO = 7.5NS + SETUPTIME_HI = 11NS + WHEN = { CHANGED(EN,11NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_HI = 11NS + SETUPTIME_LO = 7NS * .ENDS * *$ *--------- * 74F163A Synchronous 4-bit Binary Counter * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTOR * tc 07/08/92 Remodeled using LOGICEXP, PINDLY & CONSTRAINT Devices * .SUBCKT 74F163A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_F * UF163ALOG LOGICEXP(17,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK ENP ENT CLRBAR LOADBAR A B C D IEN DA DB DC DD RCO + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + IPE = { ~LOADBAR } + IA = { (LOADBAR & CLRBAR & QA) ^ (IEN & CLRBAR) } + IB = { (LOADBAR & CLRBAR & QB) ^ (IEN & CLRBAR & QA) } + IC = { (LOADBAR & CLRBAR & QC) ^ (IEN & CLRBAR & QA & QB) } + ID = { (LOADBAR & CLRBAR & QD) ^ (IEN & CLRBAR & QA & QB & QC) } + DA = { (A & IPE & CLRBAR) | IA } + DB = { (B & IPE & CLRBAR) | IB } + DC = { (C & IPE & CLRBAR) | IC } + DD = { (D & IPE & CLRBAR) | ID } + RCO = { ENT & QA & QB & QC & QD } * UF163ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + LOADBAR CLK ENT CLRBAR ENP A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & LOADBAR=='1 & TRN_LH, DELAY(2NS,4NS,7NS), + CLOCK & LOADBAR=='0 & TRN_LH, DELAY(2NS,4.5NS,7.5NS), + CLOCK & LOADBAR=='0 & TRN_HL, DELAY(3.5NS,5.5NS,9.5NS), + CLOCK & LOADBAR=='1 & TRN_HL, DELAY(4NS,6.5NS,11NS), + DELAY(4NS,6.5NS,11NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0) & TRN_LH, DELAY(1.5NS,3.5NS,7NS), + CHANGED(ENT,0) & TRN_HL, DELAY(2.5NS,5NS,8NS), + CLOCK & TRN_HL, DELAY(4NS,7.5NS,11.5NS), + CLOCK & TRN_LH, DELAY(5NS,7.5NS,11.5NS), + DELAY(5NS,7.5NS,11.5NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_LO = 5.5NS + MIN_HI = 4NS + WHEN = { LOADBAR!='1 } + WIDTH: + NODE = CLK + MIN_LO = 7NS + MIN_HI = 4NS + WHEN = { LOADBAR!='0 } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 5NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME_LO = 7NS + SETUPTIME_HI = 9.5NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 7NS + SETUPTIME_HI = 9.5NS + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME_LO = 7NS + SETUPTIME_HI = 10.5NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & NOTCLEAR & + CHANGED(IEN,10.5NS) } * .ENDS * *$ *--------- *74F164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * * FAST ADVANCED SCHOTTKY TTL LOGIC DATABOOK, 1990, NSC * KN 7-6-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F164 MRBAR_I CP_I A_I B_I Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(4) DPWR DGND + MRBAR_I CP_I A_I B_I MRBAR CP A B + D0_GATE IO_F IO_LEVEL={IO_LEVEL} * U2 AND(2) DPWR DGND + A B IN + D0_GATE IO_F * U3 DFF(8) DPWR DGND + $D_HI MRBAR CP + IN Q0 Q1 Q2 Q3 Q4 Q5 Q6 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * UF164DLY PINDLY (8,0,4) DPWR DGND + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + MRBAR CP A B + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O = { + CASE( + CHANGED_LH(CP,0) & TRN_LH, DELAY(2.5NS,5.0NS,9.0NS), + CHANGED_LH(CP,0) & TRN_HL, DELAY(5.0NS,7.0NS,11.0NS), + CHANGED_HL(MRBAR,0), DELAY(5.5NS,7.5NS,11.5NS), + DELAY(6.5NS,8.5NS,12.5NS) ;DEFAULT + ) + } + + FREQ: + NODE = CP + MAXFREQ = 80MEG + + WIDTH: + NODE = CP + MIN_HIGH = 4NS + MIN_LOW = 7NS + + WIDTH: + NODE = MRBAR + MIN_LOW = 7NS + + SETUP_HOLD: + CLOCK LH = CP + DATA(2) A B + SETUPTIME = 5NS + HOLDTIME = 2NS + WHEN = { MRBAR != '0 } + + SETUP_HOLD: + CLOCK LH = CP + DATA(1) MRBAR + RELEASETIME_LH = 7NS + * .ENDS * *$ *--------- * 74F166 8-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER * * FAST TTL LOGIC SERIES DATA BOOK, 1990, PHILIPS SEMICONDUCTORS * NH 7-22-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * CP1 IS USED AS CLOCK INHIBIT (CEBAR) AND CP2 IS USED AS CLOCK INPUT (CP) * .SUBCKT 74F166 MRBAR_I PEBAR_I CP1_I CP2_I DS_I P0_I P1_I P2_I P3_I P4_I P5_I + P6_I P7_I Q7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF166LOG LOGICEXP(20,22) DPWR DGND + MRBAR_I PEBAR_I CP1_I CP2_I DS_I P0_I P1_I P2_I P3_I P4_I P5_I P6_I P7_I + Q0 Q1 Q2 Q3 Q4 Q5 Q6 + MRBAR PEBAR CP1 CP2 DS P0 P1 P2 P3 P4 P5 P6 P7 D0 D1 D2 D3 D4 D5 D6 D7 CLK + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + MRBAR = { MRBAR_I } + PEBAR = { PEBAR_I } + CP1 = { CP1_I } + CP2 = { CP2_I } + DS = { DS_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + P4 = { P4_I } + P5 = { P5_I } + P6 = { P6_I } + P7 = { P7_I } + * INTERMEDIATE TERM + PE = { ~PEBAR } + + D0 = { (PEBAR & DS) | (PE & P0) } + D1 = { (PEBAR & Q0) | (PE & P1) } + D2 = { (PEBAR & Q1) | (PE & P2) } + D3 = { (PEBAR & Q2) | (PE & P3) } + D4 = { (PEBAR & Q3) | (PE & P4) } + D5 = { (PEBAR & Q4) | (PE & P5) } + D6 = { (PEBAR & Q5) | (PE & P6) } + D7 = { (PEBAR & Q6) | (PE & P7) } + CLK = { CP2 | CP1 } * U1 DFF(8) DPWR DGND $D_HI MRBAR CLK + D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * UF166DLY PINDLY (1,0,14) DPWR DGND + Q7 + MRBAR CP1 CP2 PEBAR DS P0 P1 P2 P3 P4 P5 P6 P7 CLK + Q7_O ;CP2 IS USED AS CLOCK INPUT (CP) + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLK = { (CHANGED_LH(CP2,0) & CP1!='1) } + + PINDLY: + Q7_O = { + CASE( + CLK & TRN_HL, DELAY(3.5NS,6NS,9NS), + CHANGED_HL(MRBAR,0) & TRN_HL, DELAY(4NS,6.5NS,9.5NS), + CLK & TRN_LH, DELAY(5NS,7.5NS,12NS), + DELAY(6NS,8NS,13NS) ;DEFAULT + ) + } + ;CP1 IS USED AS CLOCK INHIBIT (CEBAR) + ;CP2 IS USED AS CLOCK INPUT (CP) + + BOOLEAN: + NOTCLR_AND_EN = { MRBAR!='0 & CP1!='1 } + + FREQ: + NODE = CLK + MAXFREQ = 110MEG + + WIDTH: + NODE = CLK + MIN_HI = 3.5NS + MIN_LO = 5.0NS + + WIDTH: + NODE = MRBAR + MIN_LO = 4NS + + SETUP_HOLD: ;CHECK PEBAR SETUP TIME + DATA(1) PEBAR ;TO CLOCK OF FLIP FLOPS + CLOCK LH = CLK + SETUPTIME = 4NS + WHEN = { MRBAR!='0 } + + SETUP_HOLD: ;CHECK PARALLEL DATA + DATA(8) P0 P1 P2 P3 P4 P5 P6 P7 ;WHEN IN LOAD MODE + CLOCK LH = CP2 ;CLK = CP2 & CLK_INHIBIT = CP1 = L + SETUPTIME_HI = 4NS + SETUPTIME_LO = 3NS + HOLDTIME_HI = 1NS + WHEN = { NOTCLR_AND_EN & (PEBAR!='1 ^ CHANGED(PEBAR,0)) } + + SETUP_HOLD: ;CHECK PARALLEL DATA + DATA(8) P0 P1 P2 P3 P4 P5 P6 P7 ;IN ENABLE MODE + CLOCK LH = CP1 ;CLK_INHIBIT = CP1 = L TO H + SETUPTIME_HI = 4NS + SETUPTIME_LO = 3NS + HOLDTIME_HI = 2NS + WHEN = { MRBAR!='0 & (PEBAR!='1 ^ CHANGED(PEBAR,0)) } + + SETUP_HOLD: ;CHECK SERIAL DATA + DATA(1) DS ;WHEN IN SHIFT MODE + CLOCK LH = CP2 ;CLK = CP2 & CLK_INHIBIT = CP1 = L + SETUPTIME_HI = 4NS + SETUPTIME_LO = 3NS + HOLDTIME_HI = 1NS + WHEN = { NOTCLR_AND_EN & (PEBAR!='0 ^ CHANGED(PEBAR,0)) } + + SETUP_HOLD: ;CHECK SERIAL DATA + DATA(1) DS ;IN ENABLE MODE + CLOCK LH = CP1 ;CLK_INHIBIT = CP1 = L TO H + SETUPTIME_HI = 4NS + SETUPTIME_LO = 3NS + HOLDTIME_HI = 2NS + WHEN = { MRBAR!='0 & (PEBAR!='0 ^ CHANGED(PEBAR,0)) } + + SETUP_HOLD: + DATA(1) MRBAR + CLOCK LH = CP2 + RELEASETIME_LH = 4.5NS + WHEN = { CP1!='1 } + + SETUP_HOLD: ;CLOCK = CP2 + DATA(1) CP1 ;CLOCK INHIBIT = CP1 + CLOCK LH = CP2 + SETUPTIME_LO = 6NS * .ENDS * *$ *--------- * 74F168 Synchronous 4-bit Up/Down Decade Counters * * The FAST Data Book, 1989, TI * JSW 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * NOTICE: The logic for this device was copied from the ALS device * .SUBCKT 74F168 CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I + A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF168LOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D RCOBAR DA DB DC DD EN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UD = { ~U/DBAR } + LOAD = { ~LOADBAR } + EN = { ~ENTBAR & ~ENPBAR & LOADBAR } + IA4 = { ~((QABAR & U/DBAR) | (QA & UD)) } + IB4 = { ~((QBBAR & U/DBAR) | (QB & UD)) } + IC4 = { ~((QCBAR & U/DBAR) | (QC & UD)) } + ID4 = { ~((QDBAR & U/DBAR) | (QD & UD)) } + IB5 = { ~(U/DBAR & ID4) } + IC5 = { ~(QCBAR & UD & QDBAR) } + IA1 = { A & LOAD } + IA2 = { EN ^ ( LOADBAR & QA) } + IB1 = { B & LOAD } + IB2 = { ~(EN & IA4) & LOADBAR & QB } + IB3 = { IA4 & EN & IC5 & IB5 & QBBAR } + IC1 = { C & LOAD } + IC2 = { ~(EN & IA4 & IB4) & LOADBAR & QC } + IC3 = { ~(QC & LOADBAR) & EN & IA4 & IB4 & IC5 } + ID1 = { D & LOAD } + ID2 = { ~(EN & IA4) & LOADBAR & QD } + ID3 = { ~(QD & LOADBAR) & EN & IA4 & IB4 & IC4 } + DA = { IA1 | IA2 } + DB = { IB1 | IB2 | IB3 } + DC = { IC1 | IC2 | IC3 } + DD = { ID1 | ID2 | ID3 } + RCOBAR = { ~((U/DBAR & IA4 & ID4 & ~ENTBAR) | (~ENTBAR & UD & + IA4 & IB4 & IC4 & ID4)) } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_F * UF168DLY PINDLY (5,0,10) DPWR DGND + RCOBAR QA QB QC QD + CLK ENPBAR ENTBAR U/DBAR LOADBAR A B C D EN + RCOBAR_O QA_O QB_O QC_O QD_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENTBAR,0) } + PINDLY: + RCOBAR_O = { + CASE( + CNTENT & TRN_LH, DELAY(2.5NS,4.5NS,7NS), + CNTENT & TRN_HL, DELAY(2.5NS,6NS,9NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(3.5NS,8.5NS,12.5NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(4NS,12.5NS,17.5NS), + CLOCK & TRN_LH, DELAY(5.5NS,12NS,17NS), + CLOCK & TRN_HL, DELAY(4NS,8NS,12.5NS), + DELAY(5.5NS,12.5NS,17.5NS) + ) + } + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(3NS,6.5NS,9.5NS), + CLOCK & TRN_HL, DELAY(4NS,9NS,13NS), + DELAY(4NS,9NS,13NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_LOW = 5.5NS + MIN_HIGH = 5.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 4.5NS + HOLDTIME = 3.5NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 5.5NS + WHEN = { CHANGED(EN,5.5NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 9NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME_HI = 12.5NS + SETUPTIME_LO = 18NS + WHEN = { EN!='0 ^ CHANGED(EN,0) } * .ENDS * *$ *--------- * 74F169 Synchronous 4-Bit Up/Down Binary Counter * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTOR * tc 07/21/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F169 CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_F * UF169LOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D DA DB DC DD RCOBAR IEN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + U/DBAR = { U/DBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { ~(ENPBAR | ENTBAR) } + UP = { U/DBAR } + DN = { ~U/DBAR } + IA1 = { UP | DN } + IA2 = { ~((QA ^ ~(IA1 & IEN)) & LOADBAR) } + IA3 = { A | LOADBAR } + IB1 = { (QA & UP) | (QABAR & DN) } + IB2 = { ~((QB ^ ~(IB1 & IEN)) & LOADBAR) } + IB3 = { B | LOADBAR } + IC1 = { (QA & QB & UP) | (QABAR & QBBAR & DN) } + IC2 = { ~((QC ^ ~(IC1 & IEN)) & LOADBAR) } + IC3 = { C | LOADBAR } + ID1 = { (QA & QB & QC & UP) | (QABAR & QBBAR & QCBAR & DN) } + ID2 = { ~((QD ^ ~(ID1 & IEN)) & LOADBAR) } + ID3 = { D | LOADBAR } + IRC1 = { QA & QB & QC & QD & UP & ~ENTBAR } + IRC2 = { QABAR & QBBAR & QCBAR & QDBAR & DN & ~ENTBAR } + DA = { IA2 & IA3 } + DB = { IB2 & IB3 } + DC = { IC2 & IC3 } + DD = { ID2 & ID3 } + RCOBAR = { ~(IRC1 | IRC2) } * UF169DLY PINDLY (5,0,10) DPWR DGND + QA QB QC QD RCOBAR + CLK ENTBAR U/DBAR ENPBAR LOADBAR A B C D IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(3NS,6.5NS,9.5NS), + DELAY(4NS,9NS,13NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0) & TRN_LH, DELAY(2.5NS,4.5NS,7NS), + CHANGED(ENTBAR,0) & TRN_HL, DELAY(2.5NS,6NS,9NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(4NS,8NS,12NS), + CLOCK & TRN_HL, DELAY(4NS,8.5NS,12.5NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(3.5NS,8.5NS,15.5NS), + CLOCK & TRN_LH, DELAY(5.5NS,12NS,17NS), + DELAY(5.5NS,12NS,17NS) + ) + } + BOOLEAN: + NOTLOADING = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + ENABLE = { (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_LO = 5.5NS + MIN_HI = 5.5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 4.5NS + HOLDTIME = 3.5NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 5.5NS + WHEN = { NOTLOADING & CHANGED(IEN,5.5NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 9NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME_LO = 8NS + SETUPTIME_HI = 12.5NS + WHEN = { NOTLOADING & ENABLE } * .ENDS * *$ *--------- * 74F173 REGISTERS D-TYPE 4-BIT WITH 3-STATE OUTPUTS * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 7-9-92 REMODELED USIN * .SUBCKT 74F173 MR_I CP_I E0BAR_I E1BAR_I OE0BAR_I OE1BAR_I + D0_I D1_I D2_I D3_I Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND + $D_HI MRBAR CP + DFF1 DFF2 DFF3 DFF4 + Q0 Q1 Q2 Q3 + $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * UF173LOG LOGICEXP (14,13) DPWR DGND + MR_I CP_I E0BAR_I E1BAR_I OE0BAR_I OE1BAR_I D0_I D1_I D2_I D3_I Q0 Q1 Q2 Q3 + MR MRBAR CP DATEN OE D0 D1 D2 D3 + DFF1 DFF2 DFF3 DFF4 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + MR = { MR_I } + MRBAR = { ~MR } + CP = { CP_I } + E0BAR = { E0BAR_I } + E1BAR = { E1BAR_I } + OE0BAR = { OE0BAR_I } + OE1BAR = { OE1BAR_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + + DATENBAR = { E0BAR | E1BAR } + DATEN = { ~DATENBAR } + OE = { ~(OE0BAR | OE1BAR) } + DFF1 = { (D0 & DATEN) | (Q0 & DATENBAR) } + DFF2 = { (D1 & DATEN) | (Q1 & DATENBAR) } + DFF3 = { (D2 & DATEN) | (Q2 & DATENBAR) } + DFF4 = { (D3 & DATEN) | (Q3 & DATENBAR) } * UF173DLY PINDLY (4,1,7) DPWR DGND + Q0 Q1 Q2 Q3 + OE + CP MR DATEN D0 D1 D2 D3 + Q0_O Q1_O Q2_O Q3_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED = { CHANGED_LH(CP,0) } + + TRISTATE: + ENABLE HI OE + Q0_O Q1_O Q2_O Q3_O = { + CASE ( + TRN_ZH, DELAY(2.5NS,5.0NS, 8.5NS), + TRN_ZL, DELAY(4.5NS,7.0NS,11.0NS), + TRN_HZ, DELAY(1.0NS,3.5NS, 8.0NS), + TRN_LZ, DELAY(2.5NS,5.0NS, 9.0NS), + TRN_LH, DELAY(4.0NS,6.5NS,10.0NS), + CLOCKED & TRN_HL, DELAY(5.5NS,8.0NS,11.5NS), + DELAY(6NS,8.5NS,12.5NS) + ) + } + + FREQ: + NODE = CP + MAXFREQ = 90MEGHZ + WIDTH: + NODE = CP + MIN_LO = 6NS + MIN_HI = 3NS + WIDTH: + NODE = MR + MIN_HI = 3.5NS + SETUP_HOLD: + DATA(1) = MR + CLOCK LH = CP + RELEASETIME_HL = 5.5NS + SETUP_HOLD: + DATA(1) = DATEN + CLOCK LH = CP + SETUPTIME_HI = 5.0NS + SETUPTIME_LO = 8.5NS + WHEN = { MR!='1 } + SETUP_HOLD: + DATA(4) = D0 D1 D2 D3 + CLOCK LH = CP + SETUPTIME_HI = 3NS + SETUPTIME_LO = 4NS + WHEN = { MR!='1 & (DATEN!='0 ^ CHANGED(DATEN,0)) } * .ENDS * *$ *---------- * 74F174 HEX D-TYPE FLIP-FLOPS WITH CLEAR * * F Logic Data Book, TI, 1987 * tvh 06/27/89 Update interface and model names * .subckt 74F174 CLRBAR CLK D1 D2 D3 D4 D5 D6 Q1 Q2 Q3 Q4 Q5 Q6 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(6) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 + Q1 Q2 Q3 Q4 Q5 Q6 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_F174 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F174 ueff ( + TWCLKLMN=6NS TWCLKHMN=4NS + TWPCLMN=5NS TSUDCLKMN=4NS + TSUPCCLKHMN=5NS TPPCQHLMN=4.2NS + TPPCQHLMX=15NS TPCLKQLHMN=2.7NS + TPCLKQLHMX=9NS TPCLKQHLMN=3.7NS + TPCLKQHLMX=11NS + ) *$ *---------- * 74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR * * F Logic Data Book, TI, 1987 * tvh 06/27/89 Update interface and model names * .subckt 74F175 CLRBAR CLK D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(4) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 + Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + D_F175 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F175 ueff ( + TWCLKLMN=5NS TWCLKHMN=4NS + TWPCLMN=5NS TSUDCLKMN=3NS + TSUPCCLKHMN=5NS THDCLKMN=1NS + TPPCQLHMN=3.2NS TPPCQLHMX=9NS + TPPCQHLMN=3.7NS TPPCQHLMX=13NS + TPCLKQLHMN=3.2NS TPCLKQLHMX=7.5NS + TPCLKQHLMN=3.2NS TPCLKQHLMX=9.5NS + ) *$ *--------- * 74F181 ALU / FUNCTION GENERATOR * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE: IN THE DATABOOK, THE LOGIC FOR THE 74F181 WAS DIAGRAMMED WITH A * NOT-AND GATE INSTEAD OF AN XOR GATE AS IN THE OTHER FAMILIES. BOTH VERSIONS * ARE FUNCTIONALLY CORRECT. HOWEVER, THE F181 WAS MODELLED HERE WITH AN XOR. .SUBCKT 74F181 A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I + B3BAR_I S0_I S1_I S2_I S3_I M_I CN_I F0BAR_O F1BAR_O F2BAR_O F3BAR_O + AEQUALB_O PBAR_O GBAR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UF181LOG LOGICEXP (14,22) DPWR DGND + A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I B3BAR_I + S0_I S1_I S2_I S3_I M_I CN_I + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR + S0 S1 S2 S3 M CN + F0BAR F1BAR F2BAR F3BAR AEQUALB PBAR GBAR CN+4 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + A0BAR = { A0BAR_I } + A1BAR = { A1BAR_I } + A2BAR = { A2BAR_I } + A3BAR = { A3BAR_I } + B0BAR = { B0BAR_I } + B1BAR = { B1BAR_I } + B2BAR = { B2BAR_I } + B3BAR = { B3BAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + S3 = { S3_I } + M = { M_I } + CN = { CN_I } + + TOP3 = { ~( (A3BAR & B3BAR & S3) | (A3BAR & ~B3BAR & S2) ) } + BOT3 = { ~( (~B3BAR & S1) | A3BAR | (B3BAR & S0) ) } + TOP2 = { ~( (A2BAR & B2BAR & S3) | (A2BAR & ~B2BAR & S2) ) } + BOT2 = { ~( (~B2BAR & S1) | A2BAR | (B2BAR & S0) ) } + TOP1 = { ~( (A1BAR & B1BAR & S3) | (A1BAR & ~B1BAR & S2) ) } + BOT1 = { ~( (~B1BAR & S1) | A1BAR | (B1BAR & S0) ) } + TOP0 = { ~( (A0BAR & B0BAR & S3) | (A0BAR & ~B0BAR & S2) ) } + BOT0 = { ~( (~B0BAR & S1) | A0BAR | (B0BAR & S0) ) } + MBAR = { ~M } + + F3BAR = { (TOP3 ^ BOT3) ^ ~( ( CN & MBAR & TOP2 & TOP1 & TOP0) | + (BOT0 & MBAR & TOP2 & TOP1) | + (BOT1 & MBAR & TOP2) | + (BOT2 & MBAR) ) } + F2BAR = { (TOP2 ^ BOT2) ^ ~( ( CN & MBAR & TOP1 & TOP0) | + (BOT0 & MBAR & TOP1) | + (BOT1 & MBAR) ) } + F1BAR = { (TOP1 ^ BOT1) ^ ~( ( CN & MBAR & TOP0) | + (BOT0 & MBAR) ) } + F0BAR = { (TOP0 ^ BOT0) ^ ~( CN & MBAR) } + AEQUALB = { F3BAR & F2BAR & F1BAR & F0BAR } + PBAR = { ~( TOP3 & TOP2 & TOP1 & TOP0) } + GBAR = { ~( (BOT0 & TOP3 & TOP2 & TOP1) | + (BOT1 & TOP3 & TOP2) | + (BOT2 & TOP3) | + BOT3 ) } + CN+4 = { ~GBAR | (~PBAR & CN) } UF181DLY PINDLY (7,0,14) DPWR DGND + F0BAR F1BAR F2BAR F3BAR PBAR GBAR CN+4 + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M CN + F0BAR_O F1BAR_O F2BAR_O F3BAR_O PBAR_O GBAR_O CN+4_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + NOTM = { M=='0 } + CARRY = { CHANGED(CN,0) & NOTM } + MODE = { CHANGED(S3,0) | CHANGED(S2,0) | + CHANGED(S1,0) | CHANGED(S0,0) } + SUM = { S0=='1 & S1=='0 & S2=='0 & S3=='1 } + DIF = { S0=='0 & S1=='1 & S2=='1 & S3=='0 } + LOGLHSUM = { CHANGED_LH(M,0) & SUM } + LOGHLSUM = { CHANGED_HL(M,0) & SUM } + LOGLHDIF = { CHANGED_LH(M,0) & DIF } + LOGHLDIF = { CHANGED_HL(M,0) & DIF } + SUMNOTM = { SUM & NOTM } + DIFNOTM = { DIF & NOTM } + OPER3 = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) } + OPER2 = { CHANGED(A2BAR,0) | CHANGED(B2BAR,0) } + OPER1 = { CHANGED(A1BAR,0) | CHANGED(B1BAR,0) } + OPER0 = { CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + OPER = { OPER3 | OPER2 | OPER1 | OPER0 } + + PINDLY: + F3BAR_O = { + CASE ( + CARRY & TRN_LH, DELAY(3.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(2.5NS,5.0NS, 9.0NS), + MODE , DELAY(3.0NS,5.5NS, 9.5NS), + LOGLHSUM & TRN_LH, DELAY(4.5NS,7.0NS,11.0NS), + LOGHLSUM & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLSUM & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHSUM & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_LH, DELAY(4.0NS,7.0NS,11.5NS), + LOGHLDIF & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLDIF & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + OPER3 & SUMNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 8.5NS), + OPER3 & SUMNOTM & TRN_HL, DELAY(3.0NS,4.5NS, 8.5NS), + OPER3 & DIFNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 9.0NS), + OPER3 & DIFNOTM & TRN_HL, DELAY(3.0NS,5.0NS, 9.0NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.0NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.5NS,6.5NS,11.0NS), + OPER & DIFNOTM & TRN_HL, DELAY(4.5NS,7.0NS,11.0NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,5.5NS, 9.5NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,5.5NS,10.5NS), + DELAY(4.5NS,7.0NS,11.5NS) + ) + } + F2BAR_O = { + CASE ( + CARRY & TRN_LH, DELAY(3.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(2.5NS,5.0NS, 9.0NS), + MODE , DELAY(3.0NS,5.5NS, 9.5NS), + LOGLHSUM & TRN_LH, DELAY(4.5NS,7.0NS,11.0NS), + LOGHLSUM & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLSUM & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHSUM & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_LH, DELAY(4.0NS,7.0NS,11.5NS), + LOGHLDIF & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLDIF & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + OPER2 & SUMNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 8.5NS), + OPER2 & SUMNOTM & TRN_HL, DELAY(3.0NS,4.5NS, 8.5NS), + OPER2 & DIFNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 9.0NS), + OPER2 & DIFNOTM & TRN_HL, DELAY(3.0NS,5.0NS, 9.0NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.0NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.5NS,6.5NS,11.0NS), + OPER & DIFNOTM & TRN_HL, DELAY(4.5NS,7.0NS,11.0NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,5.5NS, 9.5NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,5.5NS,10.5NS), + DELAY(4.5NS,7.0NS,11.5NS) + ) + } + F1BAR_O = { + CASE ( + CARRY & TRN_LH, DELAY(3.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(2.5NS,5.0NS, 9.0NS), + MODE , DELAY(3.0NS,5.5NS, 9.5NS), + LOGLHSUM & TRN_LH, DELAY(4.5NS,7.0NS,11.0NS), + LOGHLSUM & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLSUM & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHSUM & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_LH, DELAY(4.0NS,7.0NS,11.5NS), + LOGHLDIF & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLDIF & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + OPER1 & SUMNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 8.5NS), + OPER1 & SUMNOTM & TRN_HL, DELAY(3.0NS,4.5NS, 8.5NS), + OPER1 & DIFNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 9.0NS), + OPER1 & DIFNOTM & TRN_HL, DELAY(3.0NS,5.0NS, 9.0NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.0NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.5NS,6.5NS,11.0NS), + OPER & DIFNOTM & TRN_HL, DELAY(4.5NS,7.0NS,11.0NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,5.5NS, 9.5NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,5.5NS,10.5NS), + DELAY(4.5NS,7.0NS,11.5NS) + ) + } + F0BAR_O = { + CASE ( + CARRY & TRN_LH, DELAY(3.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(2.5NS,5.0NS, 9.0NS), + MODE , DELAY(3.0NS,5.5NS, 9.5NS), + LOGLHSUM & TRN_LH, DELAY(4.5NS,7.0NS,11.0NS), + LOGHLSUM & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLSUM & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHSUM & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_LH, DELAY(4.0NS,7.0NS,11.5NS), + LOGHLDIF & TRN_HL, DELAY(4.0NS,6.0NS,10.0NS), + LOGHLDIF & TRN_LH, DELAY(3.5NS,6.0NS, 9.5NS), + LOGLHDIF & TRN_HL, DELAY(3.5NS,6.0NS, 9.5NS), + OPER0 & SUMNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 8.5NS), + OPER0 & SUMNOTM & TRN_HL, DELAY(3.0NS,4.5NS, 8.5NS), + OPER0 & DIFNOTM & TRN_LH, DELAY(2.5NS,4.5NS, 9.0NS), + OPER0 & DIFNOTM & TRN_HL, DELAY(3.0NS,5.0NS, 9.0NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.0NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.5NS,6.5NS,11.0NS), + OPER & DIFNOTM & TRN_HL, DELAY(4.5NS,7.0NS,11.0NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,5.5NS, 9.5NS), + OPER & M=='1 & TRN_HL, DELAY(3.0NS,5.5NS,10.5NS), + DELAY(4.5NS,7.0NS,11.5NS) + ) + } + PBAR_O = { + CASE ( + OPER & SUM & TRN_LH, DELAY(2.0NS,4.0NS,7.5NS), + OPER & SUM & TRN_HL, DELAY(2.5NS,4.5NS,8.0NS), + OPER & DIF & TRN_LH, DELAY(2.0NS,4.0NS,8.0NS), + OPER & DIF & TRN_HL, DELAY(2.5NS,5.0NS,9.0NS), + MODE & TRN_LH, DELAY(2.5NS,4.0NS,7.0NS), + MODE & TRN_HL, DELAY(2.5NS,4.5NS,8.0NS), + DELAY(2.5NS,5.0NS,9.0NS) + ) + } + GBAR_O = { + CASE ( + OPER & SUM & TRN_LH, DELAY(2.5NS,5.0NS,8.0NS), + OPER & SUM & TRN_HL, DELAY(2.5NS,5.0NS,8.0NS), + OPER & DIF & TRN_LH, DELAY(2.5NS,4.5NS,9.0NS), + OPER & DIF & TRN_HL, DELAY(2.5NS,5.0NS,9.5NS), + MODE & TRN_LH, DELAY(2.5NS,5.0NS,8.0NS), + MODE & TRN_HL, DELAY(2.5NS,4.0NS,8.0NS), + DELAY(2.5NS,5.0NS,9.5NS) + ) + } + CN+4_O = { + CASE ( + CARRY & TRN_LH, DELAY(3.0NS,5.0NS, 8.5NS), + CARRY & TRN_HL, DELAY(2.5NS,5.0NS, 8.5NS), + OPER & SUM & TRN_LH, DELAY(5.0NS,9.0NS,13.0NS), + OPER & SUM & TRN_HL, DELAY(5.0NS,8.0NS,12.5NS), + OPER & DIF & TRN_LH, DELAY(5.0NS,9.5NS,14.0NS), + OPER & DIF & TRN_HL, DELAY(5.0NS,8.0NS,12.5NS), + MODE & TRN_LH, DELAY(3.0NS,7.0NS,12.5NS), + MODE & TRN_HL, DELAY(2.5NS,5.5NS,10.0NS), + DELAY(5.0NS,9.5NS,14.0NS) + ) + } UF181DLY_OC PINDLY (1,0,13) DPWR DGND + AEQUALB + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M + AEQUALB_O + IO_F_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + LOGLH = { CHANGED_LH(M,0) } + LOGHL = { CHANGED_HL(M,0) } + MODE = { CHANGED(S3,0) | CHANGED(S2,0) | CHANGED(S1,0) | CHANGED(S0,0) } + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + SUM = { NOTM & S0=='1 & S1=='0 & S2=='0 & S3=='1 } + DIF = { NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + AEQUALB_O = { + CASE ( + OPER & TRN_LH, DELAY( 9.5NS,14.0NS,20.5NS), + OPER & TRN_HL, DELAY( 5.5NS, 8.5NS,12.5NS), + MODE & TRN_LH, DELAY(10.5NS,16.5NS,24.0NS), + MODE & TRN_HL, DELAY( 6.0NS, 8.5NS,13.5NS), + SUM & LOGHL & TRN_LH, DELAY(11.0NS,16.0NS,22.0NS), + SUM & LOGLH & TRN_HL, DELAY( 6.0NS, 8.0NS,11.0NS), + SUM & LOGLH & TRN_LH, DELAY(12.0NS,17.0NS,24.0NS), + SUM & LOGHL & TRN_HL, DELAY( 6.0NS, 8.0NS,11.5NS), + DIF & LOGHL & TRN_LH, DELAY(10.5NS,16.0NS,22.0NS), + DIF & LOGLH & TRN_HL, DELAY( 6.0NS, 8.0NS,11.0NS), + DIF & LOGLH & TRN_LH, DELAY(12.5NS,17.0NS,24.0NS), + DIF & LOGHL & TRN_HL, DELAY( 6.0NS, 8.0NS,11.5NS), + DELAY(12.5NS,17.0NS,24.0NS) + ) + } .ENDS *$ *--------- * 74F182 LOOK-AHEAD CARRY GENERATOR * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-17-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F182 G3BAR_I G2BAR_I G1BAR_I G0BAR_I + P3BAR_I P2BAR_I P1BAR_I P0BAR_I CN_I GBAR_O PBAR_O CN+X_O CN+Y_O CN+Z_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF182LOG LOGICEXP (9,14) DPWR DGND + G3BAR_I G2BAR_I G1BAR_I G0BAR_I P3BAR_I P2BAR_I P1BAR_I P0BAR_I CN_I + G3BAR G2BAR G1BAR G0BAR P3BAR P2BAR P1BAR P0BAR CN + GBAR PBAR CN+X CN+Y CN+Z + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + G3BAR = { G3BAR_I } + G2BAR = { G2BAR_I } + G1BAR = { G1BAR_I } + G0BAR = { G0BAR_I } + P3BAR = { P3BAR_I } + P2BAR = { P2BAR_I } + P1BAR = { P1BAR_I } + P0BAR = { P0BAR_I } + CN = { CN_I } + CNBAR = { ~CN } + PBAR = { P0BAR | P1BAR | P2BAR | P3BAR } + GBAR = { ( G0BAR & G1BAR & G2BAR & G3BAR) | + (P1BAR & G1BAR & G2BAR & G3BAR) | + (P2BAR & G2BAR & G3BAR) | + (P3BAR & G3BAR) } + CN+Z = { ~( (CNBAR & G0BAR & G1BAR & G2BAR) | + (P0BAR & G0BAR & G1BAR & G2BAR) | + (P1BAR & G1BAR & G2BAR) | + (P2BAR & G2BAR) ) } + CN+Y = { ~( (CNBAR & G0BAR & G1BAR) | + (P0BAR & G0BAR & G1BAR) | + (P1BAR & G1BAR) ) } + CN+X = { ~( (CNBAR & G0BAR) | + (P0BAR & G0BAR) ) } * UF182DLY PINDLY (5,0,9) DPWR DGND + GBAR PBAR CN+X CN+Y CN+Z + G3BAR G2BAR G1BAR G0BAR P3BAR P2BAR P1BAR P0BAR CN + GBAR_O PBAR_O CN+X_O CN+Y_O CN+Z_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + GENER = { CHANGED(G2BAR,0) | CHANGED(G1BAR,0) | CHANGED(G0BAR,0) } + PROP012 = { CHANGED(P2BAR,0) | CHANGED(P1BAR,0) | CHANGED(P0BAR,0) } + PROP123 = { CHANGED(P3BAR,0) | CHANGED(P2BAR,0) | CHANGED(P1BAR,0) } + + PINDLY: + GBAR_O = { + CASE ( + PROP123 & TRN_LH, DELAY(1.5NS,7.0NS,11.0NS), + TRN_HL, DELAY(2.5NS,5.0NS, 8.0NS), + (GENER | CHANGED(G3BAR,0)) & TRN_LH, DELAY(1.5NS,5.0NS, 7.5NS), + DELAY(1.5NS,7.0NS,11.0NS) + ) + } + PBAR_O = { + CASE ( + TRN_LH, DELAY(1.5NS,3.5NS,7.5NS), + TRN_HL, DELAY(2.5NS,4.0NS,6.5NS), + DELAY(1.5NS,3.5NS,7.5NS) + ) + } + CN+X_O CN+Y_O CN+Z_O = { + CASE ( + CHANGED(CN,0) , DELAY(2.5NS,5.0NS,8.5NS), + GENER & TRN_LH, DELAY(1.5NS,4.0NS,8.5NS), + PROP012 & TRN_LH, DELAY(1.5NS,5.0NS,8.0NS), + PROP012 & TRN_HL, DELAY(1.5NS,3.5NS,6.0NS), + GENER & TRN_HL, DELAY(1.5NS,3.0NS,5.5NS), + DELAY(2.5NS,5.0NS,8.5NS) + ) + } * .ENDS * *$ *--------- * 74F190 Synchronous 4-bit Up/Down Decade Counters * * FAST Logic Data Handbook, 1989, PHILIPS SEMICONDUCTORS * JSW 7/17/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F190 CP_I UBAR/D_I CEBAR_I PLBAR_I P0_I P1_I P2_I P3_I + RCBAR_O TC_O Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF190 LOGICEXP (16,23) DPWR DGND + CP_I UBAR/D_I CEBAR_I PLBAR_I P0_I P1_I P2_I P3_I Q0 Q1 Q2 Q3 Q0BAR + Q1BAR Q2BAR Q3BAR + CP CPBAR UBAR/D CEBAR PLBAR P0 P1 P2 P3 TC RCBAR + S0 R0 JK0 S1 R1 JK1 S2 R2 JK2 S3 R3 JK3 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + CP = { CP_I } + CPBAR = { ~CP_I } + UBAR/D = { UBAR/D_I } + CEBAR = { CEBAR_I } + PLBAR = { PLBAR_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + DU = { ~UBAR/D } + PL = { ~PLBAR } + CE = { ~CEBAR } + CTD = { UBAR/D & CE } + CTU = { DU & CE } + TC = { (Q0 & Q3 & DU) | (Q0BAR & Q1BAR & Q2BAR & + Q3BAR & UBAR/D) } + RCBAR = { ~(TC & CE & CPBAR) } + S0 = { ~(P0 & PL) } + R0 = { ~(S0 & PL) } + JK0 = { CE } + S1 = { ~(P1 & PL) } + R1 = { ~(S1 & PL) } + I1 = { ~(Q1BAR & Q2BAR & Q3BAR) } + JK1 = { (CTD & Q0BAR & I1) | (Q0 & Q3BAR & CTU) } + S2 = { ~(P2 & PL) } + R2 = { ~(S2 & PL) } + JK2 = { (CTD & Q0BAR & Q1BAR & I1) | (CTU & Q1 & Q0) } + S3 = { ~(P3 & PL) } + R3 = { ~(S3 & PL) } + JK3 = { (CTD & Q0BAR & Q1BAR & Q2BAR) | (CTU & Q3 & Q0) | + (CTU & Q2 & Q1 & Q0) } * UJKFF0 JKFF(1) DPWR DGND S0 R0 CPBAR JK0 JK0 Q0 Q0BAR D0_EFF IO_F UJKFFB JKFF(1) DPWR DGND S1 R1 CPBAR JK1 JK1 Q1 Q1BAR D0_EFF IO_F UJKFFC JKFF(1) DPWR DGND S2 R2 CPBAR JK2 JK2 Q2 Q2BAR D0_EFF IO_F UJKFFD JKFF(1) DPWR DGND S3 R3 CPBAR JK3 JK3 Q3 Q3BAR D0_EFF IO_F * UF190DLY PINDLY (6,0,8) DPWR DGND + Q0 Q1 Q2 Q3 RCBAR TC + P0 P1 P2 P3 CP UBAR/D CEBAR PLBAR + Q0_O Q1_O Q2_O Q3_O RCBAR_O TC_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { (CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | + CHANGED(P3,0)) & PLBAR!='1 } + CLOCK_LH = { CHANGED_LH(CP,0) & TRN_LH } + CLOCK_HL = { CHANGED_LH(CP,0) & TRN_HL } + PINDLY: + Q0_O Q1_O Q2_O Q3_O = { + CASE( + DATA & TRN_LH, DELAY(1.5NS,4NS,7.5NS), + CLOCK_LH, DELAY(2NS,4.5NS,8.5NS), + CHANGED_HL(PLBAR,0) & TRN_LH, DELAY(4NS,6.5NS,10.5NS), + CLOCK_HL, DELAY(5NS,7.5NS,12NS), + CHANGED_HL(PLBAR,0) & TRN_HL, DELAY(5NS,8NS,12NS), + DATA & TRN_HL, DELAY(6.5NS,9NS,13NS), + DELAY(7NS,10NS,14NS) + ) + } + RCBAR_O = { + CASE( + CHANGED(CEBAR,0) & TRN_LH, DELAY(2NS,4NS,7.5NS), + CHANGED(CEBAR,0) & TRN_HL, DELAY(3NS,5NS,8NS), + CLOCK_LH, DELAY(2NS,4.5NS,8NS), + CHANGED(CP,0) & TRN_HL, DELAY(2.5NS,5NS,8NS), + CHANGED(UBAR/D,0) & TRN_HL, DELAY(4NS,7.5NS,11NS), + CHANGED(UBAR/D,0) & TRN_LH, DELAY(8NS,11NS,17NS), + CHANGED(PLBAR,0) & TRN_HL, DELAY(7NS,10NS,13.5NS), + CHANGED(PLBAR,0) & TRN_LH, DELAY(8.5NS,16NS,21NS), + DATA & TRN_LH, DELAY(6NS,14NS,19.5NS), + DATA & TRN_HL, DELAY(6NS,11NS,15NS), + DELAY(9NS,14NS,20NS) + ) + } + TC_O = { + CASE( + CHANGED(UBAR/D,0) & TRN_LH, DELAY(3NS,6.5NS,10.5NS), + CHANGED(UBAR/D,0) & TRN_HL, DELAY(3NS,6NS,10NS), + CLOCK_HL, DELAY(6NS,8NS,12NS), + CLOCK_LH, DELAY(6NS,9NS,13NS), + CHANGED(PLBAR,0) & TRN_LH, DELAY(5.5NS,8.5NS,13NS), + CHANGED(PLBAR,0) & TRN_HL, DELAY(6NS,10.5NS,14.5NS), + DATA & TRN_LH, DELAY(5NS,9.5NS,14NS), + DATA & TRN_HL, DELAY(6NS,9.5NS,14NS), + DELAY(7NS,11NS,15NS) + ) + } + FREQ: + NODE = CP + MAXFREQ = 90MEG + WIDTH: + NODE = CP + MIN_LO = 6NS + MIN_HI = 3.5NS + WIDTH: + NODE = PLBAR + MIN_LO = 6NS + SETUP_HOLD: + CLOCK LH = CP + DATA(1) CEBAR + SETUPTIME_LO = 10NS + WHEN = { PLBAR!='0 } + SETUP_HOLD: + DATA(1) UBAR/D + CLOCK LH = CP + SETUPTIME = 12NS + WHEN = { PLBAR!='0 & (CEBAR!='1 ^ CHANGED(CEBAR,0)) } + SETUP_HOLD: + DATA(1) = PLBAR + CLOCK LH = CP + RELEASETIME_LH = 6NS + SETUP_HOLD: + DATA(4) = P0 P1 P2 P3 + CLOCK LH = PLBAR + SETUPTIME = 5NS + HOLDTIME = 2NS * .ENDS * *$ *--------- * 74F191 Synchronous 4-bit Up/Down Binary Counters * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTOR * tc 7/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F191 CP_I UBAR/D_I CEBAR_I PLBAR_I P0_I P1_I P2_I P3_I + RCBAR_O TC_O Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND S0 R0 MCP JK0 JK0 Q0 Q0BAR + D0_EFF IO_F U2 JKFF(1) DPWR DGND S1 R1 MCP JK1 JK1 Q1 Q1BAR + D0_EFF IO_F U3 JKFF(1) DPWR DGND S2 R2 MCP JK2 JK2 Q2 Q2BAR + D0_EFF IO_F U4 JKFF(1) DPWR DGND S3 R3 MCP JK3 JK3 Q3 Q3BAR + D0_EFF IO_F * UF191LOG LOGICEXP (16,23) DPWR DGND + CP_I UBAR/D_I CEBAR_I PLBAR_I P0_I P1_I P2_I P3_I Q0 Q1 Q2 Q3 + Q0BAR Q1BAR Q2BAR Q3BAR + CP UBAR/D CEBAR PLBAR P0 P1 P2 P3 TC RCBAR MCP + S0 R0 JK0 S1 R1 JK1 S2 R2 JK2 S3 R3 JK3 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CP = { CP_I } + UBAR/D = { UBAR/D_I } + CEBAR = { CEBAR_I } + PLBAR = { PLBAR_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + IEN1 = { ~(UBAR/D | CEBAR) } + IEN2 = { ~(CEBAR | ~UBAR/D) } + ILD = { ~PLBAR } + IM1 = { ~UBAR/D & Q0 & Q1 & Q2 & Q3 } + IM2 = { UBAR/D & Q0BAR & Q1BAR & Q2BAR & Q3BAR } + IC1 = { IEN2 & Q0BAR & Q1BAR } + IC2 = { IEN1 & Q0 & Q1 } + ID1 = { IEN2 & Q0BAR & Q1BAR & Q2BAR } + ID2 = { IEN1 & Q0 & Q1 & Q2 } + MCP = { ~CP } + S0 = { ~(P0 & ILD) } + R0 = { ~(S0 & ILD) } + S1 = { ~(P1 & ILD) } + R1 = { ~(S1 & ILD) } + S2 = { ~(P2 & ILD) } + R2 = { ~(S2 & ILD) } + S3 = { ~(P3 & ILD) } + R3 = { ~(S3 & ILD) } + JK0 = { ~CEBAR } + JK1 = { (IEN2 & Q0BAR) | (Q0 & IEN1) } + JK2 = { IC1 | IC2 } + JK3 = { ID1 | ID2 } + TC = { IM1 | IM2 } + RCBAR = { ~(MCP & JK0 & TC) } * UF191DLY PINDLY (6,0,8) DPWR DGND + Q0 Q1 Q2 Q3 RCBAR TC + P0 P1 P2 P3 CP UBAR/D CEBAR PLBAR + Q0_O Q1_O Q2_O Q3_O RCBAR_O TC_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CP,0) } + LOAD = { CHANGED_HL(PLBAR,0) } + UPDN = { CHANGED(UBAR/D,0) } + DATA = { (CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | + CHANGED(P3,0)) & PLBAR!='1 } + PINDLY: + Q0_O Q1_O Q2_O Q3_O = { + CASE( + DATA & TRN_LH, DELAY(1.5NS,4NS,7.5NS), + CLOCK & TRN_LH, DELAY(2NS,4.5NS,8.5NS), + LOAD & TRN_LH, DELAY(4NS,6.5NS,10.5NS), + CLOCK & TRN_HL, DELAY(5NS,7.5NS,12NS), + LOAD & TRN_HL, DELAY(5NS,8NS,12NS), + DATA & TRN_HL, DELAY(6.5NS,9NS,13NS), + DELAY(6.5NS,9NS,13NS) + ) + } + RCBAR_O = { + CASE( + CHANGED(CEBAR,0) & TRN_LH, DELAY(2NS,4NS,7.5NS), + CHANGED(CP,0) & TRN_LH, DELAY(2NS,4.5NS,8NS), + CHANGED(CP,0) & TRN_HL, DELAY(2.5NS,5NS,8NS), + CHANGED(CEBAR,0) & TRN_HL, DELAY(3NS,5NS,8NS), + UPDN & TRN_HL, DELAY(4NS,7.5NS,11NS), + LOAD & TRN_HL, DELAY(7NS,10NS,13.5NS), + DATA & TRN_HL, DELAY(6NS,11NS,15NS), + UPDN & TRN_LH, DELAY(8NS,11NS,17NS), + DATA & TRN_LH, DELAY(6NS,14NS,19.5NS), + LOAD & TRN_LH, DELAY(8.5NS,16NS,21NS), + DELAY(8.5NS,16NS,21NS) + ) + } + TC_O = { + CASE( + UPDN & TRN_HL, DELAY(3NS,6NS,10NS), + UPDN & TRN_LH, DELAY(3NS,6.5NS,10.5NS), + CLOCK & TRN_HL, DELAY(6NS,8NS,12NS), + LOAD & TRN_LH, DELAY(5.5NS,8.5NS,13NS), + CLOCK & TRN_LH, DELAY(6NS,9NS,13NS), + DATA & TRN_LH, DELAY(5NS,9.5NS,14NS), + DATA & TRN_HL, DELAY(6NS,9.5NS,14NS), + LOAD & TRN_HL, DELAY(6NS,10.5NS,14.5NS), + DELAY(6NS,10.5NS,14.5NS) + ) + } + FREQ: + NODE = CP + MAXFREQ = 90MEG + WIDTH: + NODE = CP + MIN_LO = 6NS + MIN_HI = 3.5NS + WIDTH: + NODE = PLBAR + MIN_LO = 6NS + SETUP_HOLD: + DATA(1) = CEBAR + CLOCK LH = CP + SETUPTIME = 10NS + WHEN = { PLBAR!='0 } + SETUP_HOLD: + DATA(4) = P0 P1 P2 P3 + CLOCK LH = PLBAR + SETUPTIME = 5NS + HOLDTIME = 2NS + SETUP_HOLD: + DATA(1) = UBAR/D + CLOCK LH = CP + SETUPTIME = 12NS + WHEN = { PLBAR!='0 & (CEBAR!='1 ^ CHANGED(CEBAR,0)) } + SETUP_HOLD: + DATA(1) = PLBAR + CLOCK LH = CP + RELEASETIME_LH = 6NS * .ENDS * *$ *--------- * 74F192 Synchronous 4-bit Up/Down Decade Counters (Dual clock w/ clear) * * FAST LOGIC DATA BOOK, 1989, PHILIPS SEMICONDUCTOR * JSW 7/28/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F192 CPU_I CPD_I MR_I PLBAR_I P0_I P1_I P2_I P3_I + Q0_O Q1_O Q2_O Q3_O TCDBAR_O TCUBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND S0 R0 MCLK $D_HI $D_HI IQ0 Q0BAR + D0_EFF IO_F U2 JKFF(1) DPWR DGND S1 R1 MCLK JK1 JK1 IQ1 Q1BAR + D0_EFF IO_F U3 JKFF(1) DPWR DGND S2 R2 MCLK JK2 JK2 IQ2 Q2BAR + D0_EFF IO_F U4 JKFF(1) DPWR DGND S3 R3 MCLK JK3 JK3 IQ3 Q3BAR + D0_EFF IO_F U5 SRFF(1) DPWR DGND CPU CPD $D_HI $D_LO $D_LO IU ID + D0_GFF IO_F * UF192LOG LOGICEXP (18,26) DPWR DGND + CPU_I CPD_I MR_I PLBAR_I P0_I P1_I P2_I P3_I IQ0 IQ1 IQ2 IQ3 Q0BAR Q1BAR + Q2BAR Q3BAR IU ID + CPU CPD MR PLBAR P0 P1 P2 P3 JK1 JK2 JK3 TCDBAR TCUBAR MCLK + S0 R0 S1 R1 S2 R2 S3 R3 Q0 Q1 Q2 Q3 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CPU = { CPU_I } + CPD = { CPD_I } + MR = { MR_I } + PLBAR = { PLBAR_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + IPL = { ~PLBAR } + ICL = { ~MR } + MCLK = { ~(CPU & CPD) } + IN1 = { ~(Q1BAR & Q2BAR & Q3BAR) } + S0 = { ~(P0 & IPL & ICL) } + R0 = { ~(S0 & IPL) & ICL } + S1 = { ~(P1 & IPL & ICL) } + R1 = { ~(S1 & IPL) & ICL } + S2 = { ~(P2 & IPL & ICL) } + R2 = { ~(S2 & IPL) & ICL } + S3 = { ~(P3 & IPL & ICL) } + R3 = { ~(S3 & IPL) & ICL } + JK1 = { (Q0BAR & ID & IN1) | (IQ0 & IU & Q3BAR) } + JK2 = { (Q0BAR & Q1BAR & ID & IN1) | (IQ0 & IQ1 & IU) } + JK3 = { (Q0BAR & Q1BAR & Q2BAR & ID) | (IQ0 & IQ1 & IQ2 & IU) | + (IQ3 & IQ0 & IU) } + TCUBAR = { ~(~CPU & IQ3 & IQ0) } + TCDBAR = { ~(~CPD & Q3BAR & Q2BAR & Q1BAR & Q0BAR) } + Q0 = { ~Q0BAR } + Q1 = { ~Q1BAR } + Q2 = { ~Q2BAR } + Q3 = { ~Q3BAR } * UF192DLY PINDLY (6,0,8) DPWR DGND + Q0 Q1 Q2 Q3 TCDBAR TCUBAR + CPU CPD PLBAR MR P0 P1 P2 P3 + Q0_O Q1_O Q2_O Q3_O TCDBAR_O TCUBAR_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + UPDN = { (CHANGED_LH(CPU,0) | CHANGED_LH(CPD,0)) & PLBAR!='0 + & MR!='1 } + DATA = { (CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | + CHANGED(P3,0)) & PLBAR!='1 & MR!='1 } + RESET = { CHANGED_LH(MR,0) } + LOAD = { CHANGED_HL(PLBAR,0) } + PINDLY: + Q0_O Q1_O Q2_O Q3_O = { + CASE( + DATA & TRN_LH, DELAY(1.5NS,4NS,8NS), + UPDN & TRN_LH, DELAY(2.5NS,5.5NS,9NS), + LOAD & TRN_LH, DELAY(4NS,6.5NS,11NS), + UPDN & TRN_HL, DELAY(5NS,8.5NS,13NS), + LOAD & TRN_HL, DELAY(5NS,8.5NS,13NS), + RESET, DELAY(5NS,7.5NS,12NS), + DATA & TRN_HL, DELAY(6NS,9.5NS,15NS), + DELAY(7NS,10NS,16NS) + ) + } + TCUBAR_O = { + CASE( + (CHANGED(CPU,0) | CHANGED(CPD,0)) & TRN_HL & PLBAR!='0 + & MR!='1, DELAY(3NS,5NS,9NS), + UPDN & TRN_LH, DELAY(2.5NS,5.5NS,9NS), + RESET, DELAY(5.5NS,8.5NS,13NS), + DATA & TRN_HL, DELAY(4.5NS,8.5NS,13.5NS), + LOAD & TRN_HL, DELAY(6NS,9NS,13NS), + DATA & TRN_LH, DELAY(5NS,9NS,14NS), + LOAD & TRN_LH, DELAY(6NS,9.5NS,15NS), + DELAY(7NS,10NS,16NS) + ) + } + TCDBAR_O = { + CASE( + (CHANGED(CPU,0) | CHANGED(CPD,0)) & TRN_HL & PLBAR!='0 + & MR!='1, DELAY(3NS,5NS,9NS), + UPDN & TRN_LH, DELAY(2.5NS,5.5NS,9NS), + RESET, DELAY(5NS,7.5NS,12NS), + DATA & TRN_HL, DELAY(4.5NS,8.5NS,13.5NS), + LOAD & TRN_HL, DELAY(6NS,9NS,13NS), + DATA & TRN_LH, DELAY(5NS,9NS,14NS), + LOAD & TRN_LH, DELAY(6NS,9.5NS,15NS), + DELAY(7NS,10NS,16NS) + ) + } + FREQ: + NODE = CPU + MAXFREQ = 90MEG + FREQ: + NODE = CPD + MAXFREQ = 90MEG + WIDTH: + NODE = CPU + MIN_LO = 5NS + MIN_HI = 3.5NS + WIDTH: + NODE = CPD + MIN_LO = 5NS + MIN_HI = 3.5NS + WIDTH: + NODE = PLBAR + MIN_LO = 6NS + WHEN = { MR!='1 } + WIDTH: + NODE = MR + MIN_HI = 6NS + SETUP_HOLD: + DATA(1) = MR + CLOCK LH = CPU + RELEASETIME_HL = 4NS + SETUP_HOLD: + DATA(1) = MR + CLOCK LH = CPD + RELEASETIME_HL = 4NS + SETUP_HOLD: + DATA(1) = PLBAR + CLOCK LH = CPU + RELEASETIME_LH = 6NS + WHEN = { MR!='1 } + SETUP_HOLD: + DATA(1) = PLBAR + CLOCK LH = CPD + RELEASETIME_LH = 6NS + WHEN = { MR!='1 } + SETUP_HOLD: + DATA(4) = P0 P1 P2 P3 + CLOCK LH = PLBAR + SETUPTIME = 5NS + HOLDTIME = 2NS + WHEN = { MR!='1 & PLBAR!='1 } * .ENDS * *$ *--------- * 74F193 Synchronous 4-bit Up/Down Binary Counters (Dual clock w/ clear) * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTOR * tc 7/28/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F193 CPU_I CPD_I MR_I PLBAR_I P0_I P1_I P2_I P3_I + Q0_O Q1_O Q2_O Q3_O TCDBAR_O TCUBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND S0 R0 MCLK $D_HI $D_HI Q0 Q0BAR + D0_EFF IO_F U2 JKFF(1) DPWR DGND S1 R1 MCLK JK1 JK1 Q1 Q1BAR + D0_EFF IO_F U3 JKFF(1) DPWR DGND S2 R2 MCLK JK2 JK2 Q2 Q2BAR + D0_EFF IO_F U4 JKFF(1) DPWR DGND S3 R3 MCLK JK3 JK3 Q3 Q3BAR + D0_EFF IO_F U5 SRFF(1) DPWR DGND CPU CPD $D_HI $D_LO $D_LO IU ID + D0_GFF IO_F * UF193LOG LOGICEXP (18,22) DPWR DGND + CPU_I CPD_I MR_I PLBAR_I P0_I P1_I P2_I P3_I Q0 Q1 Q2 Q3 + Q0BAR Q1BAR Q2BAR Q3BAR IU ID + CPU CPD MR PLBAR P0 P1 P2 P3 JK1 JK2 JK3 TCDBAR TCUBAR MCLK + S0 R0 S1 R1 S2 R2 S3 R3 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CPU = { CPU_I } + CPD = { CPD_I } + MR = { MR_I } + PLBAR = { PLBAR_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + IPL = { ~PLBAR } + ICL = { ~MR } + MCLK = { ~(CPU & CPD) } + S0 = { ~(P0 & IPL & ICL) } + R0 = { ~(S0 & IPL) & ICL } + S1 = { ~(P1 & IPL & ICL) } + R1 = { ~(S1 & IPL) & ICL } + S2 = { ~(P2 & IPL & ICL) } + R2 = { ~(S2 & IPL) & ICL } + S3 = { ~(P3 & IPL & ICL) } + R3 = { ~(S3 & IPL) & ICL } + JK1 = { (Q0BAR & ID) | (Q0 & IU) } + JK2 = { (Q0BAR & Q1BAR & ID) | (Q0 & Q1 & IU) } + JK3 = { (Q0BAR & Q1BAR & Q2BAR & ID) | (Q0 & Q1 & Q2 & IU) } + TCUBAR = { ~(~CPU & Q3 & Q2 & Q1 & Q0) } + TCDBAR = { ~(~CPD & Q3BAR & Q2BAR & Q1BAR & Q0BAR) } * UF193DLY PINDLY (6,0,8) DPWR DGND + Q0 Q1 Q2 Q3 TCDBAR TCUBAR + CPU CPD PLBAR MR P0 P1 P2 P3 + Q0_O Q1_O Q2_O Q3_O TCDBAR_O TCUBAR_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + UPDN = { (CHANGED_LH(CPU,0) | CHANGED_LH(CPD,0)) & PLBAR!='0 + & MR!='1 } + DATA = { (CHANGED(P0,0) | CHANGED(P1,0) | CHANGED(P2,0) | + CHANGED(P3,0)) & PLBAR!='1 & MR!='1 } + RESET = { CHANGED_LH(MR,0) } + LOAD = { CHANGED(PLBAR,0) } + PINDLY: + Q0_O Q1_O Q2_O Q3_O = { + CASE( + DATA & TRN_LH, DELAY(1.5NS,4NS,8NS), + UPDN & TRN_LH, DELAY(2.5NS,5.5NS,9NS), + CHANGED_HL(PLBAR,0) & TRN_LH, DELAY(4NS,6.5NS,11NS), + RESET, DELAY(5NS,7.5NS,12NS), + CHANGED_HL(PLBAR,0) & TRN_HL, DELAY(5NS,8.5NS,13NS), + UPDN & TRN_HL, DELAY(5NS,8.5NS,13NS), + DATA & TRN_HL, DELAY(6NS,9.5NS,15NS), + DELAY(6NS,9.5NS,15NS) + ) + } + TCDBAR_O = { + CASE( + CHANGED(CPD,0) & TRN_HL, DELAY(3NS,5NS,9NS), + CHANGED(CPD,0) & TRN_LH, DELAY(2.5NS,5.5NS,9NS), + DATA & TRN_HL, DELAY(4.5NS,8.5NS,13.5NS), + RESET, DELAY(5NS,7.5NS,12NS), + LOAD & TRN_HL, DELAY(6NS,9NS,13NS), + DATA & TRN_LH, DELAY(5NS,9NS,14NS), + LOAD & TRN_LH, DELAY(6NS,9.5NS,15NS), + DELAY(6NS,9.5NS,15NS) + ) + } + TCUBAR_O = { + CASE( + CHANGED(CPU,0) & TRN_HL, DELAY(3NS,5NS,9NS), + CHANGED(CPU,0) & TRN_LH, DELAY(2.5NS,5.5NS,9NS), + DATA & TRN_HL, DELAY(4.5NS,8.5NS,13.5NS), + RESET, DELAY(5.5NS,8.5NS,13NS), + LOAD & TRN_HL, DELAY(6NS,9NS,13NS), + DATA & TRN_LH, DELAY(5NS,9NS,14NS), + LOAD & TRN_LH, DELAY(6NS,9.5NS,15NS), + DELAY(6NS,9.5NS,15NS) + ) + } + FREQ: + NODE = CPU + MAXFREQ = 90MEG + FREQ: + NODE = CPD + MAXFREQ = 90MEG + WIDTH: + NODE = CPU + MIN_LO = 3.5NS + MIN_HI = 5NS + WIDTH: + NODE = CPD + MIN_LO = 3.5NS + MIN_HI = 5NS + WIDTH: + NODE = PLBAR + MIN_LO = 6NS + WHEN = { MR!='1 } + WIDTH: + NODE = MR + MIN_HI = 6NS + SETUP_HOLD: + DATA(1) = MR + CLOCK LH = CPU + RELEASETIME_HL = 4NS + SETUP_HOLD: + DATA(1) = MR + CLOCK LH = CPD + RELEASETIME_HL = 4NS + SETUP_HOLD: + DATA(1) = PLBAR + CLOCK LH = CPU + RELEASETIME_LH = 6NS + WHEN = { MR!='1 } + SETUP_HOLD: + DATA(1) = PLBAR + CLOCK LH = CPD + RELEASETIME_LH = 6NS + WHEN = { MR!='1 } + SETUP_HOLD: + DATA(4) = P0 P1 P2 P3 + CLOCK LH = PLBAR + SETUPTIME = 5NS + HOLDTIME = 2NS + WHEN = { MR!='1 } * .ENDS * *$ *--------- * 74F194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS * * IC15 FAST TTL LOGIC SERIES DATA BOOK, 1990, PHILIPS SEMICONDUCTORS * NH 7/8/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F194 CP_I MRBAR_I S1_I S0_I DSL_I DSR_I P0_I P1_I P2_I P3_I + Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UF194LOG LOGICEXP(14,19) DPWR DGND + CP_I MRBAR_I S1_I S0_I DSL_I DSR_I P0_I P1_I P2_I P3_I Q0 Q1 Q2 Q3 + CP MRBAR S1 S0 DSL DSR P0 P1 P2 P3 K0 K1 K2 K3 J0 J1 J2 J3 CLOCK + D0_GATE IO_F IO_LEVEL = {IO_LEVEL} + + LOGIC: * * INTERMEDIATE TERM + LOAD = { S1_I & S0_I } + SRIGHT = { ~S1_I & S0_I } + SLEFT = { S1_I & ~S0_I } + HOLD = { ~S1_I & ~S0_I } * * OUTPUT ASSIGNMENT * + CP = { CP_I } + MRBAR = { MRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + DSL = { DSL_I } + DSR = { DSR_I } + P0 = { P0_I } + P1 = { P1_I } + P2 = { P2_I } + P3 = { P3_I } + + K0 = { ~( (DSR & SRIGHT) | (LOAD & P0) | (SLEFT & Q1) | (HOLD & Q0) ) } + K1 = { ~( (Q0 & SRIGHT) | (LOAD & P1) | (SLEFT & Q2) | (HOLD & Q1) ) } + K2 = { ~( (Q1 & SRIGHT) | (LOAD & P2) | (SLEFT & Q3) | (HOLD & Q2) ) } + K3 = { ~( (Q2 & SRIGHT) | (LOAD & P3) | (SLEFT & DSL) | (HOLD & Q3) ) } + J0 = { ~K0 } + J1 = { ~K1 } + J2 = { ~K2 } + J3 = { ~K3 } + CLOCK = { ~CP } * U1 JKFF(4) DPWR DGND $D_HI MRBAR CLOCK J0 J1 J2 J3 K0 K1 K2 K3 + Q0 Q1 Q2 Q3 $D_NC $D_NC $D-NC $D_NC + D0_EFF IO_F * UF194DLY PINDLY (4,0,10) DPWR DGND + Q0 Q1 Q2 Q3 + CP MRBAR S0 S1 DSL DSR P0 P1 P2 P3 + Q0_O Q1_O Q2_O Q3_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + Q0_O Q1_O Q2_O Q3_O = { + CASE( + CHANGED_LH(CP,0) & TRN_LH, DELAY(3.5NS,5.2NS,8NS), + CHANGED_LH(CP,0) & TRN_HL, DELAY(3.5NS,5.5NS,8NS), + CHANGED_HL(MRBAR,0), DELAY(4.5NS,8.6NS,14NS), + DELAY(5NS,9NS,14NS) ;DEFAULT + ) + } + + BOOLEAN: + NOT_CLEAR = { MRBAR!='0 } + + FREQ: + NODE = CP + MAXFREQ = 90MEG + + WIDTH: + NODE = CP + MIN_HI = 5.5NS + MIN_LO = 5.5NS + + WIDTH: + NODE = MRBAR + MIN_LO = 5NS + + SETUP_HOLD: + DATA(2) S0 S1 + CLOCK LH = CP + SETUPTIME_HI = 9NS + SETUPTIME_LO = 8NS + WHEN = { NOT_CLEAR } + + SETUP_HOLD: + DATA(1) DSL + CLOCK LH = CP + SETUPTIME = 4NS + HOLDTIME = 1NS + WHEN = { NOT_CLEAR & (S1!='0 ^ CHANGED(S1,0)) & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) DSR + CLOCK LH = CP + SETUPTIME = 4NS + HOLDTIME = 1NS + WHEN = { NOT_CLEAR & (S1!='1 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(4) P0 P1 P2 P3 + CLOCK LH = CP + SETUPTIME = 4NS + HOLDTIME = 1NS + WHEN = { NOT_CLEAR & (S1!='0 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) MRBAR + CLOCK LH = CP + RELEASETIME_LH = 8NS * .ENDS * *$ *---------- * 74F240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The F Logic Data Book, 1987, TI * tvh 06/30/89 Update interface and model names * .subckt 74F240 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_F240 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_F240 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F240 utgate ( + tplhmn=2.2ns tplhmx=8ns + tplhty=4.7ns tphlmn=1.2ns + tphlmx=5.7ns tphlty=3.1ns + tpzhmn=1.2ns tpzhmx=6.1ns + tpzhty=3.1ns tpzlmn=3.2ns + tpzlmx=10ns tpzlty=6.5ns + tphzmn=1.2ns tphzmx=6.3ns + tphzty=3.6ns tplzmn=1.2ns + tplzmx=9.5ns tplzty=5.6ns + ) *$ *---------- * 74F241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The F Logic Data Book, 1987, TI * tvh 06/30/89 Update interface and model names * jgt 09/08/92 Bug Fix: changed inverters to Buffers * .subckt 74F241 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_F241 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_F241 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F241 utgate ( + tplhmn=1.7ns tplhmx=6.2ns + tplhty=3.6ns tphlmn=1.7ns + tphlmx=6.5ns tphlty=3.6ns + tpzhmn=1.2ns tpzhmx=6.7ns + tpzhty=3.9ns tpzlmn=1.2ns + tpzlmx=8ns tpzlty=5ns + tphzmn=1.2ns tphzmx=7ns + tphzty=4.1ns tplzmn=1.2ns + tplzmx=7ns tplzty=4.1ns + ) * *$ *---------- * 74F242 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The F Logic Data Book, 1987, TI * tvh 06/30/89 Update interface and model names * .subckt 74F242 A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_F242 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_F242 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F242 utgate ( + tplhmn=2.2ns tplhmx=7.5ns + tplhty=4.1ns tphlmn=1ns + tphlmx=4.5ns tphlty=3.6ns + tpzhmn=2.7ns tpzhmx=8.5ns + tpzhty=5.6ns tpzlmn=2.7ns + tpzlmx=10.5ns tpzlty=6.1ns + tphzmn=1.8ns tphzmx=9.5ns + tphzty=6.6ns tplzmn=2.7ns + tplzmx=11ns tplzty=5.6ns + ) *$ *---------- * 74F243 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The F Logic Data Book, 1987, TI * tvh 06/30/89 Update interface and model names * .subckt 74F243 A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_F243 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_F243 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F243 utgate ( + tplhmn=1.2ns tplhmx=6.2ns + tplhty=3.6ns tphlmn=1.2ns + tphlmx=6.5ns tphlty=3.6ns + tpzhmn=1.2ns tpzhmx=6.7ns + tpzhty=3.9ns tpzlmn=1.2ns + tpzlmx=8.5ns tpzlty=5.4ns + tphzmn=1ns tphzmx=7ns + tphzty=4.1ns tplzmn=1.2ns + tplzmx=7ns tplzty=4.1ns + ) *$ *---------- * 74F244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The F Logic Data Book, 1987, TI * tvh 06/30/89 Update interface and model names * .subckt 74F244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * DtoA switching time delay is greater than some of the gate delay. * UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_F244 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_F244 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F244 utgate ( + tplhmn=1.7ns tplhmx=6.2ns + tplhty=3.6ns tphlmn=1.7ns + tphlmx=6.5ns tphlty=3.6ns + tpzhmn=1.2ns tpzhmx=6.7ns + tpzhty=3.9ns tpzlmn=1.2ns + tpzlmx=8ns tpzlty=5ns + tphzmn=1.2ns tphzmx=7ns + tphzty=4.1ns tplzmn=1.2ns + tplzmx=7ns tplzty=4.1ns + ) *$ *---------- * 74F245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-2-92 UPDATE TIMING * .SUBCKT 74F245 T/RBAR_I OEBAR_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + T/RBAR_I OEBAR_I + T/RBAR OEBAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + T/RBAR T/RBARBAR + D0_GATE IO_F U3 NORA(2,2) DPWR DGND + T/RBARBAR OEBAR T/RBAR OEBAR + ENABLEAB ENABLEBA + D0_GATE IO_F * U4 BUF3A(8) DPWR DGND + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + ENABLEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + D_F245 IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 BUF3A(8) DPWR DGND + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + ENABLEBA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + D_F245 IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_F245 UTGATE ( + TPLHMN=2.5NS TPLHTY=3.5NS TPLHMX=7.0NS + TPHLMN=2.5NS TPHLTY=4.0NS TPHLMX=7.0NS + TPZHMN=2.0NS TPZHTY=4.5NS TPZHMX=8.0NS + TPZLMN=3.5NS TPZLTY=5.5NS TPZLMX=9.0NS + TPHZMN=2.0NS TPHZTY=5.0NS TPHZMX=7.5NS + TPLZMN=1.0NS TPLZTY=3.5NS TPLZMX=7NS + ) * .ENDS * *$ *--------- * 74F251 MULTIPLEXER/DATA SELECTOR 8-1 LINE WITH 3-STATE OUTPUTS * * FAST TTL SERIES, 1991, PHILIPS SEMICONDUCTORS * TC 08/24/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F251 OEBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + Z_O ZBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF251LOG LOGICEXP(12,14) DPWR DGND + OEBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + OEBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 ZBAR Z + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBAR = { OEBAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + I0 = { I0_I } + I1 = { I1_I } + I2 = { I2_I } + I3 = { I3_I } + I4 = { I4_I } + I5 = { I5_I } + I6 = { I6_I } + I7 = { I7_I } + IS0 = { ~S0 } + IS1 = { ~S1 } + IS2 = { ~S2 } + IOE = { ~OEBAR } + II0 = { I0 & IS0 & IS1 & IS2 & IOE } + II1 = { I1 & S0 & IS1 & IS2 & IOE } + II2 = { I2 & IS0 & S1 & IS2 & IOE } + II3 = { I3 & S0 & S1 & IS2 & IOE } + II4 = { I4 & IS0 & IS1 & S2 & IOE } + II5 = { I5 & S0 & IS1 & S2 & IOE } + II6 = { I6 & IS0 & S1 & S2 & IOE } + II7 = { I7 & S0 & S1 & S2 & IOE } + ZBAR = { ~(II0 | II1 | II2 | II3 | II4 | II5 | II6 | II7) } + Z = { ~ZBAR } * UF251DLY PINDLY (2,1,11) DPWR DGND + ZBAR Z + OEBAR + S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 + ZBAR_O Z_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) | + CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0) } + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0) } + TRISTATE: + ENABLE LO OEBAR + Z_O = { + CASE( + SELECT & TRN_LH, DELAY(3.5NS,7NS,11NS), + TRN_ZH, DELAY(4NS,6.5NS,11NS), + SELECT & TRN_HL, DELAY(4NS,7NS,10NS), + TRN_ZL, DELAY(3.5NS,5.5NS,9NS), + TRN_LZ, DELAY(2.5NS,4NS,7.5NS), + DATA & TRN_LH, DELAY(2.5NS,4NS,7NS), + DATA & TRN_HL, DELAY(3NS,4.5NS,7NS), + TRN_HZ, DELAY(2NS,4NS,7.5NS), + DELAY(4NS,8NS,12NS) + ) + } + ZBAR_O = { + CASE( + SELECT & TRN_LH, DELAY(3.5NS,6NS,10NS), + TRN_Z$, DELAY(3.5NS,5.5NS,9NS), + SELECT & TRN_HL, DELAY(1.5NS,5NS,8.5NS), + TRN_$Z, DELAY(2NS,4NS,7.5NS), + DATA & TRN_LH, DELAY(2NS,4NS,7NS), + DATA & TRN_HL, DELAY(1NS,2NS,5NS), + DELAY(4NS,7NS,11NS) + ) + } * .ENDS * *$ *--------- * 74F251A MULTIPLEXER/DATA SELECTOR 8-1 LINE WITH 3-STATE OUTPUTS * * FAST TTL SERIES, 1991, PHILIPS SEMICONDUCTORS * TC 08/28/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F251A OEBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + Z_O ZBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF251ALOG LOGICEXP(12,14) DPWR DGND + OEBAR_I S0_I S1_I S2_I I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I + OEBAR S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 ZBAR Z + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBAR = { OEBAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + I0 = { I0_I } + I1 = { I1_I } + I2 = { I2_I } + I3 = { I3_I } + I4 = { I4_I } + I5 = { I5_I } + I6 = { I6_I } + I7 = { I7_I } + IS0 = { ~S0 } + IS1 = { ~S1 } + IS2 = { ~S2 } + IOE = { ~OEBAR } + II0 = { I0 & IS0 & IS1 & IS2 & IOE } + II1 = { I1 & S0 & IS1 & IS2 & IOE } + II2 = { I2 & IS0 & S1 & IS2 & IOE } + II3 = { I3 & S0 & S1 & IS2 & IOE } + II4 = { I4 & IS0 & IS1 & S2 & IOE } + II5 = { I5 & S0 & IS1 & S2 & IOE } + II6 = { I6 & IS0 & S1 & S2 & IOE } + II7 = { I7 & S0 & S1 & S2 & IOE } + ZBAR = { ~(II0 | II1 | II2 | II3 | II4 | II5 | II6 | II7) } + Z = { ~ZBAR } * UF251ADLY PINDLY (2,1,11) DPWR DGND + ZBAR Z + OEBAR + S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 + ZBAR_O Z_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) | + CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0) } + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0) } + TRISTATE: + ENABLE LO OEBAR + Z_O = { + CASE( + SELECT & TRN_LH, DELAY(4NS,6.5NS,11.5NS), + SELECT & TRN_HL, DELAY(3.5NS,5.5NS,9.5NS), + TRN_ZH, DELAY(3NS,5.5NS,8.5NS), + TRN_ZL, DELAY(3NS,5NS,8NS), + DATA & TRN_HL, DELAY(3NS,5NS,8NS), + DATA & TRN_LH, DELAY(2.5NS,5NS,8NS), + TRN_HZ, DELAY(2NS,4NS,7NS), + TRN_LZ, DELAY(1NS,4NS,6.5NS), + DELAY(5NS,7NS,12NS) + ) + } + ZBAR_O = { + CASE( + SELECT & TRN_LH, DELAY(3.5NS,6NS,9.5NS), + TRN_HZ, DELAY(3NS,5NS,8NS), + SELECT & TRN_HL, DELAY(2.5NS,4.5NS,7.5NS), + DATA & TRN_LH, DELAY(2NS,4.5NS,7.5NS), + TRN_ZL, DELAY(2.5NS,4NS,7NS), + TRN_ZH, DELAY(2NS,4NS,7NS), + DATA & TRN_HL, DELAY(1NS,2.5NS,5NS), + TRN_LZ, DELAY(1NS,2NS,4.5NS), + DELAY(4NS,7NS,10NS) + ) + } * .ENDS * *$ *--------- * 74F253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F253 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF253LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * UF253DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_Z$, DELAY(3NS,6.5NS,9NS), + TRN_HZ, DELAY(2NS,3.5NS,6NS), + TRN_LZ, DELAY(1.5NS,3NS,6NS), + SELECT & TRN_LH, DELAY(4.5NS,7.5NS,11NS), + SELECT & TRN_HL, DELAY(4.5NS,8.5NS,12NS), + DATA1 & TRN_LH, DELAY(3NS,4.5NS,7.5NS), + DATA1 & TRN_HL, DELAY(3NS,5NS,8NS), + DELAY(5NS,9NS,13NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_Z$, DELAY(3NS,6.5NS,9NS), + TRN_HZ, DELAY(2NS,3.5NS,6NS), + TRN_LZ, DELAY(1.5NS,3NS,6NS), + SELECT & TRN_LH, DELAY(4.5NS,7.5NS,11NS), + SELECT & TRN_HL, DELAY(4.5NS,8.5NS,12NS), + DATA2 & TRN_LH, DELAY(3NS,4.5NS,7.5NS), + DATA2 & TRN_HL, DELAY(3NS,5NS,8NS), + DELAY(5NS,9NS,13NS) + ) + } * .ENDS * *$ *--------- * 74F257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F257 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF257LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { (1A & SELBAR) | (1B & SEL) } + Y2 = { (2A & SELBAR) | (2B & SEL) } + Y3 = { (3A & SELBAR) | (3B & SEL) } + Y4 = { (4A & SELBAR) | (4B & SEL) } * UF257DLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(3NS,6NS,8.5NS), + TRN_ZL, DELAY(3NS,6NS,8.5NS), + TRN_HZ, DELAY(2NS,4NS,7NS), + TRN_LZ, DELAY(2NS,3.5NS,7NS), + SELECT & TRN_LH, DELAY(4.5NS,8NS,15NS), + SELECT & TRN_HL, DELAY(3.5NS,6NS,9.5NS), + DATA & TRN_LH, DELAY(3NS,4.5NS,7NS), + DATA & TRN_HL, DELAY(2NS,3.5NS,6.5NS), + DELAY(5NS,9NS,16NS) + ) + } * .ENDS * *$ *--------- * 74F257A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F257A GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF257ALOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { (1A & SELBAR) | (1B & SEL) } + Y2 = { (2A & SELBAR) | (2B & SEL) } + Y3 = { (3A & SELBAR) | (3B & SEL) } + Y4 = { (4A & SELBAR) | (4B & SEL) } * UF257ADLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(4.5NS,6.5NS,8.5NS), + TRN_ZL, DELAY(4.5NS,6NS,8.5NS), + TRN_HZ, DELAY(2NS,4NS,6NS), + TRN_LZ, DELAY(2NS,3.5NS,6NS), + SELECT & TRN_LH, DELAY(5NS,7.5NS,10.5NS), + SELECT & TRN_HL, DELAY(4NS,5.5NS,8NS), + DATA & TRN_LH, DELAY(3NS,4.5NS,7NS), + DATA & TRN_HL, DELAY(2NS,3.5NS,6NS), + DELAY(6NS,8NS,11NS) + ) + } * .ENDS * *$ *--------- * 74F258 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F258 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF258LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { ~((1A & SELBAR) | (1B & SEL)) } + Y2 = { ~((2A & SELBAR) | (2B & SEL)) } + Y3 = { ~((3A & SELBAR) | (3B & SEL)) } + Y4 = { ~((4A & SELBAR) | (4B & SEL)) } * UF258DLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(3NS,5.9NS,8.5NS), + TRN_ZL, DELAY(3NS,5.5NS,8.5NS), + TRN_$Z, DELAY(2NS,3.5NS,7NS), + SELECT & TRN_LH, DELAY(3.5NS,6.5NS,9.5NS), + SELECT & TRN_HL, DELAY(2.5NS,6NS,11NS), + DATA & TRN_LH, DELAY(2.5NS,4NS,7NS), + DATA & TRN_HL, DELAY(1NS,2.5NS,5.5NS), + DELAY(4NS,7NS,12NS) + ) + } * .ENDS * *$ *--------- * 74F258A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F258A GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF258ALOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { ~((1A & SELBAR) | (1B & SEL)) } + Y2 = { ~((2A & SELBAR) | (2B & SEL)) } + Y3 = { ~((3A & SELBAR) | (3B & SEL)) } + Y4 = { ~((4A & SELBAR) | (4B & SEL)) } * UF258ADLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(3.5NS,6NS,8.5NS), + TRN_ZL, DELAY(3.5NS,5.5NS,8.5NS), + TRN_HZ, DELAY(2NS,3.5NS,6.5NS), + TRN_LZ, DELAY(2NS,3.5NS,6NS), + SELECT & TRN_LH, DELAY(3.5NS,6.5NS,9NS), + SELECT & TRN_HL, DELAY(2.5NS,6NS,9NS), + DATA & TRN_LH, DELAY(2.5NS,4.5NS,7NS), + DATA & TRN_HL, DELAY(1NS,2.5NS,4.5NS), + DELAY(4NS,7NS,10NS) + ) + } * .ENDS * *$ *--------- * 74F259 8-BIT ADDRESSABLE LATCHES * * Philips Components, 1990 * cv 09/10/90 Created from LS * .subckt 74F259 MRBAR EBAR D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + MRBAR EBAR D MRB EB DATA + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U2 bufa(3) DPWR DGND + A0 A1 A2 SA SB SC + D_F259_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + SA SB SC AB BB CB + D0_GATE IO_F U4 nanda(3,8) DPWR DGND + AB BB CB + SA BB CB + AB SB CB + SA SB CB + AB BB SC + SA BB SC + AB SB SC + SA SB SC + T0 T1 T2 T3 T4 T5 T6 T7 + D0_GATE IO_F U5 nora(2,8) DPWR DGND + EB T0 + EB T1 + EB T2 + EB T3 + EB T4 + EB T5 + EB T6 + EB T7 + E0 E1 E2 E3 E4 E5 E6 E7 + D0_GATE IO_F U6 ora(2,8) DPWR DGND + E0 MRB + E1 MRB + E2 MRB + E3 MRB + E4 MRB + E5 MRB + E6 MRB + E7 MRB + R0 R1 R2 R3 R4 R5 R6 R7 + D0_GATE IO_F U7 dltch(1) DPWR DGND + $D_HI R0 E0 DATA Q0 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 dltch(1) DPWR DGND + $D_HI R1 E1 DATA Q1 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 dltch(1) DPWR DGND + $D_HI R2 E2 DATA Q2 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 dltch(1) DPWR DGND + $D_HI R3 E3 DATA Q3 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 dltch(1) DPWR DGND + $D_HI R4 E4 DATA Q4 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 dltch(1) DPWR DGND + $D_HI R5 E5 DATA Q5 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U13 dltch(1) DPWR DGND + $D_HI R6 E6 DATA Q6 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U14 dltch(1) DPWR DGND + $D_HI R7 E7 DATA Q7 $D_NC + D_F259_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F259_1 ugate ( + TPLHMN=0.5NS TPLHTY=2NS + TPLHMX=2.5NS TPHLMN=1NS + TPHLTY=3.5NS TPHLMX=2NS + ) .model D_F259_2 ugff ( + TWGHMN=8NS TWPCLMN=3NS + TSUDGMN=7NS TSUDGMX=3NS + THDGMN=0NS THDGMX=0NS + TPPCQHLMN=4.5NS TPPCQHLTY=7NS + TPPCQHLMX=10NS TPDQLHMN=4NS + TPDQLHTY=7NS TPDQLHMX=10NS + TPDQHLMN=2.5NS TPDQHLTY=5NS + TPDQHLMX=7.5NS TPGQLHMN=4.5NS + TPGQLHTY=8NS TPGQLHMX=12NS + TPGQHLMN=3NS TPGQHLTY=5NS + TPGQHLMX=8NS + ) *$ *---------- * 74F273 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR * * The F Logic Data Book, 1987, TI * tvh 09/07/89 Update interface and model names * .subckt 74F273 CLRBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(8) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 D7 D8 + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_F273 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F273 ueff ( + TWCLKLMN=5NS TWCLKHMN=4NS + TWPCLMN=3.5NS TSUDCLKMN=1.5NS + TSUPCCLKHMN=8NS TPPCQHLTY=7NS + TPCLKQLHTY=7.5NS TPCLKQHLTY=7.5NS + ) *$ *--------- * 74F280A PARITY GENERATOR/CHECKER ODD/EVEN 9-BIT * * FAST TTL LOGIC SERIES, 1991, PHILIPS SEMICONDUCTORS * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F280A I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I I8_I + EOUT_O OOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF280ALOG LOGICEXP (9,2) DPWR DGND + I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I I8_I + EOUT OOUT + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + I0 = { I0_I } + I1 = { I1_I } + I2 = { I2_I } + I3 = { I3_I } + I4 = { I4_I } + I5 = { I5_I } + I6 = { I6_I } + I7 = { I7_I } + I8 = { I8_I } + + ABC = { ( I0 & ~I1 & ~I2) | (~I0 & I1 & ~I2) | + (~I0 & ~I1 & I2) | ( I0 & I1 & I2) } + DEF = { ( I3 & ~I4 & ~I5) | (~I3 & I4 & ~I5) | + (~I3 & ~I4 & I5) | ( I3 & I4 & I5) } + GHI = { ( I6 & ~I7 & ~I8) | (~I6 & I7 & ~I8) | + (~I6 & ~I7 & I8) | ( I6 & I7 & I8) } + EOUT = { (~ABC & DEF & GHI) | (ABC & ~DEF & GHI) | (ABC & DEF & ~GHI) | + (~ABC & ~DEF & ~GHI) } + OOUT = { ~EOUT } * UF280ADLY PINDLY (2,0,0) DPWR DGND + EOUT OOUT + + EOUT_O OOUT_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + EOUT_O = { + CASE ( + TRN_LH, DELAY(5.0NS,7.0NS,10.0NS), + DELAY(7.5NS,10.0NS,14.5NS) + ) + } + OOUT_O = { + CASE ( + TRN_LH, DELAY(6.5NS,8.6NS,11.0NS), + DELAY(6.0NS,9.1NS,13.0NS) + ) + } * .ENDS * *$ *--------- * 74F280B PARITY GENERATOR/CHECKER ODD/EVEN 9-BIT * * FAST TTL LOGIC SERIES, 1991, PHILIPS SEMICONDUCTORS * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F280B I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I I8_I + EOUT_O OOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF280BLOG LOGICEXP (9,2) DPWR DGND + I0_I I1_I I2_I I3_I I4_I I5_I I6_I I7_I I8_I + EOUT OOUT + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + I0 = { I0_I } + I1 = { I1_I } + I2 = { I2_I } + I3 = { I3_I } + I4 = { I4_I } + I5 = { I5_I } + I6 = { I6_I } + I7 = { I7_I } + I8 = { I8_I } + + ABC = { ( I0 & ~I1 & ~I2) | (~I0 & I1 & ~I2) | + (~I0 & ~I1 & I2) | ( I0 & I1 & I2) } + DEF = { ( I3 & ~I4 & ~I5) | (~I3 & I4 & ~I5) | + (~I3 & ~I4 & I5) | ( I3 & I4 & I5) } + GHI = { ( I6 & ~I7 & ~I8) | (~I6 & I7 & ~I8) | + (~I6 & ~I7 & I8) | ( I6 & I7 & I8) } + EOUT = { (~ABC & DEF & GHI) | (ABC & ~DEF & GHI) | (ABC & DEF & ~GHI) | + (~ABC & ~DEF & ~GHI) } + OOUT = { ~EOUT } * UF280BDLY PINDLY (2,0,0) DPWR DGND + EOUT OOUT + + EOUT_O OOUT_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + EOUT_O = { + CASE ( + TRN_LH, DELAY(3.5NS,6.5NS,10.0NS), + DELAY(3.5NS,7.0NS,11.1NS) + ) + } + OOUT_O = { + CASE ( + TRN_LH, DELAY(3.5NS,6.5NS,10.0NS), + DELAY(3.5NS,7.0NS,11.0NS) + ) + } * .ENDS * *$ *--------- * 74F283 4-BIT BINARY FULL ADDERS WITH FAST CARRY * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * NH 8/26/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F283 C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I C4_O + SUM1_O SUM2_O SUM3_O SUM4_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UF283LOG LOGICEXP(9,14) DPWR DGND + C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I + C0 A1 A2 A3 A4 B1 B2 B3 B4 C4 SUM1 SUM2 SUM3 SUM4 + D0_GATE IO_F IO_LEVEL = {IO_LEVEL} + + LOGIC: + C0 = { C0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + B1 = { B1_I } + B2 = { B2_I } + B3 = { B3_I } + B4 = { B4_I } + + NAND4 = { ~(A4 & B4) } + NAND3 = { ~(A3 & B3) } + NAND2 = { ~(A2 & B2) } + NAND1 = { ~(A1 & B1) } + NOR4 = { ~(A4 | B4) } + NOR3 = { ~(A3 | B3) } + NOR2 = { ~(A2 | B2) } + NOR1 = { ~(A1 | B1) } + C0BAR = { ~C0 } + + SUM1 = { (NAND1 & ~NOR1) ^ C0 } + SUM2 = { (NAND2 & ~NOR2) ^ (~(NOR1 | (NAND1 & C0BAR))) } + SUM3 = { (NAND3 & ~NOR3) ^ (~(NOR2 | (NOR1 & NAND2) | + (NAND2 & NAND1 & C0BAR))) } + SUM4 = { (NAND4 & ~NOR4) ^ (~(NOR3 | (NOR2 & NAND3) | + (NOR1 & NAND3 & NAND2) | (NAND3 & NAND2 & NAND1 & C0BAR))) } + C4 = { ~( NOR4 | (NOR3 & NAND4) | (NOR2 & NAND4 & NAND3) | + (NOR1 & NAND4 & NAND3 & NAND2) | + (NAND4 & NAND3 & NAND2 & NAND1 & C0BAR) ) } * UF283DLY PINDLY (5,0,9) DPWR DGND + SUM1 SUM2 SUM3 SUM4 C4 + C0 A1 A2 A3 A4 B1 B2 B3 B4 + SUM1_O SUM2_O SUM3_O SUM4_O C4_O + IO_F MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_AB = { CHANGED(A1,0) | CHANGED(B1,0) | CHANGED(A2,0) | + CHANGED(B2,0) | CHANGED(A3,0) | CHANGED(B3,0) | + CHANGED(A4,0) | CHANGED(B4,0) } + + PINDLY: + SUM1_O SUM2_O SUM3_O SUM4_O = { + CASE( + CHANGED(C0,0) & TRN_LH, DELAY(3NS,7NS,10.5NS), + ANY_CH_AB & TRN_LH, DELAY(2.5NS,7NS,10.5NS), + (CHANGED(C0,0) | ANY_CH_AB) & TRN_HL, DELAY(3.5NS,7NS,10.5NS), + DELAY(4NS,8NS,11NS) ;DEFAULT + ) + } + C4_O = { + CASE( + CHANGED(C0,0) & TRN_LH, DELAY(3.5NS,5.7NS,8.5NS), + ANY_CH_AB & TRN_LH, DELAY(3NS,5.7NS,8.5NS), + CHANGED(C0,0) & TRN_HL, DELAY(2.5NS,5.4NS,8NS), + ANY_CH_AB & TRN_HL, DELAY(2.5NS,5.3NS,8NS), + DELAY(4NS,6NS,9NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74F286 PARITY GENERATOR/CHECKER 9-BIT * * FAST LOGIC DATA BOOK, TI, 1989 * JLS 8-16-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F286 A_I B_I C_I D_I E_I F_I G_I H_I I_I XMITBAR_I + PIO_B PE_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF286LOG LOGICEXP (11,13) DPWR DGND + A_I B_I C_I D_I E_I F_I G_I H_I I_I XMITBAR_I PIO_B + A B C D E F G H I XMITBAR PIO_IN PIO_OUT PE + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + I = { I_I } + XMITBAR = { XMITBAR_I } + PIO_IN = { PIO_B } + + PARITY = { A ^ B ^ C ^ D ^ E ^ F ^ G ^ H ^ I } + PIO_OUT = { ~PARITY } + PE = { (PARITY ^ PIO_IN) | ~XMITBAR } * UF286DLY PINDLY (2,1,12) DPWR DGND + PIO_OUT PE + XMITBAR + A B C D E F G H I PIO_IN PIO_OUT PE + PIO_B PE_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + POLAR = { CHANGED(PIO_IN,0) } + DATA = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | + CHANGED(D,0) | CHANGED(E,0) | CHANGED(F,0) | + CHANGED(G,0) | CHANGED(H,0) | CHANGED(I,0) } + + TRISTATE: + ENABLE LO XMITBAR + PIO_B = { + CASE ( + TRN_ZH, DELAY(-1, 3.8NS,-1), + TRN_ZL, DELAY(-1, 5.8NS,-1), + TRN_HZ, DELAY(-1, 3.8NS,-1), + TRN_LZ, DELAY(-1, 3.3NS,-1), + TRN_LH, DELAY(-1, 8.3NS,-1), + TRN_HL, DELAY(-1, 8.6NS,-1), + DELAY(-1, 8.6NS,-1) + ) + } + PINDLY: + PE_O = { + CASE ( + POLAR & TRN_LH, DELAY(-1, 4.9NS, -1), + POLAR & TRN_HL, DELAY(-1, 5.0NS, -1), + DATA & TRN_LH, DELAY(-1,10.8NS,-1), + DATA & TRN_HL, DELAY(-1,10.0NS,-1), + DELAY(-1,10.0NS,-1) + ) + } * .ENDS * *$ *--------- * 74F298 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * FAST TTL LOGIC SERIES, 1991, PHILIPS SEMICONDUCTORS * TC 08/25/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F298 S_I CPBAR_I I0A_I I1A_I I0B_I I1B_I I0C_I I1C_I I0D_I I1D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(4) DPWR DGND $D_HI $D_HI CPBAR + JA JB JC JD KA KB KC KD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * UF298LOG LOGICEXP(10,18) DPWR DGND + S_I CPBAR_I I0A_I I1A_I I0B_I I1B_I I0C_I I1C_I I0D_I I1D_I + S CPBAR I0A I1A I0B I1B I0C I1C I0D I1D JA JB JC JD KA KB KC KD + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + S = { S_I } + CPBAR = { CPBAR_I } + I0A = { I0A_I } + I1A = { I1A_I } + I0B = { I0B_I } + I1B = { I1B_I } + I0C = { I0C_I } + I1C = { I1C_I } + I0D = { I0D_I } + I1D = { I1D_I } + IS = { ~S } + KA = { ~((I0A & IS) | (S & I1A)) } + KB = { ~((I0B & IS) | (S & I1B)) } + KC = { ~((I0C & IS) | (S & I1C)) } + KD = { ~((I0D & IS) | (S & I1D)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } * UF298DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + I0A I1A I0B I1B I0C I1C I0D I1D S CPBAR + QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + TRN_LH, DELAY(4NS,5.5NS,9NS), + DELAY(4.5NS,6.5NS,9.5NS) + ) + } + FREQ: + NODE = CPBAR + MAXFREQ = 105MEG + WIDTH: + NODE = CPBAR + MIN_LO = 7NS + MIN_HI = 5NS + SETUP_HOLD: + DATA(4) = I0A I0B I0C I0D + CLOCK HL = CPBAR + SETUPTIME = 2NS + HOLDTIME = 1NS + WHEN = { S!='1 ^ CHANGED(S,0) } + SETUP_HOLD: + DATA(4) = I1A I1B I1C I1D + CLOCK HL = CPBAR + SETUPTIME = 2NS + HOLDTIME = 1NS + WHEN = { S!='0 ^ CHANGED(S,0) } + SETUP_HOLD: + DATA(1) = S + CLOCK HL = CPBAR + SETUPTIME_LO = 6NS + SETUPTIME_HI = 7NS * .ENDS * *$ *------------------------------------------------------------------------- * 74F350 4-BIT SHIFTER WITH THREE-STATE OUTPUTS * * IC15 FAST TTL LOGIC SERIES DATABOOK, 1990, PHILIPS SEMICONDUCTORS, * KN 7-14-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F350 OEBAR_I S0_I S1_I D-3_I D-2_I D-1_I D0_I D1_I D2_I D3_I + Y0_O Y1_O Y2_O Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF350LOG LOGICEXP(10,14) DPWR DGND + OEBAR_I S0_I S1_I D-3_I D-2_I D-1_I D0_I D1_I D2_I D3_I + OEBAR S0 S1 D-3 D-2 D-1 D0 D1 D2 D3 + Y0 Y1 Y2 Y3 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + OEBAR = { OEBAR_I } + S0 = { S0_I } + S1 = { S1_I } + D-3 = { D-3_I } + D-2 = { D-2_I } + D-1 = { D-1_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + * INTERMEDIATE TERMS: + /S0/S1 = { ~S0 & ~S1 } + /S0S1 = { ~S0 & S1 } + S0/S1 = { S0 & ~S1 } + S0S1 = { S0 & S1 } + * OUTPUT ASSIGNMENTS: + Y0 = { (/S0/S1 & D0) | (S0/S1 & D-1) | (/S0S1 & D-2) | (S0S1 & D-3) } + Y1 = { (/S0/S1 & D1) | (S0/S1 & D0) | (/S0S1 & D-1) | (S0S1 & D-2) } + Y2 = { (/S0/S1 & D2) | (S0/S1 & D1) | (/S0S1 & D0) | (S0S1 & D-1) } + Y3 = { (/S0/S1 & D3) | (S0/S1 & D2) | (/S0S1 & D1) | (S0S1 & D0) } * UF350DLY PINDLY (4,1,10) DPWR DGND + Y0 Y1 Y2 Y3 + OEBAR + OEBAR S0 S1 D0 D1 D2 D3 D-1 D-2 D-3 + Y0_O Y1_O Y2_O Y3_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + SELECT = { CHANGED(S0,0) | CHANGED(S1,0) } + DATA1 = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) } + DATA = { DATA1 | CHANGED(D-1,0) | CHANGED(D-2,0) | CHANGED(D-3,0) } + + TRISTATE: + ENABLE LO OEBAR + Y0_O Y1_O Y2_O Y3_O = { + CASE( + TRN_ZH, DELAY(2.5NS,5.0NS,8NS), + TRN_ZL, DELAY(4.0NS,7.0NS,10NS), + TRN_HZ, DELAY(2.0NS,3.9NS,6.5NS), + TRN_LZ, DELAY(2.0NS,4.0NS,6.5NS), + SELECT & TRN_HL, DELAY(3.0NS,6.5NS,9.5NS), + SELECT & TRN_LH, DELAY(4.0NS,7.8NS,11NS), + DATA & TRN_HL, DELAY(2.5NS,4.0NS,6.5NS), + DATA & TRN_LH, DELAY(3.0NS,4.5NS,7NS), + DELAY(5NS,8.8NS,12NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74F352 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F352 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF352LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * UF352DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT & TRN_LH, DELAY(4NS,6.5NS,12.5NS), + SELECT & TRN_HL, DELAY(3.5NS,6NS,9.5NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(3NS,6NS,8.5NS), + DATA1 & TRN_LH, DELAY(2NS,5NS,8NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(2NS,5NS,7NS), + DATA1 & TRN_HL, DELAY(1NS,3NS,5NS), + DELAY(5NS,7NS,13NS) + ) + } + Y2_O = { + CASE( + SELECT & TRN_LH, DELAY(4NS,6.5NS,12.5NS), + SELECT & TRN_HL, DELAY(3.5NS,6NS,9.5NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(3NS,6NS,8.5NS), + DATA2 & TRN_LH, DELAY(2NS,5NS,8NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(2NS,5NS,7NS), + DATA2 & TRN_HL, DELAY(1NS,3NS,5NS), + DELAY(5NS,7NS,13NS) + ) + } * .ENDS * *$ *--------- * 74F353 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * FAST Logic Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F353 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF353LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * UF353DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(3.5NS,6NS,9NS), + TRN_ZL, DELAY(3.5NS,6.5NS,9NS), + TRN_HZ, DELAY(2NS,4NS,6NS), + TRN_LZ, DELAY(1.5NS,2.5NS,7NS), + SELECT & TRN_LH, DELAY(4.5NS,9NS,12.5NS), + SELECT & TRN_HL, DELAY(3NS,6NS,9.5NS), + DATA1 & TRN_LH, DELAY(3NS,5NS,8NS), + DATA1 & TRN_HL, DELAY(1NS,3NS,5.5NS), + DELAY(5NS,10NS,13NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(3.5NS,6NS,9NS), + TRN_ZL, DELAY(3.5NS,6.5NS,9NS), + TRN_HZ, DELAY(2NS,4NS,6NS), + TRN_LZ, DELAY(1.5NS,2.5NS,7NS), + SELECT & TRN_LH, DELAY(4.5NS,9NS,12.5NS), + SELECT & TRN_HL, DELAY(3NS,6NS,9.5NS), + DATA2 & TRN_LH, DELAY(3NS,5NS,8NS), + DATA2 & TRN_HL, DELAY(1NS,3NS,5.5NS), + DELAY(5NS,10NS,13NS) + ) + } * .ENDS * *$ *--------- * 74F373 Octal D-Type Transparent Latches with 3-STATE Outputs * * The Fast Data Book, 1982, FAIRCHILD * atl 8/25/89 Update interface and model names * .subckt 74F373 OEBAR LE 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + OEBAR OE + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI LE + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_F373_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OE + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_F373_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F373_1 ugff ( + tpgqlhmn=2ns tpgqlhty=3.7ns + tpgqlhmx=5ns tpgqhlmn=1ns + tpgqhlty=1.5ns tpgqhlmx=2ns + twghmn=6ns tsudgmn=2ns + thdgmn=3ns + ) .model D_F373_2 utgate ( + tplhmn=3ns tplhty=5.3ns + tplhmx=8ns tphlmn=2ns + tphlty=3.7ns tphlmx=6ns + tpzhmn=2ns tpzhty=5ns + tpzhmx=12ns tpzlmn=2ns + tpzlty=5.6ns tpzlmx=8.5ns + tphzmn=2ns tphzty=4.5ns + tphzmx=7.5ns tplzmn=2ns + tplzty=3.8ns tplzmx=6ns + ) *$ *--------- * 74F374 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs * * The F Logic Data Book, 1987, TI * atl 7/18/89 Update interface and model names * .subckt 74F374 OCBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UD dff(8) DPWR DGND + $D_HI $D_HI CLK + D1 D2 D3 D4 D5 D6 D7 D8 + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_F374_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQS buf3a(8) DPWR DGND + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + OC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + D_F374_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F374_1 ueff ( + twclklmn=6ns twclkhmn=7ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_F374_2 utgate ( + tplhmn=3.2ns tplhty=6.1ns + tplhmx=10ns tphlmn=3.2ns + tphlty=6.1ns tphlmx=10ns + tpzhmn=1.2ns tpzhty=8.6ns + tpzhmx=12.5ns tpzlmn=1.2ns + tpzlty=5.4ns tpzlmx=8.5ns + tphzmn=1.2ns tphzty=4.9ns + tphzmx=8ns tplzmn=1.2ns + tplzty=3.9ns tplzmx=6.5ns + ) *$ *-------- * 74F377 Octal D-TYPE Flip-Flops with Clock Enable * * The F Logic Data Book, 1987, TI * atl 8/7/89 Update interface and model names * .subckt 74F377 GBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + GBAR CLK GBBUF CLKBUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} X1Q GBBUF CLKBUF 1D 1Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2Q GBBUF CLKBUF 2D 2Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3Q GBBUF CLKBUF 3D 3Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4Q GBBUF CLKBUF 4D 4Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X5Q GBBUF CLKBUF 5D 5Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X6Q GBBUF CLKBUF 6D 6Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X7Q GBBUF CLKBUF 7D 7Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X8Q GBBUF CLKBUF 8D 8Q DPWR DGND F377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt F377DAT GB CLK D Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 USET inv DPWR DGND + GB G2 + D_F377_1 IO_F MNTYMXDLY={MNTYMXDLY} UNXOR nxor DPWR DGND + GB G2 EN + D0_GATE IO_F UIN buf3 DPWR DGND + $D_X EN IN + D0_TGATE IO_F UINV inv DPWR DGND + GB G + D0_GATE IO_F UAO ao(2,2) DPWR DGND + G D GB QBUF IN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UDFF dff(1) DPWR DGND + $D_HI $D_HI CLK IN QBUF $D_NC + D_F377_2 IO_F MNTYMXDLY={MNTYMXDLY} UQOUT buf DPWR DGND + QBUF Q + D_F377_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F377_1 ugate ( + tplhmn=0.5ns tphlmn=1ns + ) .model D_F377_2 ueff ( + twclklmn=4ns tsudclkmn=2ns + ) .model D_F377_3 ugate ( + tplhty=6.5ns tphlty=7ns + ) *$ *------------------------------------------------------------------------- * 74F378 Octal D-TYPE Flip-Flops with Clock Enable * * The F Logic Data Book, 1987, TI * atl 8/7/89 Update interface and model names * .subckt 74F378 CLK GBAR 1D 2D 3D 4D 5D 6D 1Q 2Q 3Q 4Q 5Q 6Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + GBAR CLK GBBUF CLKBUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} X1Q GBBUF CLKBUF 1D 1Q DPWR DGND F378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2Q GBBUF CLKBUF 2D 2Q DPWR DGND F378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3Q GBBUF CLKBUF 3D 3Q DPWR DGND F378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4Q GBBUF CLKBUF 4D 4Q DPWR DGND F378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X5Q GBBUF CLKBUF 5D 5Q DPWR DGND F378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X6Q GBBUF CLKBUF 6D 6Q DPWR DGND F378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt F378DAT GB CLK D Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 USET inv DPWR DGND + GB G2 + D_F378_1 IO_F MNTYMXDLY={MNTYMXDLY} UNXOR nxor DPWR DGND + GB G2 EN + D0_GATE IO_F UIN buf3 DPWR DGND + $D_X EN IN + D0_TGATE IO_F UINV inv DPWR DGND + GB G + D0_GATE IO_F UAO ao(2,2) DPWR DGND + G D GB QBUF IN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UDFF dff(1) DPWR DGND + $D_HI $D_HI CLK IN QBUF $D_NC + D_F378_2 IO_F MNTYMXDLY={MNTYMXDLY} UQOUT buf DPWR DGND + QBUF Q + D_F378_3 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F378_1 ugate ( + tphlmn=6ns + ) .model D_F378_2 ueff ( + twclklmn=6ns twclkhmn=4ns + tsudclkmn=4ns + ) .model D_F378_3 ugate ( + tplhmn=2.2ns tplhmx=8.5ns + tphlmn=2.7ns tphlmx=9.5ns + tplhty=5.1ns tphlty=5.6ns + ) *$ *------------------------------------------------------------------------- * 74F379 Octal D-TYPE Flip-Flops with Clock Enable * * The F Logic Data Book, 1987, TI * atl 8/7/89 Update interface and model names * .subckt 74F379 CLK GBAR 1D 2D 3D 4D 1Q 1QBAR 2Q 2QBAR 3Q 3QBAR 4Q 4QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + GBAR CLK GBBUF CLKBUF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UGEDL buf DPWR DGND + GBBUF GBD + D_F379_1 IO_F MNTYMXDLY={MNTYMXDLY} X1Q GBD CLKBUF 1D 1Q 1QBAR DPWR DGND F379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2Q GBD CLKBUF 2D 2Q 2QBAR DPWR DGND F379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3Q GBD CLKBUF 3D 3Q 3QBAR DPWR DGND F379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4Q GBD CLKBUF 4D 4Q 4QBAR DPWR DGND F379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt F379DAT GB CLK D Q QB DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 USET inv DPWR DGND + GB G2 + D_F379_2 IO_F MNTYMXDLY={MNTYMXDLY} UNXOR nxor DPWR DGND + GB G2 EN + D0_GATE IO_F UIN buf3 DPWR DGND + $D_X EN IN + D0_TGATE IO_F UINV inv DPWR DGND + GB G + D0_GATE IO_F UAO ao(2,2) DPWR DGND + G D GB QBUF IN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UDFF dff(1) DPWR DGND + $D_HI $D_HI CLK IN QBUF QBBUF + D_F379_3 IO_F MNTYMXDLY={MNTYMXDLY} UQOUT bufa(2) DPWR DGND + QBUF QBBUF Q QB + D_F379_4 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F379_1 ugate ( + tplhmn=1ns tphlmn=1ns + ) .model D_F379_2 ugate ( + tplhmn=2ns tphlmn=2ns + ) .model D_F379_3 ueff ( + twclklmn=5ns twclkhmn=4ns + tsudclkmn=3ns thdclkmn=1ns + ) .model D_F379_4 ugate ( + tplhmn=3.2ns tplhmx=7.5ns + tphlmn=4.2ns tphlmx=9.5ns + tplhty=4.6ns tphlty=6.1ns + ) *$ *--------- * 74F381 ALU / FUNCTION GENERATOR * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-8-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F381 S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + F3_O F2_O F1_O F0_O PBAR_O GBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF381LOG LOGICEXP (12,18) DPWR DGND + S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3 F2 F1 F0 PBAR GBAR + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + S2 = { S2_I } + S1 = { S1_I } + S0 = { S0_I } + CN = { CN_I } + A3 = { A3_I } + A2 = { A2_I } + A1 = { A1_I } + A0 = { A0_I } + B3 = { B3_I } + B2 = { B2_I } + B1 = { B1_I } + B0 = { B0_I } + A3BAR = { ~A3 } + A2BAR = { ~A2 } + A1BAR = { ~A1 } + A0BAR = { ~A0 } + B3BAR = { ~B3 } + B2BAR = { ~B2 } + B1BAR = { ~B1 } + B0BAR = { ~B0 } + + L5 = { S0 | S1 } + L4 = { S1 | S2 } + L3 = { S0 | ~S1 } + L2 = { ~(S0 & S1 & ~S2) } + L1 = { (S0 & S1) | ~S2 } + L0 = { (S0 | S1) & ~S2 } + TOP0 = { ~( (A0BAR & B0BAR & L4 & L3) | (A0 & B0BAR & L5 & L3 & L2) | + (A0BAR & B0 & L4 & L2) ) } + BOT0 = { ~( (A0BAR & B0BAR & L5 & L2 & L1) | (A0 & B0BAR & L4 & L3) | + (A0BAR & B0 & L4 & L3) | (A0 & B0 & L5 & L2) ) } + TOP1 = { ~( (A1BAR & B1BAR & L4 & L3) | (A1 & B1BAR & L5 & L3 & L2) | + (A1BAR & B1 & L4 & L2) ) } + BOT1 = { ~( (A1BAR & B1BAR & L5 & L2 & L1) | (A1 & B1BAR & L4 & L3) | + (A1BAR & B1 & L4 & L3) | (A1 & B1 & L5 & L2) ) } + TOP2 = { ~( (A2BAR & B2BAR & L4 & L3) | (A2 & B2BAR & L5 & L3 & L2) | + (A2BAR & B2 & L4 & L2) ) } + BOT2 = { ~( (A2BAR & B2BAR & L5 & L2 & L1) | (A2 & B2BAR & L4 & L3) | + (A2BAR & B2 & L4 & L3) | (A2 & B2 & L5 & L2) ) } + TOP3 = { ~( (A3BAR & B3BAR & L4 & L3) | (A3 & B3BAR & L5 & L3 & L2) | + (A3BAR & B3 & L4 & L2) ) } + BOT3 = { ~( (A3BAR & B3BAR & L5 & L2 & L1) | (A3 & B3BAR & L4 & L3) | + (A3BAR & B3 & L4 & L3) | (A3 & B3 & L5 & L2) ) } + + F0 = { BOT0 ^ ~( CN & L0) } + F1 = { BOT1 ^ ~( ( CN & L0 & TOP0) | + (BOT0 & L0 & TOP0) ) } + F2 = { BOT2 ^ ~( ( CN & L0 & TOP0 & TOP1) | + (BOT0 & L0 & TOP0 & TOP1) | + (BOT1 & L0 & TOP1) ) } + F3 = { BOT3 ^ ~( ( CN & L0 & TOP0 & TOP1 & TOP2) | + (BOT0 & L0 & TOP0 & TOP1 & TOP2) | + (BOT1 & L0 & TOP1 & TOP2) | + (BOT2 & L0 & TOP2) ) } + PBAR = { ~(TOP0 & TOP1 & TOP2 & TOP3) } + GBAR = { ~( (~PBAR & BOT0) | + (TOP1 & TOP2 & TOP3 & BOT1) | + (TOP2 & TOP3 & BOT2) | + (TOP3 & BOT3) ) } * UF381DLY PINDLY (6,0,12) DPWR DGND + F3 F2 F1 F0 PBAR GBAR + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3_O F2_O F1_O F0_O PBAR_O GBAR_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3,0) | CHANGED(A2,0) | CHANGED(A1,0) | CHANGED(A0,0) | + CHANGED(B3,0) | CHANGED(B2,0) | CHANGED(B1,0) | CHANGED(B0,0) } + MODE = { CHANGED(S2,0) | CHANGED(S1,0) | CHANGED(S0,0) } + + PINDLY: + F3_O F2_O F1_O F0_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.5NS,6.0NS,12.5NS), + CARRY & TRN_HL, DELAY(2.5NS,4.5NS, 7.5NS), + OPER & TRN_LH, DELAY(3.5NS,7.0NS,16.0NS), + OPER & TRN_HL, DELAY(3.0NS,6.0NS,10.0NS), + MODE & TRN_LH, DELAY(5.0NS,9.0NS,21.5NS), + MODE & TRN_HL, DELAY(4.0NS,7.5NS,11.5NS), + DELAY(5.0NS,9.0NS,21.5NS) + ) + } + GBAR_O = { + CASE ( + OPER & TRN_LH, DELAY(3.5NS,6.5NS,10.0NS), + OPER & TRN_HL, DELAY(5.0NS,6.0NS, 9.0NS), + MODE & TRN_LH, DELAY(5.0NS,7.5NS,12.5NS), + MODE & TRN_HL, DELAY(5.0NS,8.5NS,14.0NS), + DELAY(5.0NS,8.5NS,14.0NS) + ) + } + PBAR_O = { + CASE ( + OPER & TRN_LH, DELAY(3.0NS,5.5NS, 9.0NS), + OPER & TRN_HL, DELAY(3.5NS,6.0NS, 9.0NS), + MODE & TRN_LH, DELAY(5.0NS,7.5NS,12.5NS), + MODE & TRN_HL, DELAY(5.0NS,8.5NS,14.0NS), + DELAY(5.0NS,8.5NS,14.0NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74F382 ALU / FUNCTION GENERATOR * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-8-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F382 S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + F3_O F2_O F1_O F0_O OVR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF382LOG LOGICEXP (12,18) DPWR DGND + S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3 F2 F1 F0 OVR CN+4 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + S2 = { S2_I } + S1 = { S1_I } + S0 = { S0_I } + CN = { CN_I } + A3 = { A3_I } + A2 = { A2_I } + A1 = { A1_I } + A0 = { A0_I } + B3 = { B3_I } + B2 = { B2_I } + B1 = { B1_I } + B0 = { B0_I } + S2BAR = { ~S2 } + S1BAR = { ~S1 } + S0BAR = { ~S0 } + A3BAR = { ~A3 } + A2BAR = { ~A2 } + A1BAR = { ~A1 } + A0BAR = { ~A0 } + B3BAR = { ~B3 } + B2BAR = { ~B2 } + B1BAR = { ~B1 } + B0BAR = { ~B0 } + + L6 = { ~( (S0 & S1BAR & S2BAR) | (S0 & S1 & S2) | + (S0BAR & S1 & S2BAR) ) } + L5 = { ~( (S0 & S1BAR ) | (S0 & S2) | + (S0BAR & S1 ) ) } + L4 = { ~( ( S1BAR & S2 ) | (S0 & S1 ) ) } + L3 = { S0BAR | S1 | S2 } + L2 = { S0BAR | S1BAR | S2 } + L1 = { S0 | S1BAR | S2 } + L0 = { (S0 & S2BAR) | ( S1 & S2BAR) } + TOP0 = { ~( (A0BAR & B0BAR & L6) | (A0 & B0BAR & L4) | + (A0BAR & B0 & L4) | (A0 & B0 & L5) ) } + BOT0 = { ~( (A0BAR & B0BAR ) | (A0 & B0BAR & L1) | + (A0BAR & B0 & L3) | (A0 & B0 & L2) ) } + TOP1 = { ~( (A1BAR & B1BAR & L6) | (A1 & B1BAR & L4) | + (A1BAR & B1 & L4) | (A1 & B1 & L5) ) } + BOT1 = { ~( (A1BAR & B1BAR ) | (A1 & B1BAR & L1) | + (A1BAR & B1 & L3) | (A1 & B1 & L2) ) } + TOP2 = { ~( (A2BAR & B2BAR & L6) | (A2 & B2BAR & L4) | + (A2BAR & B2 & L4) | (A2 & B2 & L5) ) } + BOT2 = { ~( (A2BAR & B2BAR ) | (A2 & B2BAR & L1) | + (A2BAR & B2 & L3) | (A2 & B2 & L2) ) } + TOP3 = { ~( (A3BAR & B3BAR & L6) | (A3 & B3BAR & L4) | + (A3BAR & B3 & L4) | (A3 & B3 & L5) ) } + BOT3 = { ~( (A3BAR & B3BAR ) | (A3 & B3BAR & L1) | + (A3BAR & B3 & L3) | (A3 & B3 & L2) ) } + + F0 = { ~(TOP0 ^ ~( CN & L0) ) } + F1 = { ~(TOP1 ^ ~( ( CN & L0 & TOP0) | + (BOT0 & L0 ) ) ) } + F2 = { ~(TOP2 ^ ~( ( CN & L0 & TOP0 & TOP1) | + (BOT0 & L0 & TOP1) | + (BOT1 & L0 ) ) ) } + PRE3 = { ~( ( CN & L0 & TOP0 & TOP1 & TOP2) | + (BOT0 & L0 & TOP1 & TOP2) | + (BOT1 & L0 & TOP2) | + (BOT2 & L0 ) ) } + F3 = { ~(TOP3 ^ PRE3) } + CN+4 = { (TOP0 & TOP1 & TOP2 & TOP3 & CN) | + (TOP1 & TOP2 & TOP3 & BOT0) | + (TOP2 & TOP3 & BOT1) | + (TOP3 & BOT2) | + (BOT3) } + OVR = { ~CN+4 ^ PRE3 } * UF382DLY PINDLY (6,0,12) DPWR DGND + F3 F2 F1 F0 OVR CN+4 + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3_O F2_O F1_O F0_O OVR_O CN+4_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3,0) | CHANGED(A2,0) | CHANGED(A1,0) | CHANGED(A0,0) | + CHANGED(B3,0) | CHANGED(B2,0) | CHANGED(B1,0) | CHANGED(B0,0) } + MODE = { CHANGED(S2,0) | CHANGED(S1,0) | CHANGED(S0,0) } + + PINDLY: + F3_O F2_O F1_O F0_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.5NS, 7.0NS,13.5NS), + CARRY & TRN_HL, DELAY(2.5NS, 4.5NS, 7.5NS), + OPER & TRN_LH, DELAY(3.5NS, 8.0NS,17.0NS), + OPER & TRN_HL, DELAY(2.5NS, 6.0NS,11.0NS), + MODE & TRN_LH, DELAY(5.5NS, 9.0NS,16.0NS), + MODE & TRN_HL, DELAY(5.5NS, 7.5NS,12.0NS), + DELAY(5.5NS, 9.0NS,17.0NS) + ) + } + OVR_O = { + CASE ( + CARRY & TRN_LH, DELAY(4.0NS, 9.0NS,15.0NS), + CARRY & TRN_HL, DELAY(3.0NS, 5.0NS, 7.0NS), + OPER & TRN_LH, DELAY(5.5NS, 9.0NS,16.5NS), + OPER & TRN_HL, DELAY(3.5NS, 6.5NS,10.0NS), + MODE & TRN_LH, DELAY(6.5NS,10.5NS,17.0NS), + MODE & TRN_HL, DELAY(5.0NS, 8.0NS,12.0NS), + DELAY(6.5NS,10.5NS,17.0NS) + ) + } + CN+4_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.5NS, 4.5NS, 6.5NS), + CARRY & TRN_HL, DELAY(3.5NS, 5.0NS, 7.0NS), + OPER & TRN_LH, DELAY(3.5NS, 7.0NS,11.5NS), + OPER & TRN_HL, DELAY(3.5NS, 6.5NS,10.5NS), + MODE & TRN_LH, DELAY(6.5NS,10.5NS,17.0NS), + MODE & TRN_HL, DELAY(5.0NS, 8.0NS,12.0NS), + DELAY(6.5NS,10.5NS,17.0NS) + ) + } * .ENDS * *$ *--------- * 74F393 COUNTER BINARY 4-BIT, ASYNCHRONOUS * * IC15 FAST TTL LOGIC SERIES, 1991, PHILIPS SEMICONDUCTORS * JLS 7-28-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F393 CPBAR_I MR_I Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI MRBAR CPBAR $D_HI $D_HI Q0 $D_NC + D0_EFF IO_F U2 JKFF(1) DPWR DGND + $D_HI MRBAR Q0 $D_HI $D_HI Q1 $D_NC + D0_EFF IO_F U3 JKFF(1) DPWR DGND + $D_HI MRBAR Q1 $D_HI $D_HI Q2 $D_NC + D0_EFF IO_F U4 JKFF(1) DPWR DGND + $D_HI MRBAR Q2 $D_HI $D_HI Q3 $D_NC + D0_EFF IO_F U5 BUFA(2) DPWR DGND + CPBAR_I MR_I + CPBAR MR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U6 INV DPWR DGND + MR MRBAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} * UF393DLY PINDLY (4,0,2) DPWR DGND + Q0 Q1 Q2 Q3 + MR CPBAR + Q0_O Q1_O Q2_O Q3_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED = { CHANGED_HL(CPBAR,0) } + CLEARED = { CHANGED_LH(MR,0) } + + PINDLY: + Q0_O = { + CASE ( + CLOCKED & TRN_LH, DELAY( 3.5NS, 5.5NS, 9.0NS), + CLOCKED & TRN_HL, DELAY( 5.0NS, 7.0NS,10.5NS), + DELAY( 4.0NS, 6.0NS, 9.0NS) + ) + } + Q1_O = { + CASE ( + CLEARED , DELAY( 4.0NS, 6.0NS, 9.0NS), + CLOCKED & TRN_LH, DELAY( 4.5NS, 7.0NS,13.0NS), + DELAY( 7.0NS, 9.5NS,13.0NS) + ) + } + Q2_O = { + CASE ( + CLEARED , DELAY( 4.0NS, 6.0NS, 9.0NS), + CLOCKED & TRN_LH, DELAY( 7.0NS,10.0NS,15.0NS), + DELAY( 9.0NS,11.5NS,15.5NS) + ) + } + Q3_O = { + CASE ( + CLEARED , DELAY( 4.0NS, 6.0NS, 9.0NS), + CLOCKED & TRN_LH, DELAY(10.0NS,12.5NS,17.0NS), + DELAY(11.5NS,14.0NS,17.5NS) + ) + } + + FREQ: + NODE = CPBAR + MAXFREQ = 100MEGHZ + WIDTH: + NODE = CPBAR + MIN_LO = 4.0NS + MIN_HI = 5.0NS + WIDTH: + NODE = MR + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(1) = MR + CLOCK HL = CPBAR + RELEASETIME_HL = 3NS * .ENDS * *$ *------------------------------------------------------------------------- * 74F398 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * TC 08/26/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F398 S_I CP_I I0A_I I1A_I I0B_I I1B_I I0C_I I1C_I I0D_I I1D_I + QA_O QB_O QC_O QD_O QABAR_O QBBAR_O QCBAR_O QDBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CP + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_F * UF398LOG LOGICEXP(10,14) DPWR DGND + S_I CP_I I0A_I I1A_I I0B_I I1B_I I0C_I I1C_I I0D_I I1D_I + S CP I0A I1A I0B I1B I0C I1C I0D I1D DA DB DC DD + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + S = { S_I } + CP = { CP_I } + I0A = { I0A_I } + I1A = { I1A_I } + I0B = { I0B_I } + I1B = { I1B_I } + I0C = { I0C_I } + I1C = { I1C_I } + I0D = { I0D_I } + I1D = { I1D_I } + IS = { ~S } + DA = { (I0A & IS) | (S & I1A) } + DB = { (I0B & IS) | (S & I1B) } + DC = { (I0C & IS) | (S & I1C) } + DD = { (I0D & IS) | (S & I1D) } * UF398DLY PINDLY (8,0,10) DPWR DGND + QA QB QC QD QABAR QBBAR QCBAR QDBAR + I0A I1A I0B I1B I0C I1C I0D I1D S CP + QA_O QB_O QC_O QD_O QABAR_O QBBAR_O QCBAR_O QDBAR_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O QABAR_O QBBAR_O QCBAR_O QDBAR_O = { + CASE( + TRN_LH, DELAY(3NS,5.7NS,8.5NS), + DELAY(3NS,6.5NS,9NS) + ) + } + FREQ: + NODE = CP + MAXFREQ = 90MEG + WIDTH: + NODE = CP + MIN_LO = 6NS + MIN_HI = 4NS + SETUP_HOLD: + DATA(4) = I0A I0B I0C I0D + CLOCK LH = CP + SETUPTIME = 3NS + HOLDTIME = 1NS + WHEN = { S!='1 ^ CHANGED(S,0) } + SETUP_HOLD: + DATA(4) = I1A I1B I1C I1D + CLOCK LH = CP + SETUPTIME = 3NS + HOLDTIME = 1NS + WHEN = { S!='0 ^ CHANGED(S,0) } + SETUP_HOLD: + DATA(1) = S + CLOCK LH = CP + SETUPTIME = 8.5NS * .ENDS * *$ *------------------------------------------------------------------------- * 74F399 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * TC 08/26/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F399 S_I CP_I I0A_I I1A_I I0B_I I1B_I I0C_I I1C_I I0D_I I1D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CP + DA DB DC DD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * UF399LOG LOGICEXP(10,14) DPWR DGND + S_I CP_I I0A_I I1A_I I0B_I I1B_I I0C_I I1C_I I0D_I I1D_I + S CP I0A I1A I0B I1B I0C I1C I0D I1D DA DB DC DD + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + S = { S_I } + CP = { CP_I } + I0A = { I0A_I } + I1A = { I1A_I } + I0B = { I0B_I } + I1B = { I1B_I } + I0C = { I0C_I } + I1C = { I1C_I } + I0D = { I0D_I } + I1D = { I1D_I } + IS = { ~S } + DA = { (I0A & IS) | (S & I1A) } + DB = { (I0B & IS) | (S & I1B) } + DC = { (I0C & IS) | (S & I1C) } + DD = { (I0D & IS) | (S & I1D) } * UF399DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + I0A I1A I0B I1B I0C I1C I0D I1D S CP + QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + TRN_LH, DELAY(3NS,5.7NS,8.5NS), + DELAY(3NS,6.5NS,9NS) + ) + } + FREQ: + NODE = CP + MAXFREQ = 90MEG + WIDTH: + NODE = CP + MIN_LO = 6NS + MIN_HI = 4NS + SETUP_HOLD: + DATA(4) = I0A I0B I0C I0D + CLOCK LH = CP + SETUPTIME = 3NS + HOLDTIME = 1NS + WHEN = { S!='1 ^ CHANGED(S,0) } + SETUP_HOLD: + DATA(4) = I1A I1B I1C I1D + CLOCK LH = CP + SETUPTIME = 3NS + HOLDTIME = 1NS + WHEN = { S!='0 ^ CHANGED(S,0) } + SETUP_HOLD: + DATA(1) = S + CLOCK LH = CP + SETUPTIME = 8.5NS * .ENDS * *$ *--------- * 74F518 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * F LOGIC DATA BOOK, 1989, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F518 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQ_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UF518LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQ + D0_GATE IO_F IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQ = { (PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UF518DLY PINDLY (1,0,17) DPWR DGND + PEQ + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQ_O + IO_F_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQ_O = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(2NS,-1,7.5NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(4.5NS,-1,14.5NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(2NS,-1,10NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(4NS,-1,10NS), + DELAY(5NS,-1,15NS) + ) + } * .ENDS * *$ *--------- * 74F519 8-BIT IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * F LOGIC DATA BOOK, 1989, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F519 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQ_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UF519LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQ + D0_GATE IO_F IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQ = { (PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UF519DLY PINDLY (1,0,17) DPWR DGND + PEQ + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQ_O + IO_F_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQ_O = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(2NS,-1,7.5NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(4.5NS,-1,14.5NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(2NS,-1,10NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(4NS,-1,15NS), + DELAY(5NS,-1,16NS) + ) + } * .ENDS * *$ *--------- * 74F520 8-BIT IDENTITY COMPARATORS * * F LOGIC DATA BOOK, 1989, TI * NH 8/24/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F520 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UF520LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_F IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UF520DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_F MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_LH, DELAY(3.4NS,4.6NS,6.4NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(4.9NS,7.5NS,10.4NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(3.7NS,5.7NS,8.7NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(4.4NS,7NS,10.3NS), + DELAY(5NS,8NS,11NS) + ) + } * .ENDS * *$ *--------- * 74F521 8-BIT IDENTITY COMPARATORS * * F LOGIC DATA BOOK, 1989, TI * NH 8/24/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F521 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * UF521LOG LOGICEXP(17,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I GBAR_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GBAR PEQBAR + D0_GATE IO_F IO_LEVEL = {IO_LEVEL} + + LOGIC: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * UF521DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_F MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_LH, DELAY(2.2NS,4.6NS,7.5NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(2.7NS,6.1NS,10NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(2.7NS,6.6NS,11NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(3.2NS,6.6NS,11NS), + DELAY(4NS,7NS,12NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74F524 8-bit Registered Comparator * * The Fast Data Book, 1982, FAIRCHILD * atl 8/30/89 Update interface and model names * .subckt 74F524 CP S0 S1 SEBAR C/SI M C/SO LT GT EQ I/O0 I/O1 I/O2 I/O3 I/O4 + I/O5 I/O6 I/O7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(6) DPWR DGND + CP S0 S1 C/SI M SEBAR + CPBF S0BF S1BF CSI MBF SEBF + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UIO bufa(8) DPWR DGND + I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 + I0 I1 I2 I3 I4 I5 I6 I7 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UINV inva(4) DPWR DGND + SEBF S0BF S1BF SHF SE S0B S1B SHFB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UMISC anda(2,5) DPWR DGND + S0B S1B + S0B S1BF + S0BF S1B + S0BF S1BF + CTR CPBF + HLD REA SHF LAD CK + D0_GATE IO_F UREHX1 bufa(2) DPWR DGND + REA HLD REAX HLDX + D0_GATE IO_F UREHX2 bufa(2) DPWR DGND + REA HLD REAX HLDX + D_F524_1 IO_F MNTYMXDLY={MNTYMXDLY} URHD or(2) DPWR DGND + REAX HLDX RHD + D0_GATE IO_F UCTRL nora(2,2) DPWR DGND + CPBF CTR RHD TEMP TEMP CTR + D0_GATE IO_F UIN buf3a(8) DPWR DGND + OA OB OC OD OE OF OG OH + REA + I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 + D_F524_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCSIX1 buf DPWR DGND + CSI CSIX + D0_GATE IO_F UCSIX2 buf DPWR DGND + CSI CSIX + D_F524_3 IO_F MNTYMXDLY={MNTYMXDLY} XA CK CSIX SHF LAD I0 OA DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XB CK OA SHF LAD I1 OB DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XC CK OB SHF LAD I2 OC DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XD CK OC SHF LAD I3 OD DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XE CK OD SHF LAD I4 OE DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XF CK OE SHF LAD I5 OF DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XG CK OF SHF LAD I6 OG DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XH CK OG SHF LAD I7 OH DPWR DGND F524SHR + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} USRO dff(1) DPWR DGND + $D_HI $D_HI CK OH SRO $D_NC + D_F524_4 IO_F MNTYMXDLY={MNTYMXDLY} UAB7 xora(2) DPWR DGND + OH MBF I7 MBF A7 B7 + D0_GATE IO_F XCMP OA OB OC OD OE OF OG A7 I0 I1 I2 I3 I4 I5 I6 B7 LTI GTI EQI DPWR DGND F524CMP + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCSB1 buf DPWR DGND + CSI CSID1 + D_F524_5 IO_F MNTYMXDLY={MNTYMXDLY} UCSB2 buf DPWR DGND + CSI CSID2 + D_F524_6 IO_F MNTYMXDLY={MNTYMXDLY} USED1 buf DPWR DGND + SE SED1 + D_F524_7 IO_F MNTYMXDLY={MNTYMXDLY} UOEN nanda(2,2) DPWR DGND + CSID1 SE CSID2 SED1 OEN1 OEN2 + D0_GATE IO_F UT0 inv DPWR DGND + CK T0 + D_F524_8 IO_F MNTYMXDLY={MNTYMXDLY} UT inva(9) DPWR DGND + MBF I0 I1 I2 I3 I4 I5 I6 I7 + T1 T2 T3 T4 T5 T6 T7 T8 T9 + D_F524_9 IO_F MNTYMXDLY={MNTYMXDLY} UEN nxora(10) DPWR DGND + CK T0 + MBF T1 + I0 T2 + I1 T3 + I2 T4 + I3 T5 + I4 T6 + I5 T7 + I6 T8 + I7 T9 + ENEQ EM E0 E1 E2 + E3 E4 E5 E6 E7 + D_F524_10 IO_F MNTYMXDLY={MNTYMXDLY} UE8 or(8) DPWR DGND + E0 E1 E2 E3 E4 E5 E6 E7 E8 + D0_GATE IO_F UG136 nora(2,3) DPWR DGND + ENEQ E8 ENEQ EM G2 G4 G1 G3 G6 + D0_GATE IO_F UG24 anda(2,2) DPWR DGND + G1 EM G3 E8 G2 G4 + D0_GATE IO_F UG57 bufa(2) DPWR DGND + G2 G4 G5 G7 + D0_GATE IO_F UGLTT bufa(3) DPWR DGND + LTI GTI EQI LTT GTT EQT + D_F524_11 IO_F MNTYMXDLY={MNTYMXDLY} ULTID1 buf3 DPWR DGND + LTT G6 LTID + D_F524_12 IO_F MNTYMXDLY={MNTYMXDLY} ULTID2 buf3 DPWR DGND + LTT G5 LTID + D_F524_13 IO_F MNTYMXDLY={MNTYMXDLY} ULTID3 buf3 DPWR DGND + LTT G7 LTID + D_F524_14 IO_F MNTYMXDLY={MNTYMXDLY} ULT or(2) DPWR DGND + LTID OEN1 LT + D_F524_15 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UGTID1 buf3 DPWR DGND + GTT G6 GTID + D_F524_16 IO_F MNTYMXDLY={MNTYMXDLY} UGTID2 buf3 DPWR DGND + GTT G5 GTID + D_F524_17 IO_F MNTYMXDLY={MNTYMXDLY} UGTID3 buf3 DPWR DGND + GTT G7 GTID + D_F524_18 IO_F MNTYMXDLY={MNTYMXDLY} UGT or(2) DPWR DGND + GTID OEN2 GT + D_F524_19 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UENEQ inv DPWR DGND + ENEQ ENEQB + D0_GATE IO_F UEQID1 buf3 DPWR DGND + EQT ENEQ EQIDE + D_F524_20 IO_F MNTYMXDLY={MNTYMXDLY} UEQID2 buf3 DPWR DGND + EQT ENEQB EQIDE + D_F524_21 IO_F MNTYMXDLY={MNTYMXDLY} UEQ or(2) DPWR DGND + EQIDE SEBF EQ + D_F524_22 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} USHFD buf DPWR DGND + SHF SHFD + D_F524_23 IO_F MNTYMXDLY={MNTYMXDLY} USHFBD inv DPWR DGND + SHF SHFBD + D_F524_23 IO_F MNTYMXDLY={MNTYMXDLY} UEQIC1 buf3 DPWR DGND + EQT ENEQ EQIDC + D_F524_24 IO_F MNTYMXDLY={MNTYMXDLY} UEQIC2 buf3 DPWR DGND + EQT ENEQB EQIDC + D_F524_25 IO_F MNTYMXDLY={MNTYMXDLY} UC/SO ao(2,2) DPWR DGND + SRO SHFD EQIDC SHFBD C/SO + D_F524_26 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt F524SHR CK SR SHF LAD D O DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 ULASHX1 bufa(2) DPWR DGND + LAD SHF LADX SHFX + D0_GATE IO_F ULASHX2 bufa(2) DPWR DGND + LAD SHF LADX SHFX + D_F524_27 IO_F MNTYMXDLY={MNTYMXDLY} UDIN ao(2,2) DPWR DGND + D LADX SR SHFX DIN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UO dff(1) DPWR DGND + $D_HI $D_HI CK DIN O $D_NC + D_F524_28 IO_F MNTYMXDLY={MNTYMXDLY} .ends * .subckt F524CMP OA OB OC OD OE OF OG OH I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 + I/O7 LT GT EQ DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UEP anda(2,6) DPWR DGND + EQ7 EQ6 + EQ6P EQ5 + EQ5P EQ4 + EQ4P EQ3 + EQ3P EQ2 + EQ2P EQ1 + EQ6P EQ5P EQ4P EQ3P EQ2P EQ1P + D0_GATE IO_F X0 OA I/O0 EQ1P GT0 LT0 EQ0 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X1 OB I/O1 EQ2P GT1 LT1 EQ1 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 OC I/O2 EQ3P GT2 LT2 EQ2 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 OD I/O3 EQ4P GT3 LT3 EQ3 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4 OE I/O4 EQ5P GT4 LT4 EQ4 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X5 OF I/O5 EQ6P GT5 LT5 EQ5 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X6 OG I/O6 EQ7 GT6 LT6 EQ6 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X7 OH I/O7 $D_HI GT7 LT7 EQ7 DPWR DGND F524MAG + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UGLT ora(8,2) DPWR DGND + GT0 GT1 GT2 GT3 GT4 GT5 GT6 GT7 + LT0 LT1 LT2 LT3 LT4 LT5 LT6 LT7 + GT LT + D0_GATE IO_F UEQ and(8) DPWR DGND + EQ0 EQ1 EQ2 EQ3 EQ4 EQ5 EQ6 EQ7 EQ + D0_GATE IO_F .ends * .subckt F524MAG A B EP GT LT EQ DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(2) DPWR DGND + A B AB BB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UAND anda(2,4) DPWR DGND + AB B + A BB + C EP + D EP + C D LT GT + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UEQ nor(2) DPWR DGND + C D EQ + D0_GATE IO_F .ends * .model D_F524_1 ugate ( + tplhmn=9.9ns tphlmn=9.9ns + ) .model D_F524_2 utgate ( + tpzhmn=6ns tpzhty=10.1ns + tpzhmx=14ns tpzlmn=6.5ns + tpzlty=11.2ns tpzlmx=15.5ns + tphzmn=5ns tphzty=7.9ns + tphzmx=11ns tplzmn=5.5ns + tplzty=9.6ns tplzmx=13.5ns + ) .model D_F524_3 ugate ( + tphlmn=2ns + ) .model D_F524_4 ueff ( + twclkhmn=4ns + ) .model D_F524_5 ugate ( + tplhmn=0.5ns tplhty=0.3ns + tplhmx=0.501ns tphlmn=3ns + tphlty=5ns tphlmx=6ns + ) .model D_F524_6 ugate ( + tpHLmn=1.5ns tpHLty=2.4ns + tpHLmx=3ns tpLHty=1ps + tpLHmx=0.5ns + ) .model D_F524_7 ugate ( + tplhmn=0.5ns tplhty=1ps + tplhmx=1ps + ) .model D_F524_8 ugate ( + tphlmn=10.5ns tphlty=17.5ns + tphlmx=24.5ns + ) .model D_F524_9 ugate ( + tplhmn=10.5ns tplhty=17.5ns + tplhmx=24.5ns tphlmn=10.5ns + tphlty=17.5ns tphlmx=24.5ns + ) .model D_F524_10 ugate ( + tplhmn=0.1ns tphlmn=0.1ns + ) .model D_F524_11 ugate ( + tplhmn=0.5ns tphlmn=0.5ns + ) .model D_F524_12 utgate ( + tplhmn=3.4ns tplhty=6.4ns + tplhmx=8.4ns tphlmn=1.9ns + tphlty=2.8ns tphlmx=3.9ns + ) .model D_F524_13 utgate ( + tplhmn=3ns tplhty=5.4ns + tplhmx=8.5ns tphlmn=1.5ns + tphlty=2.7ns tphlmx=3.5ns + ) .model D_F524_14 utgate ( + tplhmn=1.5ns tplhty=2.7ns + tplhmx=5.5ns tphlmn=2ns + tphlty=3.5ns tphlmx=5.5ns + ) .model D_F524_15 ugate ( + tplhmn=5ns tplhty=8.5ns + tplhmx=12ns tphlmn=3.5ns + tphlty=6.2ns tphlmx=9ns + ) .model D_F524_16 utgate ( + tplhmn=1.9ns tplhty=3.4ns + tplhmx=4.4ns tphlmn=5.4ns + tphlty=8.2ns tphlmx=11.9ns + ) .model D_F524_17 utgate ( + tplhmn=0ns tplhty=0.4ns + tplhmx=0.5ns tphlmn=3.5ns + tphlty=5.1ns tphlmx=7.5ns + ) .model D_F524_18 utgate ( + tplhmn=0.5ns tplhty=1.1ns + tplhmx=1.5ns tphlmn=3.5ns + tphlty=4.3ns tphlmx=6ns + ) .model D_F524_19 ugate ( + tplhmn=7.5ns tplhty=12.5ns + tplhmx=17ns tphlmn=3ns + tphlty=6.5ns tphlmx=9ns + ) .model D_F524_20 utgate ( + tplhmn=5.9ns tplhty=10.6ns + tplhmx=14.9ns tphlmn=0.4ns + tphlty=1.8ns tphlmx=2.9ns + ) .model D_F524_21 utgate ( + tplhmn=5ns tplhty=9.2ns + tplhmx=13ns tphlmn=3ns + tphlty=4.3ns tphlmx=6ns + ) .model D_F524_22 ugate ( + tplhmn=4ns tplhty=6.3ns + tplhmx=9ns tphlmn=2.5ns + tphlty=4.6ns tphlmx=6.5ns + ) .model D_F524_23 ugate ( + tplhmn=2ns tplhty=3ns + tplhmx=4ns tphlmn=1ns + tphlty=1.7ns tphlmx=2ns + ) .model D_F524_24 utgate ( + tplhmn=2.9ns tplhty=5.6ns + tplhmx=9.4ns + ) .model D_F524_25 utgate ( + tplhmn=3.5ns tplhty=6.4ns + tplhmx=9.5ns tphlmn=0.5ns + tphlty=2.3ns tphlmx=2.5ns + ) .model D_F524_26 ugate ( + tplhmn=5ns tplhty=8.3ns + tplhmx=11.5ns tphlmn=5ns + tphlty=7.6ns tphlmx=11ns + ) .model D_F524_27 ugate ( + tplhmn=5ns tphlmn=5ns + ) .model D_F524_28 ueff ( + twclkhmn=4ns tsudclkmn=5ns + tpclkqlhmn=0.1ns tpclkqhlmn=0.1ns + ) *$ *--------- * 74F533 Octal D-TYPE Transparent Latches with 3-STATE Outputs * * The High-Speed CMOS Logic Data Book, 1988, TI * atl 9/18/89 Update interface and model names * .subckt 74F533 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UQI dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + D_F533_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQBAR buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_F533_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F533_1 ugff ( + twghmn=6ns tsudgmn=3ns + thdgmn=2ns tpgqlhmn=1ns + tpgqlhty=1.6ns tpgqlhmx=3ns + tpgqhlty=0.4ns tpgqhlmx=1ps + ) .model D_F533_2 utgate ( + tplhmn=3.2ns tplhty=6.5ns + tplhmx=10ns tphlmn=2.2ns + tphlty=4.8ns tphlmx=8ns + tpzhmn=1.2ns tpzhty=7.3ns + tpzhmx=11ns tpzlmn=1.2ns + tpzlty=4.7ns tpzlmx=7.5ns + tphzmn=1.2ns tphzty=4.3ns + tphzmx=7ns tplzmn=1.2ns + tplzty=3.7ns tplzmx=6.5ns + ) *$ *--------- * 74F534 Octal D-TYPE Edge-Triggered Flip-Flops with 3-STATE Outputs * * The F Logic Data Book, 1987, TI * atl 7/19/89 Update interface and model names * .subckt 74F534 OCBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR + 6QBAR 7QBAR 8QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UDFF dff(8) DPWR DGND + $D_HI $D_HI CLK + 1D 2D 3D 4D 5D 6D 7D 8D + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_F534_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UOCQ inv3a(8) DPWR DGND + 1QQ 2QQ 3QQ 4QQ 5QQ 6QQ 7QQ 8QQ + OC + 1QBAR 2QBAR 3QBAR 4QBAR 5QBAR 6QBAR 7QBAR 8QBAR + D_F534_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F534_1 ueff ( + twclklmn=6ns twclkhmn=7ns + tsudclkmn=2ns thdclkmn=2ns + ) .model D_F534_2 utgate ( + tplhmn=3.2ns tplhmx=10ns + tphlmn=3.2ns tphlmx=10ns + tplhty=6.1ns tphlty=6.1ns + tpzhmn=1.2ns tpzhmx=12.5ns + tpzlmn=1.2ns tpzlmx=8.5ns + tpzhty=8.6ns tpzlty=5.4ns + tphzmn=1.2ns tphzmx=8ns + tplzmn=1.2ns tplzmx=6.5ns + tphzty=4.9ns tplzty=3.9ns + ) *$ *------------------------------------------------------------------------- * 74F537 DECODER 1 OF 10 WITH 3-STATE OUTPUTS * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 7-29-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F537 OEBAR_I E0BAR_I E1_I P_I A0_I A1_I A2_I A3_I + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O Q8_O Q9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF537LOG LOGICEXP (8,18) DPWR DGND + OEBAR_I E0BAR_I E1_I P_I A0_I A1_I A2_I A3_I + OEBAR E0BAR E1 P A0 A1 A2 A3 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + OEBAR = { OEBAR_I } + E0BAR = { E0BAR_I } + E1 = { E1_I } + P = { P_I } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + PBAR = { ~P } + A0BAR = { ~A0 } + A1BAR = { ~A1 } + A2BAR = { ~A2 } + A3BAR = { ~A3 } + ENABLEIN = { ~E0BAR & E1 } + + Q0 = { ~(ENABLEIN & A3BAR & A2BAR & A1BAR & A0BAR) ^ PBAR } + Q1 = { ~(ENABLEIN & A3BAR & A2BAR & A1BAR & A0 ) ^ PBAR } + Q2 = { ~(ENABLEIN & A3BAR & A2BAR & A1 & A0BAR) ^ PBAR } + Q3 = { ~(ENABLEIN & A3BAR & A2BAR & A1 & A0 ) ^ PBAR } + Q4 = { ~(ENABLEIN & A3BAR & A2 & A1BAR & A0BAR) ^ PBAR } + Q5 = { ~(ENABLEIN & A3BAR & A2 & A1BAR & A0 ) ^ PBAR } + Q6 = { ~(ENABLEIN & A3BAR & A2 & A1 & A0BAR) ^ PBAR } + Q7 = { ~(ENABLEIN & A3BAR & A2 & A1 & A0 ) ^ PBAR } + Q8 = { ~(ENABLEIN & A3 & A2BAR & A1BAR & A0BAR) ^ PBAR } + Q9 = { ~(ENABLEIN & A3 & A2BAR & A1BAR & A0 ) ^ PBAR } * UF537DLY PINDLY (10,1,7) DPWR DGND + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 + OEBAR + E0BAR E1 P A0 A1 A2 A3 + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O Q8_O Q9_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE0 = { CHANGED(E0BAR,0) } + ABLE1 = { CHANGED(E1 ,0) } + POLAR = { CHANGED(P,0) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) | + CHANGED(A2,0) | CHANGED(A3,0) } + + TRISTATE: + ENABLE LO OEBAR + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O Q8_O Q9_O = { + CASE ( + TRN_ZH, DELAY(2.5NS, 4.5NS, 8.0NS), + TRN_ZL, DELAY(4.0NS, 5.5NS, 9.0NS), + TRN_HZ, DELAY(1.0NS, 3.0NS, 7.0NS), + TRN_LZ, DELAY(2.0NS, 4.0NS, 7.0NS), + POLAR & TRN_HL, DELAY(3.5NS, 6.5NS,11.0NS), + ADDR & TRN_HL, DELAY(3.0NS, 7.5NS,12.0NS), + ABLE0 & TRN_HL, DELAY(3.0NS, 8.0NS,12.0NS), + ABLE1 & TRN_HL, DELAY(4.0NS, 8.5NS,12.5NS), + ABLE0 & TRN_LH, DELAY(4.0NS, 8.0NS,12.0NS), + ABLE1 & TRN_LH, DELAY(6.0NS, 8.5NS,13.0NS), + ADDR & TRN_LH, DELAY(4.5NS, 9.0NS,16.0NS), + POLAR & TRN_LH, DELAY(5.0NS,12.5NS,17.0NS), + DELAY(5.0NS,12.5NS,17.0NS) + ) + } * .ENDS * *$ *--------- * 74F538 DECODER 1 OF 8 WITH 3-STATE OUTPUTS * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 7-28-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE: THE PUBLISHED LOGIC DIAGRAM IS WRONG. THE INPUT BUFFER FOR * POLARITY CONTROL(P) SHOULD BE AN INPUT INVERTER * .SUBCKT 74F538 OE0BAR_I OE1BAR_I E0BAR_I E1BAR_I E2_I E3_I P_I + A0_I A1_I A2_I + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF538LOG LOGICEXP (10,15) DPWR DGND + OE0BAR_I OE1BAR_I E0BAR_I E1BAR_I E2_I E3_I P_I A0_I A1_I A2_I + ENABLEOUT ABLELO ABLEHI P A0 A1 A2 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + OE0BAR = { OE0BAR_I } + OE1BAR = { OE1BAR_I } + E0BAR = { E0BAR_I } + E1BAR = { E1BAR_I } + E2 = { E2_I } + E3 = { E3_I } + P = { P_I } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + ABLELO = { ~E0BAR & ~E1BAR } + ABLEHI = { E2 & E3 } + PBAR = { ~P } + A0BAR = { ~A0 } + A1BAR = { ~A1 } + A2BAR = { ~A2 } + ENABLEIN = { ABLELO & ABLEHI } + + ENABLEOUT = { ~(OE0BAR | OE1BAR) } + Q0 = { ~(ENABLEIN & A2BAR & A1BAR & A0BAR) ^ PBAR } + Q1 = { ~(ENABLEIN & A2BAR & A1BAR & A0 ) ^ PBAR } + Q2 = { ~(ENABLEIN & A2BAR & A1 & A0BAR) ^ PBAR } + Q3 = { ~(ENABLEIN & A2BAR & A1 & A0 ) ^ PBAR } + Q4 = { ~(ENABLEIN & A2 & A1BAR & A0BAR) ^ PBAR } + Q5 = { ~(ENABLEIN & A2 & A1BAR & A0 ) ^ PBAR } + Q6 = { ~(ENABLEIN & A2 & A1 & A0BAR) ^ PBAR } + Q7 = { ~(ENABLEIN & A2 & A1 & A0 ) ^ PBAR } * UF538DLY PINDLY (8,1,7) DPWR DGND + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + ENABLEOUT + ABLELO ABLEHI P A0 A1 A2 ENABLEOUT + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE01 = { CHANGED(ABLELO,0) } + ABLE23 = { CHANGED(ABLEHI,0) } + POLAR = { CHANGED(P,0) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) } + + TRISTATE: + ENABLE HI ENABLEOUT + Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O = { + CASE ( + TRN_ZH, DELAY(2.0NS, 5.5NS,11.0NS), + TRN_ZL, DELAY(6.0NS, 9.5NS,15.0NS), + TRN_HZ, DELAY(1.0NS, 3.0NS, 7.0NS), + TRN_LZ, DELAY(1.0NS, 3.5NS, 9.5NS), + POLAR & TRN_HL, DELAY(3.5NS, 6.5NS,10.5NS), + ABLE01 & TRN_HL, DELAY(3.0NS, 7.5NS,12.5NS), + ABLE23 & TRN_HL, DELAY(3.5NS, 7.0NS,13.0NS), + ADDR & TRN_HL, DELAY(3.0NS, 7.5NS,13.5NS), + ABLE01 & TRN_LH, DELAY(5.0NS, 8.5NS,13.0NS), + ABLE23 & TRN_LH, DELAY(5.5NS, 9.0NS,13.5NS), + ADDR & TRN_LH, DELAY(5.0NS, 8.5NS,14.0NS), + POLAR & TRN_LH, DELAY(4.0NS, 9.5NS,16.5NS), + DELAY(4.0NS, 9.5NS,16.5NS) + ) + } * .ENDS * *$ *--------- * 74F539 DECODER 1 OF 4 WITH 3-STATE OUTPUTS * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 7-29-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F539 OEBAR_I EBAR_I P_I A0_I A1_I Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF539LOG LOGICEXP (5,9) DPWR DGND + OEBAR_I EBAR_I P_I A0_I A1_I + OEBAR EBAR P A0 A1 + Q0 Q1 Q2 Q3 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + OEBAR = { OEBAR_I } + EBAR = { EBAR_I } + P = { P_I } + A0 = { A0_I } + A1 = { A1_I } + PBAR = { ~P } + A0BAR = { ~A0 } + A1BAR = { ~A1 } + ABLEIN = { ~EBAR } + + Q0 = { ~(ABLEIN & A1BAR & A0BAR) ^ PBAR } + Q1 = { ~(ABLEIN & A1BAR & A0 ) ^ PBAR } + Q2 = { ~(ABLEIN & A1 & A0BAR) ^ PBAR } + Q3 = { ~(ABLEIN & A1 & A0 ) ^ PBAR } * UF539DLY PINDLY (4,1,4) DPWR DGND + Q0 Q1 Q2 Q3 + OEBAR + EBAR P A0 A1 + Q0_O Q1_O Q2_O Q3_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(EBAR,0) } + LHPOLAR = { CHANGED_LH(P,0) } + HLPOLAR = { CHANGED_HL(P,0) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) } + + TRISTATE: + ENABLE LO OEBAR + Q0_O Q1_O Q2_O Q3_O = { + CASE ( + TRN_ZH, DELAY(2.0NS, 4.0NS, 8.5NS), + TRN_ZL, DELAY(5.0NS, 7.0NS,11.5NS), + TRN_HZ, DELAY(1.0NS, 3.0NS, 6.5NS), + TRN_LZ, DELAY(1.5NS, 4.0NS, 8.5NS), + HLPOLAR & TRN_HL, DELAY(3.0NS, 5.5NS, 9.5NS), + LHPOLAR & TRN_HL, DELAY(4.0NS, 6.0NS, 9.5NS), + LHPOLAR & TRN_LH, DELAY(3.5NS, 6.5NS,10.5NS), + ABLE & TRN_HL, DELAY(3.0NS, 7.0NS,11.5NS), + ABLE & TRN_LH, DELAY(4.5NS, 7.5NS,12.0NS), + ADDR & TRN_HL, DELAY(3.0NS, 8.0NS,13.0NS), + ADDR & TRN_LH, DELAY(4.0NS, 8.5NS,13.5NS), + HLPOLAR & TRN_LH, DELAY(5.0NS,11.5NS,15.5NS), + DELAY(5.0NS,11.5NS,15.5NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74F543 OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS * * FAST LOGIC DATA BOOK, 1989, SIGNETICS * KN 9-3-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F543 GABBAR_I GBABAR_I CEABBAR_I CEBABAR_I LEABBAR_I LEBABAR_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF543LOG LOGICEXP(22,26) DPWR DGND + GABBAR_I GBABAR_I CEABBAR_I CEBABAR_I LEABBAR_I LEBABAR_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + GABBAR GBABAR CEABBAR CEBABAR LEABBAR LEBABAR EN_AB EN_BA CLK_A CLK_B + A0 A1 A2 A3 A4 A5 A6 A7 + B0 B1 B2 B3 B4 B5 B6 B7 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GABBAR = { GABBAR_I } + GBABAR = { GBABAR_I } + CEABBAR = { CEABBAR_I } + CEBABAR = { CEBABAR_I } + LEABBAR = { LEABBAR_I } + LEBABAR = { LEBABAR_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + * OUTPUT ASSIGNMENTS: + EN_BA = { ~GBABAR & ~CEBABAR } + EN_AB = { ~GABBAR & ~CEABBAR } + CLK_B = { ~LEBABAR & ~CEBABAR } + CLK_A = { ~LEABBAR & ~CEABBAR } * U2 DLTCH(8) DPWR DGND $D_HI $D_HI CLK_A + A0 A1 A2 A3 A4 A5 A6 A7 + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_F * U3 DLTCH(8) DPWR DGND $D_HI $D_HI CLK_B + B0 B1 B2 B3 B4 B5 B6 B7 + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_F * UF543DLY PINDLY (16,2,26) DPWR DGND + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + EN_AB EN_BA + GABBAR GBABAR CEABBAR CEBABAR LEABBAR LEBABAR A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 B6 B7 CLK_A CLK_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CHANGE_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + CHANGE_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + + CHANGE_LEABBAR = { CHANGED(LEABBAR,0) & CEABBAR!='1 } + CHANGE_LEBABAR = { CHANGED(LEBABAR,0) & CEBABAR!='1 } + CHANGE_CEABBAR = { CHANGED(CEABBAR,0) } + CHANGE_CEBABAR = { CHANGED(CEBABAR,0) } + CHANGE_GABBAR = { CHANGED(GABBAR,0) } + CHANGE_GBABAR = { CHANGED(GBABAR,0) } + + TRISTATE: + ENABLE HI EN_BA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + CHANGE_CEBABAR & TRN_LZ, DELAY(3.0NS,7.0NS,12.0NS), + CHANGE_CEBABAR & TRN_ZH, DELAY(4.0NS,7.0NS,11.5NS), + CHANGE_CEBABAR & TRN_ZL, DELAY(4.5NS,7.0NS,11.0NS), + CHANGE_CEBABAR & TRN_HZ, DELAY(2.0NS,5.0NS, 9.5NS), + CHANGE_GBABAR & TRN_ZL, DELAY(3.0NS,5.0NS, 9.0NS), + CHANGE_GBABAR & TRN_LZ, DELAY(1.0NS,4.0NS, 8.5NS), + CHANGE_GBABAR & TRN_ZH, DELAY(1.5NS,4.0NS, 8.0NS), + CHANGE_GBABAR & TRN_HZ, DELAY(1.0NS,3.0NS, 7.5NS), + CHANGE_LEBABAR & TRN_LH, DELAY(4.5NS,7.0NS,11.0NS), + CHANGE_LEBABAR & TRN_HL, DELAY(4.0NS,6.0NS, 9.5NS), + CHANGE_B & TRN_HL, DELAY(2.5NS,4.5NS, 8.0NS), + CHANGE_B & TRN_LH, DELAY(2.5NS,4.0NS, 7.5NS), + DELAY(5NS,8NS,13NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE HI EN_AB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + CHANGE_CEABBAR & TRN_LZ, DELAY(3.0NS,7.0NS,12.0NS), + CHANGE_CEABBAR & TRN_ZH, DELAY(4.0NS,7.0NS,11.5NS), + CHANGE_CEABBAR & TRN_ZL, DELAY(4.5NS,7.0NS,11.0NS), + CHANGE_CEABBAR & TRN_HZ, DELAY(2.0NS,5.0NS, 9.5NS), + CHANGE_GABBAR & TRN_ZL, DELAY(3.0NS,5.0NS, 9.0NS), + CHANGE_GABBAR & TRN_LZ, DELAY(1.0NS,4.0NS, 8.5NS), + CHANGE_GABBAR & TRN_ZH, DELAY(1.5NS,4.0NS, 8.0NS), + CHANGE_GABBAR & TRN_HZ, DELAY(1.0NS,3.0NS, 7.5NS), + CHANGE_LEABBAR & TRN_LH, DELAY(5.5NS,8.5NS,12.5NS), + CHANGE_LEABBAR & TRN_HL, DELAY(4.0NS,6.5NS,10.0NS), + CHANGE_A & TRN_LH, DELAY(3.0NS,5.5NS, 9.0NS), + CHANGE_A & TRN_HL, DELAY(2.5NS,5.0NS, 8.5NS), + DELAY(6NS,9NS,13NS) ;DEFAULT + ) + } + BOOLEAN: + CEABBAR_ACTIVE = { CEABBAR!='1 } + CEBABAR_ACTIVE = { CEBABAR!='1 } + LEABBAR_ACTIVE = { LEABBAR!='1 } + LEBABAR_ACTIVE = { LEBABAR!='1 } + + WIDTH: + NODE = CLK_A + MIN_LO = 4.5NS + MESSAGE = "LATCH ENABLE PULSE WIDTH LOW TOO SHORT" + + WIDTH: + NODE = CLK_B + MIN_LO = 4.5NS + MESSAGE = "LATCH ENABLE PULSE WIDTH LOW TOO SHORT" + + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK HL = LEABBAR + SETUPTIME_LO = 3NS + HOLDTIME_LO = 2NS + WHEN = { CEABBAR_ACTIVE } + + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B6 B5 B6 B7 + CLOCK HL = LEBABAR + SETUPTIME_LO = 3NS + HOLDTIME_LO = 2NS + WHEN = { CEBABAR_ACTIVE } + + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK HL = CEABBAR + SETUPTIME_HI = 1.5NS + SETUPTIME_LO = 3NS + HOLDTIME_LO = 2NS + WHEN = { LEABBAR_ACTIVE } + + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B6 B5 B6 B7 + CLOCK HL = CEBABAR + SETUPTIME_HI = 1.5NS + SETUPTIME_LO = 3NS + HOLDTIME_LO = 2NS + WHEN = { LEBABAR_ACTIVE } + * .ENDS * *$ *------------------------------------------------------------------------- * 74F544 TRANSCEIVERS REGISTERED OCTAL WITH 3-STATE OUTPUTS * * F FAST LOGIC DATA BOOK, 1989, PHILIPS SEMICONDUCTORS * KN 9-3-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F544 GABBAR_I GBABAR_I CEABBAR_I CEBABAR_I LEABBAR_I LEBABAR_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF544LOG LOGICEXP(22,26) DPWR DGND + GABBAR_I GBABAR_I CEABBAR_I CEBABAR_I LEABBAR_I LEBABAR_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + GABBAR GBABAR CEABBAR CEBABAR LEABBAR LEBABAR EN_AB EN_BA CLK_A CLK_B + A0 A1 A2 A3 A4 A5 A6 A7 + B0 B1 B2 B3 B4 B5 B6 B7 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GABBAR = { GABBAR_I } + GBABAR = { GBABAR_I } + CEABBAR = { CEABBAR_I } + CEBABAR = { CEBABAR_I } + LEABBAR = { LEABBAR_I } + LEBABAR = { LEBABAR_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + * OUTPUT ASSIGNMENTS: + EN_BA = { ~GBABAR & ~CEBABAR } + EN_AB = { ~GABBAR & ~CEABBAR } + CLK_B = { ~LEBABAR & ~CEBABAR } + CLK_A = { ~LEABBAR & ~CEABBAR } * U2 DLTCH(8) DPWR DGND $D_HI $D_HI CLK_A + A0 A1 A2 A3 A4 A5 A6 A7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + D0_GFF IO_F * U3 DLTCH(8) DPWR DGND $D_HI $D_HI CLK_B + B0 B1 B2 B3 B4 B5 B6 B7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + D0_GFF IO_F * UF544DLY PINDLY (16,2,26) DPWR DGND + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + EN_AB EN_BA + GABBAR GBABAR CEABBAR CEBABAR LEABBAR LEBABAR A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 B6 B7 CLK_A CLK_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CHANGE_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + CHANGE_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + + CHANGE_LEABBAR = { CHANGED(LEABBAR,0) & CEABBAR!='1 } + CHANGE_LEBABAR = { CHANGED(LEBABAR,0) & CEBABAR!='1 } + CHANGE_CEABBAR = { CHANGED(CEABBAR,0) } + CHANGE_CEBABAR = { CHANGED(CEBABAR,0) } + CHANGE_GABBAR = { CHANGED(GABBAR,0) } + CHANGE_GBABAR = { CHANGED(GBABAR,0) } + + TRISTATE: + ENABLE HI EN_BA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + CHANGE_CEBABAR & TRN_ZL, DELAY(4.5NS,8.0NS,12.0NS), + CHANGE_CEBABAR & TRN_LZ, DELAY(4.0NS,8.5NS,11.5NS), + CHANGE_CEBABAR & TRN_ZH, DELAY(3.5NS,7.0NS,10.0NS), + CHANGE_GBABAR & TRN_ZL, DELAY(3.0NS,5.5NS, 9.0NS), + CHANGE_CEBABAR & TRN_HZ, DELAY(2.5NS,5.0NS, 9.0NS), + CHANGE_GBABAR & TRN_ZH, DELAY(1.5NS,4.0NS, 7.5NS), + CHANGE_GBABAR & TRN_LZ, DELAY(1.5NS,4.0NS, 7.5NS), + CHANGE_GBABAR & TRN_HZ, DELAY(1.0NS,4.0NS, 7.0NS), + CHANGE_LEBABAR, DELAY(4.0NS,7.0NS,10.5NS), + CHANGE_B & TRN_LH, DELAY(3.0NS,6.5NS,10.5NS), + CHANGE_B & TRN_HL, DELAY(3.0NS,5.0NS, 8.5NS), + DELAY(5NS,9NS,13NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE HI EN_AB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + CHANGE_CEABBAR & TRN_ZL, DELAY(4.5NS,8.0NS,12.0NS), + CHANGE_CEABBAR & TRN_LZ, DELAY(4.0NS,8.5NS,11.5NS), + CHANGE_CEABBAR & TRN_ZH, DELAY(3.5NS,7.0NS,10.0NS), + CHANGE_GABBAR & TRN_ZL, DELAY(3.0NS,5.5NS, 9.0NS), + CHANGE_CEABBAR & TRN_HZ, DELAY(2.5NS,5.0NS, 9.0NS), + CHANGE_GABBAR & TRN_ZH, DELAY(1.5NS,4.0NS, 7.5NS), + CHANGE_GABBAR & TRN_LZ, DELAY(1.5NS,4.0NS, 7.5NS), + CHANGE_GABBAR & TRN_HZ, DELAY(1.0NS,4.0NS, 7.0NS), + CHANGE_LEABBAR & TRN_LH, DELAY(4.0NS,8.0NS,12.5NS), + CHANGE_A & TRN_LH, DELAY(3.0NS,6.5NS,10.5NS), + CHANGE_LEABBAR & TRN_HL, DELAY(4.0NS,7.5NS,10.5NS), + CHANGE_A & TRN_HL, DELAY(3.0NS,5.0NS, 8.5NS), + DELAY(5NS,9NS,13NS) ;DEFAULT + ) + } + BOOLEAN: + CEABBAR_ACTIVE = { CEABBAR!='1 } + CEBABAR_ACTIVE = { CEBABAR!='1 } + LEABBAR_ACTIVE = { LEABBAR!='1 } + LEBABAR_ACTIVE = { LEBABAR!='1 } + + WIDTH: + NODE = CLK_A + MIN_LO = 4.5NS + MESSAGE = "LATCH ENABLE PULSE WIDTH LOW TOO SHORT" + + WIDTH: + NODE = CLK_B + MIN_LO = 4.5NS + MESSAGE = "LATCH ENABLE PULSE WIDTH LOW TOO SHORT" + + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK HL = LEABBAR + SETUPTIME_LO = 2.5NS + SETUPTIME_HI = 2NS + HOLDTIME = 2.5NS + WHEN = { CEABBAR_ACTIVE } + + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B6 B5 B6 B7 + CLOCK HL = LEBABAR + SETUPTIME_LO = 2.5NS + SETUPTIME_HI = 2NS + HOLDTIME = 2.5NS + WHEN = { CEBABAR_ACTIVE } + + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK HL = CEABBAR + SETUPTIME = 2.5NS + HOLDTIME = 2NS + WHEN = { LEABBAR_ACTIVE } + + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B6 B5 B6 B7 + CLOCK HL = CEBABAR + SETUPTIME = 2.5NS + HOLDTIME = 2NS + WHEN = { LEBABAR_ACTIVE } + * .ENDS * *$ *------------------------------------------------------------------------- * 74F545 Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs * * The Fast Data Book, 1982, FAIRCHILD * atl 8/31/89 Update interface and model names * .subckt 74F545 OEBAR T/RBAR A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(2) DPWR DGND + OEBAR GAB OE GABB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UG anda(2,2) DPWR DGND + OE GABB OE T/RBAR GBA GAB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} UA buf3a(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 + GBA + A0 A1 A2 A3 A4 A5 A6 A7 + D_F545_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB buf3a(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 + GAB + B0 B1 B2 B3 B4 B5 B6 B7 + D_F545_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F545_1 utgate ( + tplhmn=3.5ns tplhty=6.5ns + tplhmx=9.1ns tphlmn=3.5ns + tphlty=6.5ns tphlmx=9.1ns + tpzhmn=4ns tpzhty=7ns + tpzhmx=10ns tpzlmn=5.5ns + tpzlty=8.5ns tpzlmx=14ns + tphzmn=5.5ns tphzty=8.5ns + tphzmx=14ns tplzmn=4ns + tplzty=7ns tplzmx=10ns + ) * *$ *------------------------------------------------------------------------- * 74F547 DEMULTIPLEXER/DECODER OCTAL WITH ADDRESS LATCHES AND ACKNOWLEDGE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * TC 08/24/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74F547 LE_I E0BAR_I E1_I E2_I RDBAR_I WRBAR_I A0_I A1_I A2_I ACKBAR_O + Q0BAR_O Q1BAR_O Q2BAR_O Q3BAR_O Q4BAR_O Q5BAR_O Q6BAR_O Q7BAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DLTCH(3) DPWR DGND $D_HI $D_HI LE + A0 A1 A2 IQ0 IQ1 IQ2 IQ0BAR IQ1BAR IQ2BAR + D0_GFF IO_F IO_LEVEL={IO_LEVEL} * UF547LOG LOGICEXP(15,18) DPWR DGND + LE_I E0BAR_I E1_I E2_I RDBAR_I WRBAR_I A0_I A1_I A2_I + IQ0 IQ0BAR IQ1 IQ1BAR IQ2 IQ2BAR + LE E0BAR E1 E2 RDBAR WRBAR A0 A1 A2 ACKBAR + Q0BAR Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR Q6BAR Q7BAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + LE = { LE_I } + E0BAR = { E0BAR_I } + E1 = { E1_I } + E2 = { E2_I } + RDBAR = { RDBAR_I } + WRBAR = { WRBAR_I } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + IEN = { ~(E0BAR | ~(E1 & E2)) } + ACKBAR = { ~(~(RDBAR & WRBAR) & IEN) } + Q0BAR = { ~(IEN & IQ2BAR & IQ1BAR & IQ0BAR) } + Q1BAR = { ~(IEN & IQ2BAR & IQ1BAR & IQ0) } + Q2BAR = { ~(IEN & IQ2BAR & IQ1 & IQ0BAR) } + Q3BAR = { ~(IEN & IQ2BAR & IQ1 & IQ0) } + Q4BAR = { ~(IEN & IQ2 & IQ1BAR & IQ0BAR) } + Q5BAR = { ~(IEN & IQ2 & IQ1BAR & IQ0) } + Q6BAR = { ~(IEN & IQ2 & IQ1 & IQ0BAR) } + Q7BAR = { ~(IEN & IQ2 & IQ1 & IQ0) } * UF547DLY PINDLY (9,0,9) DPWR DGND + Q0BAR Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR Q6BAR Q7BAR ACKBAR + A0 A1 A2 E0BAR E1 E2 LE RDBAR WRBAR + Q0BAR_O Q1BAR_O Q2BAR_O Q3BAR_O Q4BAR_O Q5BAR_O Q6BAR_O Q7BAR_O ACKBAR_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) } + LATCH = { CHANGED(LE,0) } + ENABLE12 = { CHANGED(E1,0) | CHANGED(E2,0) } + ENABLE0 = { CHANGED(E0BAR,0) } + ROW = { CHANGED(RDBAR,0) | CHANGED(WRBAR,0) } + PINDLY: + Q0BAR_O Q1BAR_O Q2BAR_O Q3BAR_O Q4BAR_O Q5BAR_O Q6BAR_O Q7BAR_O = { + CASE( + LATCH & TRN_HL, DELAY(5NS,10.5NS,15NS), + ADDR & TRN_HL, DELAY(4NS,7NS,13NS), + LATCH & TRN_LH, DELAY(3NS,6NS,11NS), + ENABLE12 & TRN_LH, DELAY(3NS,6NS,11NS), + ENABLE12 & TRN_HL, DELAY(4NS,6NS,11NS), + ADDR & TRN_LH, DELAY(1.5NS,4.5NS,10NS), + ENABLE0 & TRN_LH, DELAY(2NS,4.5NS,9.5NS), + ENABLE0 & TRN_HL, DELAY(3NS,5.5NS,9.5NS), + DELAY(6NS,11NS,16NS) + ) + } + ACKBAR_O = { + CASE( + ENABLE12 & TRN_LH, DELAY(7NS,11NS,15NS), + (ENABLE0 | ROW) & TRN_LH, DELAY(6.5NS,9NS,14NS), + ENABLE12 & TRN_HL, DELAY(4NS,6.5NS,11NS), + (ENABLE0 | ROW) & TRN_HL, DELAY(3NS,5.5NS,10.5NS), + DELAY(8NS,12NS,16NS) + ) + } + WIDTH: + NODE = LE + MIN_HI = 6NS + SETUP_HOLD: + DATA(3) = A0 A1 A2 + CLOCK LH = LE + SETUPTIME = 5NS + HOLDTIME = 6NS * .ENDS * *$ *------------------------------------------------------------------------- * 74F548 DECODER/DEMULTIPLEXER OCTAL WITH ACKNOWLEDGE * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 8-24-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74F548 E0BAR_I E1BAR_I E2_I E3_I RDBAR_I WRBAR_I A0_I A1_I A2_I + ACKBAR_O Q0BAR_O Q1BAR_O Q2BAR_O Q3BAR_O Q4BAR_O Q5BAR_O Q6BAR_O Q7BAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UF548LOG LOGICEXP (9,16) DPWR DGND + E0BAR_I E1BAR_I E2_I E3_I RDBAR_I WRBAR_I A0_I A1_I A2_I + ENABLE01 ENABLE23 READWR A0 A1 A2 ENABLE + ACKBAR Q0BAR Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR Q6BAR Q7BAR + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + E0BAR = { E0BAR_I } + E1BAR = { E1BAR_I } + E2 = { E2_I } + E3 = { E3_I } + RDBAR = { RDBAR_I } + WRBAR = { WRBAR_I } + A0 = { A0_I } + A1 = { A1_I } + A2 = { A2_I } + + A0BAR = { ~A0 } + A1BAR = { ~A1 } + A2BAR = { ~A2 } + ENABLE01 = { ~E0BAR & ~E1BAR } + ENABLE23 = { E2 & E3 } + ENABLE = { ENABLE01 & ENABLE23 } + Q0BAR = { ~(ENABLE & A2BAR & A1BAR & A0BAR) } + Q1BAR = { ~(ENABLE & A2BAR & A1BAR & A0 ) } + Q2BAR = { ~(ENABLE & A2BAR & A1 & A0BAR) } + Q3BAR = { ~(ENABLE & A2BAR & A1 & A0 ) } + Q4BAR = { ~(ENABLE & A2 & A1BAR & A0BAR) } + Q5BAR = { ~(ENABLE & A2 & A1BAR & A0 ) } + Q6BAR = { ~(ENABLE & A2 & A1 & A0BAR) } + Q7BAR = { ~(ENABLE & A2 & A1 & A0 ) } + READWR = { WRBAR & RDBAR } + ACKBAR = { ~(ENABLE & ~READWR) } UF548DLY PINDLY (8,0,6) DPWR DGND + Q0BAR Q1BAR Q2BAR Q3BAR Q4BAR Q5BAR Q6BAR Q7BAR + ENABLE ENABLE01 ENABLE23 A0 A1 A2 + Q0BAR_O Q1BAR_O Q2BAR_O Q3BAR_O Q4BAR_O Q5BAR_O Q6BAR_O Q7BAR_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE01 = { CHANGED(ENABLE,0) & CHANGED(ENABLE01,0) } + ABLE23 = { CHANGED(ENABLE,0) & CHANGED(ENABLE23,0) } + ADDR = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) } + + PINDLY: + Q0BAR_O Q1BAR_O Q2BAR_O Q3BAR_O Q4BAR_O Q5BAR_O Q6BAR_O Q7BAR_O = { + CASE ( + ABLE23 & TRN_HL, DELAY(3.5NS,6.0NS,10.5NS), + ABLE23 & TRN_LH, DELAY(3.0NS,6.0NS,10.5NS), + ADDR & TRN_HL, DELAY(4.0NS,6.5NS,10.0NS), + ABLE01 & TRN_HL, DELAY(3.0NS,5.5NS, 9.5NS), + ABLE01 & TRN_LH, DELAY(2.0NS,4.5NS, 9.5NS), + ADDR & TRN_LH, DELAY(1.5NS,4.5NS, 9.0NS), + DELAY(3.5NS,6.0NS,10.5NS) + ) + } UF548DLY_OC PINDLY (1,0,4) DPWR DGND + ACKBAR + ENABLE ENABLE01 ENABLE23 READWR + ACKBAR_O + IO_F_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE01 = { CHANGED(ENABLE,0) & CHANGED(ENABLE01,0) } + ABLE23 = { CHANGED(ENABLE,0) & CHANGED(ENABLE23,0) } + RDWR = { CHANGED(READWR,0) } + + PINDLY: + ACKBAR_O = { + CASE ( + ABLE23 & TRN_LH, DELAY(8.0NS,11.0NS,15.0NS), + ABLE01 & TRN_LH, DELAY(6.5NS, 9.5NS,13.0NS), + RDWR & TRN_LH, DELAY(5.5NS, 9.0NS,12.5NS), + ABLE23 & TRN_HL, DELAY(4.0NS, 7.0NS,11.5NS), + ABLE01 & TRN_HL, DELAY(3.0NS, 6.0NS,10.5NS), + RDWR & TRN_HL, DELAY(2.5NS, 5.0NS, 8.5NS), + DELAY(8.0NS,11.0NS,15.0NS) + ) + } .ENDS *$ *------------------------------------------------------------------------- * 74F550 TRANSCEIVERS REGISTERED OCTAL WITH STATUS FLAG * * FAST DATA MANUAL, 1987, PHILIPS SEMICONDUCTORS * KN 9-3-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F550 OEABAR_I OEBBAR_I CPA_I CPB_I CEABAR_I CEBBAR_I CFAB_I CFBA_I + FAB_O FBA_O A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF550LOG LOGICEXP(28,32) DPWR DGND + OEABAR_I OEBBAR_I CPA_I CPB_I CEABAR_I CEBBAR_I CFAB_I CFBA_I FAB FBA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B CFABBAR CFBABAR + OEABAR OEBBAR CLKA CLKB CEABAR CEBBAR CFAB CFBA + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + CEA CEB DAB DBA CLRF_AB CLRF_BA CPA CPB + + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + OEABAR = { OEABAR_I } + OEBBAR = { OEBBAR_I } + CEABAR = { CEABAR_I } + CEBBAR = { CEBBAR_I } + CPA = { CPA_I } + CLKA = { CPA & ~CEABAR } + CPB = { CPB_I } + CLKB = { CPB & ~CEBBAR } + CFAB = { CFAB_I } + CFBA = { CFBA_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + * OUTPUT ASSIGNMENTS: + CEB = { ~CEBBAR } + CEA = { ~CEABAR } + DBA = { CEB | (FBA & CEBBAR) } + DAB = { CEA | (FAB & CEABAR) } + CLRF_AB = { ~(CFAB & CFABBAR) } + CLRF_BA = { ~(CFBA & CFBABAR) } * UINV INVA(2) DPWR DGND + CFAB CFBA CFABBAR CFBABAR + D_INV550 IO_F MNTYMXDLY={MNTYMXDLY} * UAB DFF(1) DPWR DGND $D_HI CLRF_AB CPA + DAB FAB QABBAR + D0_EFF IO_F * UBA DFF(1) DPWR DGND $D_HI CLRF_BA CPB + DBA FBA QBABAR + D0_EFF IO_F * U2 DFF(8) DPWR DGND $D_HI $D_HI CLKA ; CEABAR + CPA = CLKA + A0 A1 A2 A3 A4 A5 A6 A7 + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * U3 DFF(8) DPWR DGND $D_HI $D_HI CLKB ; CEBBAR + CPB = CLKB + B0 B1 B2 B3 B4 B5 B6 B7 + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * UF550DLY PINDLY (18,2,22) DPWR DGND + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 FAB FBA + OEABAR OEBBAR + CPA CPB CFAB CFBA CEABAR CEBBAR A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B FAB_O FBA_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_A = { CHANGED_LH(CPA,0) } + CLOCK_B = { CHANGED_LH(CPB,0) } + EN_CLK_A = { CLOCK_A & CEABAR!='1 } + EN_CLK_B = { CLOCK_B & CEBBAR!='1 } + CHANGE_CFAB = { CHANGED(CFAB,0) } + CHANGE_CFBA = { CHANGED(CFBA,0) } + + PINDLY: + FAB_O = { + CASE( + CLOCK_A & TRN_LH, DELAY(3.0NS,6.0NS,9.0NS), + CHANGE_CFAB & TRN_HL, DELAY(4.5NS,9.0NS,13.0NS), + DELAY(5.5NS,10.0NS,14.0NS) ;DEFAULT + ) + } + FBA_O = { + CASE( + CLOCK_B & TRN_LH, DELAY(3.0NS,6.0NS,9.0NS), + CHANGE_CFBA & TRN_HL, DELAY(4.5NS,9.0NS,13.0NS), + DELAY(5.5NS,10.0NS,14.0NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OEABAR + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + TRN_ZH, DELAY(2.0NS,5.5NS, 8.5NS), + TRN_ZL, DELAY(3.0NS,7.0NS,10.5NS), + TRN_HZ, DELAY(2.5NS,6.5NS,10.0NS), + TRN_LZ, DELAY(2.0NS,5.5NS, 8.5NS), + EN_CLK_B & TRN_LH, DELAY(2.5NS,5.5NS, 8.5NS), + EN_CLK_B & TRN_HL, DELAY(3.5NS,7.0NS,10.0NS), + DELAY(4NS,8NS,11NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OEBBAR + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + TRN_ZH, DELAY(2.0NS,5.5NS, 8.5NS), + TRN_ZL, DELAY(3.0NS,7.0NS,10.5NS), + TRN_HZ, DELAY(2.5NS,6.5NS,10.0NS), + TRN_LZ, DELAY(2.0NS,5.5NS, 8.5NS), + EN_CLK_A & TRN_LH, DELAY(2.5NS,5.5NS, 8.5NS), + EN_CLK_A & TRN_HL, DELAY(3.5NS,7.0NS,10.0NS), + DELAY(4NS,8NS,11NS) ;DEFAULT + ) + } + + BOOLEAN: + EN_CLKA = { CEABAR!='1 } + EN_CLKB = { CEBBAR!='1 } + + FREQ: + NODE = CPA + MAXFREQ = 50MEG + + WIDTH: + NODE = CPA + MIN_HI = 3.5NS + MIN_LO = 3.5NS + WHEN = { EN_CLKA } + + FREQ: + NODE = CPB + MAXFREQ = 50MEG + + WIDTH: + NODE = CPB + MIN_HI = 3.5NS + MIN_LO = 3.5NS + WHEN = { EN_CLKB } + + WIDTH: + NODE = CFAB + MIN_HI = 3.5NS + + WIDTH: + NODE = CFBA + MIN_HI = 3.5NS + + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPA + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B6 B5 B6 B7 + CLOCK LH = CPB + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(1) = CEABAR + CLOCK LH = CPA + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(1) = CEBBAR + CLOCK LH = CPB + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(1) = CFAB + CLOCK LH = CPA + RELEASETIME_HL = 10NS + + SETUP_HOLD: + DATA(1) = CFBA + CLOCK LH = CPB + RELEASETIME_HL = 10NS + * .ENDS * .MODEL D_INV550 UGATE ( + TPLHMN=5NS TPLHMX=5NS + TPHLMN=5NS TPHLMX=5NS + ) * *$ *------------------------------------------------------------------------- * 74F551 TRANSCEIVERS REGISTERED OCTAL WITH 3-STATE OUTPUTS * * FAST DATA MANUAL, 1987, SIGNETICS * KN 9-3-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F551 OEABAR_I OEBBAR_I CPA_I CPB_I CEABAR_I CEBBAR_I CFAB_I CFBA_I + FAB_O FBA_O A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF551LOG LOGICEXP(28,32) DPWR DGND + OEABAR_I OEBBAR_I CPA_I CPB_I CEABAR_I CEBBAR_I CFAB_I CFBA_I FAB FBA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B CFABBAR CFBABAR + OEABAR OEBBAR CLKA CLKB CEABAR CEBBAR CFAB CFBA + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + CEA CEB DAB DBA CLRF_AB CLRF_BA CPA CPB + + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + OEABAR = { OEABAR_I } + OEBBAR = { OEBBAR_I } + CEABAR = { CEABAR_I } + CEBBAR = { CEBBAR_I } + CPA = { CPA_I } + CLKA = { CPA & ~CEABAR } + CPB = { CPB_I } + CLKB = { CPB & ~CEBBAR } + CFAB = { CFAB_I } + CFBA = { CFBA_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + * OUTPUT ASSIGNMENTS: + CEB = { ~CEBBAR } + CEA = { ~CEABAR } + DBA = { CEB | (FBA & CEBBAR) } + DAB = { CEA | (FAB & CEABAR) } + CLRF_AB = { ~(CFAB & CFABBAR) } + CLRF_BA = { ~(CFBA & CFBABAR) } * UINV INVA(2) DPWR DGND + CFAB CFBA CFABBAR CFBABAR + D_INV551 IO_F MNTYMXDLY={MNTYMXDLY} * UAB DFF(1) DPWR DGND $D_HI CLRF_AB CPA + DAB FAB QABBAR + D0_EFF IO_F * UBA DFF(1) DPWR DGND $D_HI CLRF_BA CPB + DBA FBA QBABAR + D0_EFF IO_F * U2 DFF(8) DPWR DGND $D_HI $D_HI CLKA ; CEABAR + CPA = CLKA + A0 A1 A2 A3 A4 A5 A6 A7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + D0_EFF IO_F * U3 DFF(8) DPWR DGND $D_HI $D_HI CLKB ; CEBBAR + CPB = CLKB + B0 B1 B2 B3 B4 B5 B6 B7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + D0_EFF IO_F * UF551DLY PINDLY (18,2,22) DPWR DGND + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 FAB FBA + OEABAR OEBBAR + CPA CPB CFAB CFBA CEABAR CEBBAR A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B FAB_O FBA_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_A = { CHANGED_LH(CPA,0) } + CLOCK_B = { CHANGED_LH(CPB,0) } + EN_CLK_A = { CLOCK_A & CEABAR!='1 } + EN_CLK_B = { CLOCK_B & CEBBAR!='1 } + CHANGE_CFAB = { CHANGED(CFAB,0) } + CHANGE_CFBA = { CHANGED(CFBA,0) } + + PINDLY: + FAB_O = { + CASE( + CLOCK_A & TRN_LH, DELAY(3.0NS,6.0NS,9.0NS), + CHANGE_CFAB & TRN_HL, DELAY(4.5NS,9.0NS,13.0NS), + DELAY(5.5NS,10.0NS,14.0NS) ;DEFAULT + ) + } + FBA_O = { + CASE( + CLOCK_B & TRN_LH, DELAY(3.0NS,6.0NS,9.0NS), + CHANGE_CFBA & TRN_HL, DELAY(4.5NS,9.0NS,13.0NS), + DELAY(5.5NS,10.0NS,14.0NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OEABAR + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + TRN_ZH, DELAY(2.0NS,5.5NS, 8.5NS), + TRN_ZL, DELAY(3.0NS,7.0NS,10.5NS), + TRN_HZ, DELAY(2.5NS,6.5NS,10.0NS), + TRN_LZ, DELAY(2.0NS,5.5NS, 8.5NS), + EN_CLK_B & TRN_LH, DELAY(2.5NS,5.5NS, 8.5NS), + EN_CLK_B & TRN_HL, DELAY(3.5NS,7.0NS,10.0NS), + DELAY(4NS,4NS,11NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OEBBAR + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + TRN_ZH, DELAY(2.0NS,5.5NS, 8.5NS), + TRN_ZL, DELAY(3.0NS,7.0NS,10.5NS), + TRN_HZ, DELAY(2.5NS,6.5NS,10.0NS), + TRN_LZ, DELAY(2.0NS,5.5NS, 8.5NS), + EN_CLK_A & TRN_LH, DELAY(2.5NS,5.5NS, 8.5NS), + EN_CLK_A & TRN_HL, DELAY(3.5NS,7.0NS,10.0NS), + DELAY(4NS,8NS,11NS) ;DEFAULT + ) + } + + BOOLEAN: + EN_CLKA = { CEABAR!='1 } + EN_CLKB = { CEBBAR!='1 } + + FREQ: + NODE = CPA + MAXFREQ = 50MEG + + WIDTH: + NODE = CPA + MIN_HI = 3.5NS + MIN_LO = 3.5NS + WHEN = { EN_CLKA } + + FREQ: + NODE = CPB + MAXFREQ = 50MEG + + WIDTH: + NODE = CPB + MIN_HI = 3.5NS + MIN_LO = 3.5NS + WHEN = { EN_CLKB } + + WIDTH: + NODE = CFAB + MIN_HI = 3.5NS + + WIDTH: + NODE = CFBA + MIN_HI = 3.5NS + + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPA + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B6 B5 B6 B7 + CLOCK LH = CPB + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(1) = CEABAR + CLOCK LH = CPA + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(1) = CEBBAR + CLOCK LH = CPB + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + + SETUP_HOLD: + DATA(1) = CFAB + CLOCK LH = CPA + RELEASETIME_HL = 10NS + + SETUP_HOLD: + DATA(1) = CFBA + CLOCK LH = CPB + RELEASETIME_HL = 10NS + * .ENDS * .MODEL D_INV551 UGATE ( + TPLHMN=5NS TPLHMX=5NS + TPHLMN=5NS TPHLMX=5NS + ) * *$ *-------- * 74F563 Octal D-TYPE Transparent Latches with 3-STATE Outputs * * RCA Advanced CMOS Logic IC's 1988 by GE 7/16/90 * .subckt 74F563 OEBAR LE D0 D1 D2 D3 D4 D5 D6 D7 O0BAR O1BAR O2BAR O3BAR O4BAR + O5BAR O6BAR O7BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inv DPWR DGND + OEBAR OE + D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQBUF dltch(8) DPWR DGND + $D_HI $D_HI LE + D0 D1 D2 D3 D4 D5 D6 D7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB + D_F563_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQOUT buf3a(8) DPWR DGND + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB + OE + O0BAR O1BAR O2BAR O3BAR O4BAR O5BAR O6BAR O7BAR + D_F563_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F563_1 ugff ( + twghmn=4ns tsudgmn=2ns + thdgmn=3ns tpgqlhmn=3.5ns + tpgqlhmx=7.5ns tpgqhlmn=2ns + tpgqhlmx=5ns tpdqlhmn=2.5ns + tpdqlhmx=6.5ns tpdqhlmn=1.5ns + tpdqhlmx=4.5ns + ) .model D_F563_2 utgate ( + tplhmn=1ns tplhmx=2ns + tphlmn=1ns tphlmx=2ns + tpzhmn=2ns tpzhmx=7.5ns + tpzlmn=3ns tpzlmx=8.5ns + tphzmn=1.5ns tphzmx=5.5ns + tplzmn=1.5ns tplzmx=5.5ns + ) *$ *--------- * 74F568 Synchronous 4-bit Up/Down Decade Counters with 3-STATE Outputs * * The FAST Data Book, 1990, PHILIPS SEMICONDUCTORS * JSW 7/22/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * NOTICE: The logic diagram for the F device seemed to have an extra * erroneous gate ( note node IB1 in LOGICEXP ) so it was not * connected in the logic expression device for the 74F568. * .SUBCKT 74F568 CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I ACLRBAR_I + SCLRBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O CCOBAR_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF568LOG LOGICEXP(20,19) DPWR DGND + CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I ACLRBAR_I SCLRBAR_I + A_I B_I C_I D_I QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK GBAR U/DBAR ENPBAR ENTBAR LOADBAR ACLRBAR SCLRBAR A B C D + CCOBAR RCOBAR DA DB DC DD EN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + GBAR = { GBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ACLRBAR = { ACLRBAR_I } + SCLRBAR = { SCLRBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UD = { ~U/DBAR } + LOAD = { ~LOADBAR | ~SCLRBAR } + NOTLOAD = { ~LOAD } + EN = { ~ENTBAR & ~ENPBAR & NOTLOAD } + IAX = { ~EN } + IB1 = { UD & QB & QA } + IB2 = { QDBAR & QA & U/DBAR } + IB3 = { QD & QABAR & UD } + IB4 = { QABAR & QC & UD } + IB5 = { QB & QABAR & UD } + IBX = { ~(EN & (IB2 | IB3 | IB4 | IB5)) } + IC1 = { QB & QA & U/DBAR } + IC2 = { QBBAR & QABAR & QD & UD } + IC3 = { QABAR & QBBAR & QC & UD } + ICX = { ~(EN & (IC1 | IC2 | IC3)) } + ID1 = { QA & QD & U/DBAR } + ID2 = { QC & QB & QA & U/DBAR } + ID3 = { QCBAR & QBBAR & QABAR & UD } + ID4 = { QABAR & UD & QD } + IDX = { ~(EN & (ID1 | ID2 | ID3 | ID4)) } + DA = { ~((IAX ^ QA) & NOTLOAD) & ~(~(A & SCLRBAR) & LOAD) } + DB = { ~((IBX ^ QB) & NOTLOAD) & ~(~(B & SCLRBAR) & LOAD) } + DC = { ~((ICX ^ QC) & NOTLOAD) & ~(~(C & SCLRBAR) & LOAD) } + DD = { ~((IDX ^ QD) & NOTLOAD) & ~(~(D & SCLRBAR) & LOAD) } + RCOBAR = { ~((U/DBAR & QA & QBBAR & QCBAR & QD & ~ENTBAR) | + (~ENTBAR & UD & QABAR & QBBAR & QCBAR & QDBAR)) } + CCOBAR = { ~(~CLK & EN & ~RCOBAR) } * UDFF DFF(4) DPWR DGND $D_HI ACLRBAR CLK DA DB DC DD QA QB QC QD + QABAR QBBAR QCBAR QDBAR D0_EFF IO_F * UF568DLY PINDLY (6,1,14) DPWR DGND + CCOBAR RCOBAR QA QB QC QD + GBAR + CLK GBAR ENPBAR ENTBAR ACLRBAR U/DBAR SCLRBAR LOADBAR LOADBAR A B C D EN + CCOBAR_O RCOBAR_O QA_O QB_O QC_O QD_O + IO_F + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + ACLEAR = { CHANGED_HL(ACLRBAR,0) } + CNTENT = { CHANGED(ENTBAR,0) } + CNTENP = { CHANGED(ENPBAR,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + CCOBAR_O = { + CASE( + CHANGED(CLK,0) & TRN_LH, DELAY(2NS,4.5NS,6NS), + CHANGED(CLK,0) & TRN_HL, DELAY(2NS,4NS,7NS), + (CNTENT | CNTENP) & TRN_LH, DELAY(1.5NS,4NS,7.5NS), + CHANGED(LOADBAR,0) & TRN_LH, DELAY(2.5NS,5NS,8.5NS), + CHANGED(LOADBAR,0) & TRN_HL, DELAY(4NS,6NS,9.5NS), + (CNTENT | CNTENP) & TRN_HL, DELAY(3NS,5.5NS,10NS), + CHANGED(SCLRBAR,0) & TRN_LH, DELAY(5NS,8NS,12NS), + CHANGED(SCLRBAR,0) & TRN_HL, DELAY(7NS,9.5NS,13NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(4NS,9NS,13.5NS), + ACLEAR, DELAY(7.5NS,11NS,16NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(5NS,11NS,17NS), + DELAY(7NS,11NS,17NS) + ) + } + RCOBAR_O = { + CASE( + CNTENT & TRN_LH, DELAY(1NS,3NS,7NS), + CNTENT & TRN_HL, DELAY(2.5NS,5NS,9NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(2NS,5NS,10NS), + CLOCK & TRN_HL, DELAY(4NS,7.5NS,12NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(5NS,10NS,15NS), + CLOCK & TRN_LH, DELAY(5.5NS,10NS,16NS), + ACLEAR, DELAY(7.5NS,11NS,16NS), + DELAY(7.5NS,11NS,16NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE & TRN_LZ, DELAY(1.5NS,3.5NS,6.5NS), + DISABLE & TRN_HZ, DELAY(1.5NS,3.5NS,7.5NS), + ENABLE & TRN_ZH, DELAY(2NS,4NS,7.5NS), + CLOCK & TRN_LH, DELAY(3NS,6NS,10NS), + ENABLE & TRN_ZL, DELAY(4NS,6.5NS,10NS), + CLOCK & TRN_HL, DELAY(4NS,7.5NS,12NS), + ACLEAR, DELAY(5.5NS,8NS,12NS), + DELAY(5.5NS,8NS,12NS) + ) + } + BOOLEAN: + SCLEAR = { SCLRBAR!='0 ^ CHANGED(SCLRBAR,0) } + LOAD = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = ACLRBAR + MIN_LO = 5NS + WIDTH: + NODE = CLK + MIN_LO = 6NS + MIN_HI = 8NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & ACLRBAR!='0 & SCLEAR } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 6NS + WHEN = { CHANGED(EN,6NS) & LOAD & ACLRBAR!='0 & SCLEAR } + SETUP_HOLD: + DATA(1) = SCLRBAR + CLOCK LH = CLK + SETUPTIME = 9NS + WHEN = { ACLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 9NS + WHEN = { ACLRBAR!='0 & SCLEAR } + SETUP_HOLD: + DATA(1) = ACLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 7NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME_HI = 12.5NS + SETUPTIME_LO = 17.5NS + WHEN = { ACLRBAR!='0 & SCLEAR & LOAD } * .ENDS * *$ *--------- * 74F569 Synchronous 4-Bit Up/Down Binary Counter w/ 3-state Outputs * * FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTOR * tc 7/30/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74F569 CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I ACLRBAR_I + SCLRBAR_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O CCOBAR_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UDFF DFF(4) DPWR DGND $D_HI ACLRBAR CLK DA DB DC DD QA QB QC QD + QABAR QBBAR QCBAR QDBAR D0_EFF IO_F * UF569LOG LOGICEXP(20,19) DPWR DGND + CLK_I GBAR_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I ACLRBAR_I SCLRBAR_I + A_I B_I C_I D_I QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK GBAR U/DBAR ENPBAR ENTBAR LOADBAR ACLRBAR SCLRBAR A B C D DA DB DC DD + CCOBAR RCOBAR IEN + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + GBAR = { GBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ACLRBAR = { ACLRBAR_I } + SCLRBAR = { SCLRBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UP = { U/DBAR } + DN = { ~U/DBAR } + ILC1 = { ~(SCLRBAR & LOADBAR) } + ILC2 = { ~ILC1 } + IEN = { ~(ENTBAR | ENPBAR | ILC1) } + IUD1 = { UP | DN } + IUD2 = { (UP & QA) | (DN & QABAR) } + IUD3 = { (UP & QA & QB) | (DN & QABAR & QBBAR) } + IUD4 = { (UP & QA & QB & QC) | (DN & QABAR & QBBAR & QCBAR) } + IA1 = { ~((~(IUD1 & IEN) ^ QA) & ILC2) } + IA2 = { ~(~(A & SCLRBAR) & ILC1) } + IB1 = { ~((~(IUD2 & IEN) ^ QB) & ILC2) } + IB2 = { ~(~(B & SCLRBAR) & ILC1) } + IC1 = { ~((~(IUD3 & IEN) ^ QC) & ILC2) } + IC2 = { ~(~(C & SCLRBAR) & ILC1) } + ID1 = { ~((~(IUD4 & IEN) ^ QD) & ILC2) } + ID2 = { ~(~(D & SCLRBAR) & ILC1) } + IRC1 = { UP & ~ENTBAR & QD & QC & QB & QA } + IRC2 = { DN & ~ENTBAR & QDBAR & QCBAR & QBBAR & QABAR } + DA = { IA1 & IA2 } + DB = { IB1 & IB2 } + DC = { IC1 & IC2 } + DD = { ID1 & ID2 } + RCOBAR = { ~(IRC1 | IRC2) } + CCOBAR = { ~(~RCOBAR & ~CLK & IEN) } * UF569DLY PINDLY (6,1,14) DPWR DGND + CCOBAR RCOBAR QA QB QC QD + GBAR + CLK GBAR ENPBAR ENTBAR LOADBAR SCLRBAR ACLRBAR U/DBAR U/DBAR A B C D IEN + CCOBAR_O RCOBAR_O QA_O QB_O QC_O QD_O + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + ACLEAR = { CHANGED_HL(ACLRBAR,0) } + CNTENT = { CHANGED(ENTBAR,0) } + CNTENP = { CHANGED(ENPBAR,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + CCOBAR_O = { + CASE( + CHANGED(CLK,0) & TRN_LH, DELAY(2NS,4.5NS,6NS), + CHANGED(CLK,0) & TRN_HL, DELAY(2NS,4NS,7NS), + (CNTENP | CNTENT) & TRN_LH, DELAY(1.5NS,4NS,7.5NS), + CHANGED(LOADBAR,0) & TRN_LH, DELAY(2.5NS,5NS,8.5NS), + CHANGED(LOADBAR,0) & TRN_HL, DELAY(4NS,6NS,9.5NS), + (CNTENP | CNTENT) & TRN_HL, DELAY(3NS,5.5NS,10NS), + CHANGED(SCLRBAR,0) & TRN_LH, DELAY(5NS,8NS,12NS), + CHANGED(SCLRBAR,0) & TRN_HL, DELAY(7NS,9.5NS,13NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(4NS,9NS,13.5NS), + ACLEAR, DELAY(7.5NS,11NS,16NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(5NS,11NS,17NS), + DELAY(5NS,11NS,17NS) + ) + } + RCOBAR_O = { + CASE( + CNTENT & TRN_LH, DELAY(1NS,3NS,7NS), + CNTENT & TRN_HL, DELAY(2.5NS,5NS,9NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(4NS,6.5NS,12NS), + CLOCK & TRN_HL, DELAY(4NS,7.5NS,12NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(4NS,7.5NS,12NS), + CLOCK & TRN_LH, DELAY(5.5NS,10NS,16NS), + ACLEAR, DELAY(7.5NS,11NS,16NS), + DELAY(7.5NS,11NS,16NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE & TRN_LZ, DELAY(1.5NS,3.5NS,6.5NS), + DISABLE & TRN_HZ, DELAY(1.5NS,3.5NS,7.5NS), + ENABLE & TRN_ZH, DELAY(2NS,4NS,7.5NS), + ENABLE & TRN_ZL, DELAY(4NS,6.5NS,10NS), + CLOCK & TRN_LH, DELAY(3NS,6NS,10NS), + CLOCK & TRN_HL, DELAY(4NS,7.5NS,12NS), + ACLEAR, DELAY(5.5NS,8NS,12NS), + DELAY(5.5NS,8NS,12NS) + ) + } + BOOLEAN: + NOTCLEARING = { SCLRBAR!='0 ^ CHANGED(SCLRBAR,0) } + NOTLOADING = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 90MEG + WIDTH: + NODE = CLK + MIN_LO = 6NS + MIN_HI = 8NS + WIDTH: + NODE = ACLRBAR + MIN_LO = 5NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 4.5NS + HOLDTIME = 2.5NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & ACLRBAR!='0 & NOTCLEARING } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 6NS + WHEN = { CHANGED(IEN,30NS) & ACLRBAR!='0 & NOTLOADING & NOTCLEARING } + SETUP_HOLD: + DATA(1) = SCLRBAR + CLOCK LH = CLK + SETUPTIME = 9NS + WHEN = { ACLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 9NS + WHEN = { ACLRBAR!='0 & NOTCLEARING } + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME_LO = 8NS + SETUPTIME_HI = 12.5NS + WHEN = { ACLRBAR!='0 & NOTCLEARING & NOTLOADING } + SETUP_HOLD: + DATA(1) = ACLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 7NS * .ENDS * *$ *-------- * 74F573 Octal D-TYPE Transparent Latches with 3-STATE Outputs * * 1990 Philips Components, updated 8-29-90 * .subckt 74F573 OEBAR E D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inv DPWR DGND + OEBAR OE + D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQBUF dltch(8) DPWR DGND + $D_HI $D_HI E + D0 D1 D2 D3 D4 D5 D6 D7 + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_F573_1 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQOUT buf3a(8) DPWR DGND + 1QB 2QB 3QB 4QB 5QB 6QB 7QB 8QB + OE + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + D_F573_2 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_F573_1 ugff ( + twghmn=3ns tsudgmn=1ns + thdgmn=3.25ns tpdqlhmn=2.5ns + tpdqlhty=4.5ns tpdqlhmx=6ns + tpdqhlmn=.5ns tpdqhlty=2.5ns + tpdqhlmx=4ns tpgqlhmn=4ns + tpgqlhty=7.5ns tpgqlhmx=9.5ns + tpgqhlmn=2.5ns tpgqhlty=4ns + tpgqhlmx=5ns + ) .model D_F573_2 utgate ( + tplhmn=.5ns tplhty=1ns + tplhmx=2ns tphlmn=.5ns + tphlty=1ns tphlmx=2ns + tpzhmn=2.5ns tpzhty=5.5ns + tpzhmx=9.5ns tpzlmn=2.5ns + tpzhty=5.5ns tpzlmx=8ns + tphzmn=1ns tphzty=3ns + tphzmx=6ns tplzmn=1ns + tplzty=2.5ns tplzmx=5.5ns + ) *$ *---------- * 74F620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74F620 OEBABAR_I OEAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + OEAB_I OEAB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + OEBABAR_I OEBA + D0_GATE IO_F IO_LEVEL={IO_LEVEL} * U3 INV3A(8) DPWR DGND + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + D_F620_AB IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 INV3A(8) DPWR DGND + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OEBA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + D_F620_BA IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_F620_BA UTGATE ( + TPLHMN=2.0NS TPLHTY=4.5NS TPLHMX= 7.5NS + TPHLMN=1.0NS TPHLTY=2.5NS TPHLMX= 5.0NS + TPZHMN=2.5NS TPZHTY=7.5NS TPZHMX=11.5NS + TPZLMN=3.5NS TPZLTY=7.5NS TPZLMX=11.5NS + TPHZMN=2.0NS TPHZTY=4.5NS TPHZMX= 8.0NS + TPLZMN=1.5NS TPLZTY=4.5NS TPLZMX= 7.5NS + ) .MODEL D_F620_AB UTGATE ( + TPLHMN=2.0NS TPLHTY=4.5NS TPLHMX= 7.5NS + TPHLMN=1.0NS TPHLTY=2.5NS TPHLMX= 5.0NS + TPZHMN=4.0NS TPZHTY=7.5NS TPZHMX=11.5NS + TPZLMN=4.0NS TPZLTY=7.5NS TPZLMX=11.0NS + TPHZMN=2.5NS TPHZTY=6.5NS TPHZMX=10.5NS + TPLZMN=3.5NS TPLZTY=6.5NS TPLZMX=10.5NS + ) * .ENDS * *$ *--------- * 74F621 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * IC15 FAST TTL LOGIC SERIES SUPPLEMENT TO IC15, 1991, PHILIPS * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F621 GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF621LOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + GABBAR = { ~GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { B1_B | GBABAR } + A2 = { B2_B | GBABAR } + A3 = { B3_B | GBABAR } + A4 = { B4_B | GBABAR } + A5 = { B5_B | GBABAR } + A6 = { B6_B | GBABAR } + A7 = { B7_B | GBABAR } + A8 = { B8_B | GBABAR } + B1 = { A1_B | GABBAR } + B2 = { A2_B | GABBAR } + B3 = { A3_B | GABBAR } + B4 = { A4_B | GABBAR } + B5 = { A5_B | GABBAR } + B6 = { A6_B | GABBAR } + B7 = { A7_B | GABBAR } + B8 = { A8_B | GABBAR } * UF621DLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(5.5NS,10NS,14NS), + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(3NS,6.5NS,11NS), + A_OUTPUT & TRN_LH, DELAY(5.5NS,9NS,12.5NS), + A_OUTPUT & TRN_HL, DELAY(3NS,5.5NS,8NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(6.5NS,11NS,15NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(6NS,12NS,17NS), + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(3NS,6.5NS,10NS), + B_OUTPUT & TRN_LH, DELAY(5.5NS,9.5NS,13NS), + B_OUTPUT & TRN_HL, DELAY(3.5NS,6NS,8.5NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(7NS,13NS,18NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74F622 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * IC15 FAST TTL LOGIC SERIES SUPPLEMENT TO IC15, 1991, PHILIPS * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74F622 GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF622LOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GBA = { ~GBABAR } + GAB = { GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { ~(B1_B & GBA) } + A2 = { ~(B2_B & GBA) } + A3 = { ~(B3_B & GBA) } + A4 = { ~(B4_B & GBA) } + A5 = { ~(B5_B & GBA) } + A6 = { ~(B6_B & GBA) } + A7 = { ~(B7_B & GBA) } + A8 = { ~(B8_B & GBA) } + B1 = { ~(A1_B & GAB) } + B2 = { ~(A2_B & GAB) } + B3 = { ~(A3_B & GAB) } + B4 = { ~(A4_B & GAB) } + B5 = { ~(A5_B & GAB) } + B6 = { ~(A6_B & GAB) } + B7 = { ~(A7_B & GAB) } + B8 = { ~(A8_B & GAB) } * UF622DLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(8NS,10.5NS,12.5NS), + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(6NS,8NS,10.5NS), + A_OUTPUT & TRN_LH, DELAY(7.5NS,10NS,12.5NS), + A_OUTPUT & TRN_HL, DELAY(1.5NS,3.5NS,5.5NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(9NS,11.5NS,13.5NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(10NS,12.5NS,15.5NS), + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(5NS,7.5NS,9.5NS), + B_OUTPUT & TRN_LH, DELAY(8NS,11NS,13.5NS), + B_OUTPUT & TRN_HL, DELAY(1.5NS,4NS,6NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(11NS,13.5NS,16.5NS) ;DEFAULT + ) + } * .ENDS * *$ *---------- * 74F623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74F623 OEBABAR_I OEAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + OEAB_I OEAB + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + OEBABAR_I OEBA + D0_GATE IO_F IO_LEVEL={IO_LEVEL} * U3 BUF3A(8) DPWR DGND + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + D_F623_AB IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 BUF3A(8) DPWR DGND + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OEBA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + D_F623_BA IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_F623_AB UTGATE ( + TPLHMN=2.0NS TPLHTY=4.0NS TPLHMX= 6.5NS + TPHLMN=2.5NS TPHLTY=5.0NS TPHLMX= 7.5NS + TPZHMN=5.0NS TPZHTY=8.0NS TPZHMX=11.5NS + TPZLMN=4.5NS TPZLTY=7.0NS TPZLMX= 9.5NS + TPHZMN=3.0NS TPHZTY=6.0NS TPHZMX=10.0NS + TPLZMN=4.0NS TPLZTY=7.0NS TPLZMX=10.0NS + ) .MODEL D_F623_BA UTGATE ( + TPLHMN=2.0NS TPLHTY=4.0NS TPLHMX= 6.5NS + TPHLMN=2.5NS TPHLTY=4.5NS TPHLMX= 7.5NS + TPZHMN=5.0NS TPZHTY=8.5NS TPZHMX=12.0NS + TPZLMN=5.0NS TPZLTY=7.5NS TPZLMX=10.0NS + TPHZMN=2.5NS TPHZTY=4.5NS TPHZMX= 7.5NS + TPLZMN=2.5NS TPLZTY=4.5NS TPLZMX= 7.0NS + ) * .ENDS * *$ *---------- * 74F640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * FAST TTL LOGIC SERIES, 1991, PHILIPS SEMICONDUCTORS * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74F640 OEBAR_I T/RBAR_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + OEBAR_I T/RBAR_I + OEBAR T/RBAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + T/RBAR T/RBARBAR + D0_GATE IO_F U3 NORA(2,2) DPWR DGND + T/RBARBAR OEBAR T/RBAR OEBAR + ENABLEAB ENABLEBA + D0_GATE IO_F * U4 INV3A(8) DPWR DGND + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + ENABLEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + D_F640 IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 INV3A(8) DPWR DGND + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + ENABLEBA + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + D_F640 IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_F640 UTGATE ( + TPLHMN=2.0NS TPLHTY=4.5NS TPLHMX= 8.0NS + TPHLMN=1.0NS TPHLTY=2.5NS TPHLMX= 5.5NS + TPZHMN=5.0NS TPZHTY=6.5NS TPZHMX=12.0NS + TPZLMN=5.0NS TPZLTY=7.0NS TPZLMX=11.0NS + TPHZMN=1.5NS TPHZTY=3.5NS TPHZMX= 8.0NS + TPLZMN=2.0NS TPLZTY=4.5NS TPLZMX= 7.5NS + ) * .ENDS * *$ *--------- * 74F651 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH INVERTED 3-STATE OUTPUTS * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTORS * JSW 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74F651 OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I A0_B A1_B A2_B A3_B + A4_B A5_B A6_B A7_B B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CPAB + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * U2 DFF(8) DPWR DGND $D_HI $D_HI CPBA + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * U3 BUF3A(8) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O IOEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U4 BUF3A(8) DPWR DGND + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O OEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * U5 BUF3A(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 OEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U6 BUF3A(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 IOEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * UF651LOG LOGICEXP(38,40) DPWR DGND + OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I A0_B A1_B A2_B A3_B A4_B A5_B + A6_B A7_B B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B QA0 QA1 QA2 + QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 + QB5 QB6 QB7 + OEBABAR OEAB CPBA SBA CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O B0_O B1_O B2_O B3_O B4_O B5_O + B6_O B7_O IOEAB IOEBABAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBABAR = { OEBABAR_I } + OEAB = { OEAB_I } + CPBA = { CPBA_I } + SBA = { SBA_I } + CPAB = { CPAB_I } + SAB = { SAB_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IOEAB = { ~OEAB } + IOEBABAR = { ~OEBABAR } + A0_O = { ~((SBA & QA0) | (ISBA & B0)) } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) } + B0_O = { ~((SAB & QB0) | (ISAB & A0)) } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } * UF651DLY PINDLY (16,2,22) DPWR DGND + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + OEBABAR OEAB + CPBA SBA CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 B6 B7 + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CPAB,0) } + CLOCK_BA = { CHANGED_LH(CPBA,0) } + SELECT_AB = { CHANGED(SAB,0) } + SELECT_BA = { CHANGED(SBA,0) } + BUS_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + BUS_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + TRISTATE: + ENABLE LO OEBABAR + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + BUS_B & TRN_HL, DELAY(3NS,6NS,10NS), + SELECT_BA & TRN_HL, DELAY(4NS,6.5NS,10NS), + TRN_ZH, DELAY(3.5NS,7NS,11NS), + BUS_B & TRN_LH, DELAY(2.5NS,6NS,12NS), + CLOCK_BA & TRN_HL, DELAY(5NS,7.5NS,12NS), + SELECT_BA & TRN_LH, DELAY(4NS,7NS,12.5NS), + CLOCK_BA & TRN_LH, DELAY(4.5NS,7NS,12.5NS), + TRN_ZL, DELAY(5.5NS,10.5NS,13NS), + TRN_HZ, DELAY(4NS,9.5NS,14.5NS), + TRN_LZ, DELAY(4NS,9NS,15.5NS), + DELAY(5NS,10NS,16NS) + ) + } + TRISTATE: + ENABLE HI OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + BUS_A & TRN_HL, DELAY(3NS,6NS,10NS), + SELECT_AB & TRN_HL, DELAY(4NS,6.5NS,10NS), + TRN_ZH, DELAY(3.5NS,7NS,11NS), + BUS_A & TRN_LH, DELAY(2.5NS,6NS,12NS), + CLOCK_AB & TRN_HL, DELAY(5NS,7.5NS,12NS), + SELECT_AB & TRN_LH, DELAY(4NS,7NS,12.5NS), + CLOCK_AB & TRN_LH, DELAY(4.5NS,7NS,12.5NS), + TRN_ZL, DELAY(5.5NS,10.5NS,13NS), + TRN_HZ, DELAY(4NS,9.5NS,14.5NS), + TRN_LZ, DELAY(4NS,9NS,15.5NS), + DELAY(5NS,10NS,16NS) + ) + } + FREQ: + NODE = CPBA + MAXFREQ = 80MEG + FREQ: + NODE = CPAB + MAXFREQ = 80MEG + WIDTH: + NODE = CPBA + MIN_LO = 6.5NS + MIN_HI = 4.5NS + WIDTH: + NODE = CPAB + MIN_LO = 6.5NS + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B4 B5 B6 B7 + CLOCK LH = CPBA + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEBABAR + CLOCK LH = OEAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEAB + CLOCK HL = OEBABAR + SETUPTIME = 5NS * .ENDS * *$ *--------- * 74F651A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH INVERTED 3-STATE OUTPUTS * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTORS * JSW 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74F651A OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I A0_B A1_B A2_B + A3_B A4_B A5_B A6_B A7_B B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CPAB + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * U2 DFF(8) DPWR DGND $D_HI $D_HI CPBA + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F * U3 BUF3A(8) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O IOEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U4 BUF3A(8) DPWR DGND + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O OEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * U5 BUF3A(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 OEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U6 BUF3A(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 IOEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * UF651ALOG LOGICEXP(38,40) DPWR DGND + OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I A0_B A1_B A2_B A3_B A4_B A5_B + A6_B A7_B B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B QA0 QA1 QA2 + QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 + QB5 QB6 QB7 + OEBABAR OEAB CPBA SBA CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O B0_O B1_O B2_O B3_O B4_O B5_O + B6_O B7_O IOEAB IOEBABAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBABAR = { OEBABAR_I } + OEAB = { OEAB_I } + CPBA = { CPBA_I } + SBA = { SBA_I } + CPAB = { CPAB_I } + SAB = { SAB_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IOEAB = { ~OEAB } + IOEBABAR = { ~OEBABAR } + A0_O = { ~((SBA & QA0) | (ISBA & B0)) } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) } + B0_O = { ~((SAB & QB0) | (ISAB & A0)) } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } * UF651ADLY PINDLY (16,2,22) DPWR DGND + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + OEBABAR OEAB + CPBA SBA CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 B6 B7 + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CPAB,0) } + CLOCK_BA = { CHANGED_LH(CPBA,0) } + SELECT_AB = { CHANGED(SAB,0) } + SELECT_BA = { CHANGED(SBA,0) } + BUS_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + BUS_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + TRISTATE: + ENABLE LO OEBABAR + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + BUS_B & TRN_HL, DELAY(2NS,4.5NS,9NS), + BUS_B & TRN_LH, DELAY(2NS,5NS,9NS), + SELECT_BA & TRN_HL, DELAY(4NS,6.5NS,9NS), + CLOCK_BA & TRN_HL, DELAY(4NS,6.5NS,10NS), + TRN_ZH, DELAY(3.5NS,7NS,10NS), + TRN_$Z, DELAY(4NS,8NS,10.5NS), + TRN_ZL, DELAY(4.5NS,8.5NS,11NS), + SELECT_BA & TRN_LH, DELAY(4NS,7NS,11.5NS), + CLOCK_BA & TRN_LH, DELAY(4.5NS,7NS,11.5NS), + DELAY(5NS,8NS,12NS) + ) + } + TRISTATE: + ENABLE HI OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + BUS_A & TRN_HL, DELAY(2NS,4.5NS,9NS), + BUS_A & TRN_LH, DELAY(2NS,5NS,9NS), + SELECT_AB & TRN_HL, DELAY(4NS,6.5NS,9NS), + CLOCK_AB & TRN_HL, DELAY(4NS,6.5NS,10NS), + TRN_ZH, DELAY(3.5NS,7NS,10NS), + TRN_$Z, DELAY(4NS,8NS,10.5NS), + TRN_ZL, DELAY(4.5NS,8.5NS,11NS), + SELECT_AB & TRN_LH, DELAY(4NS,7NS,11.5NS), + CLOCK_AB & TRN_LH, DELAY(4.5NS,7NS,11.5NS), + DELAY(5NS,8NS,12NS) + ) + } + FREQ: + NODE = CPBA + MAXFREQ = 80MEG + FREQ: + NODE = CPAB + MAXFREQ = 80MEG + WIDTH: + NODE = CPBA + MIN_LO = 6.5NS + MIN_HI = 4.5NS + WIDTH: + NODE = CPAB + MIN_LO = 6.5NS + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B4 B5 B6 B7 + CLOCK LH = CPBA + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEBABAR + CLOCK LH = OEAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEAB + CLOCK HL = OEBABAR + SETUPTIME = 5NS * .ENDS * *$ *--------- * 74F652 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH 3-STATE OUTPUTS * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTORS * TC 09/07/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74F652 OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CPAB + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB0BAR QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR + D0_EFF IO_F * U2 DFF(8) DPWR DGND $D_HI $D_HI CPBA + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA0BAR QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR + D0_EFF IO_F * U3 BUF3A(8) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O IOEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U4 BUF3A(8) DPWR DGND + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O OEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * U5 BUF3A(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 OEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U6 BUF3A(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 IOEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * UF652LOG LOGICEXP(38,40) DPWR DGND + OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + QA0BAR QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR + QB0BAR QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR + OEBABAR OEAB CPBA SBA CPAB SAB + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O IOEAB IOEBABAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBABAR = { OEBABAR_I } + OEAB = { OEAB_I } + CPBA = { CPBA_I } + SBA = { SBA_I } + CPAB = { CPAB_I } + SAB = { SAB_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IOEAB = { ~OEAB } + IOEBABAR = { ~OEBABAR } + A0_O = { ~((SBA & QA0BAR) | (ISBA & ~B0)) } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) } + B0_O = { ~((SAB & QB0BAR) | (ISAB & ~A0)) } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } * UF652DLY PINDLY (16,2,22) DPWR DGND + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + OEBABAR OEAB + CPBA SBA CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 B6 B7 + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CPAB,0) } + CLOCK_BA = { CHANGED_LH(CPBA,0) } + SELECT_AB = { CHANGED(SAB,0) } + SELECT_BA = { CHANGED(SBA,0) } + BUS_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + BUS_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + TRISTATE: + ENABLE LO OEBABAR + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + CLOCK_BA & TRN_LH, DELAY(4.5NS,7NS,12.5NS), + SELECT_BA & TRN_LH, DELAY(4NS,7NS,12.5NS), + CLOCK_BA & TRN_HL, DELAY(5NS,7.5NS,12NS), + BUS_B & TRN_LH, DELAY(2.5NS,6NS,12NS), + SELECT_BA & TRN_HL, DELAY(4NS,6.5NS,10NS), + BUS_B & TRN_HL, DELAY(3NS,6NS,10NS), + TRN_ZH, DELAY(3.5NS,7NS,11NS), + TRN_ZL, DELAY(5.5NS,10.5NS,13NS), + TRN_HZ, DELAY(4NS,9.5NS,14.5NS), + TRN_LZ, DELAY(4NS,9NS,15.5NS), + DELAY(5NS,10NS,16NS) + ) + } + TRISTATE: + ENABLE HI OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + CLOCK_AB & TRN_LH, DELAY(4.5NS,7NS,12.5NS), + SELECT_AB & TRN_LH, DELAY(4NS,7NS,12.5NS), + CLOCK_AB & TRN_HL, DELAY(5NS,7.5NS,12NS), + BUS_A & TRN_LH, DELAY(2.5NS,6NS,12NS), + SELECT_AB & TRN_HL, DELAY(4NS,6.5NS,10NS), + BUS_A & TRN_HL, DELAY(3NS,6NS,10NS), + TRN_ZH, DELAY(3.5NS,7NS,11NS), + TRN_ZL, DELAY(5.5NS,10.5NS,13NS), + TRN_HZ, DELAY(4NS,9.5NS,14.5NS), + TRN_LZ, DELAY(4NS,9NS,15.5NS), + DELAY(5NS,10NS,16NS) + ) + } + FREQ: + NODE = CPBA + MAXFREQ = 80MEG + FREQ: + NODE = CPAB + MAXFREQ = 80MEG + WIDTH: + NODE = CPBA + MIN_LO = 6.5NS + MIN_HI = 4.5NS + WIDTH: + NODE = CPAB + MIN_LO = 6.5NS + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B4 B5 B6 B7 + CLOCK LH = CPBA + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEBABAR + CLOCK LH = OEAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEAB + CLOCK HL = OEBABAR + SETUPTIME = 5NS * .ENDS * *$ *--------- * 74F652A BUS TRANSCEIVERS AND REGISTERS OCTAL WITH 3-STATE OUTPUTS * * THE FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTORS * TC 09/07/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74F652A OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CPAB + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB0BAR QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR + D0_EFF IO_F * U2 DFF(8) DPWR DGND $D_HI $D_HI CPBA + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA0BAR QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR + D0_EFF IO_F * U3 BUF3A(8) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O IOEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U4 BUF3A(8) DPWR DGND + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O OEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * U5 BUF3A(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 OEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F * U6 BUF3A(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 IOEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F * UF652ALOG LOGICEXP(38,40) DPWR DGND + OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + QA0BAR QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR + QB0BAR QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR + OEBABAR OEAB CPBA SBA CPAB SAB + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O IOEAB IOEBABAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBABAR = { OEBABAR_I } + OEAB = { OEAB_I } + CPBA = { CPBA_I } + SBA = { SBA_I } + CPAB = { CPAB_I } + SAB = { SAB_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IOEAB = { ~OEAB } + IOEBABAR = { ~OEBABAR } + A0_O = { ~((SBA & QA0BAR) | (ISBA & ~B0)) } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) } + B0_O = { ~((SAB & QB0BAR) | (ISAB & ~A0)) } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } * UF652ADLY PINDLY (16,2,22) DPWR DGND + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + OEBABAR OEAB + CPBA SBA CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 B6 B7 + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CPAB,0) } + CLOCK_BA = { CHANGED_LH(CPBA,0) } + SELECT_AB = { CHANGED(SAB,0) } + SELECT_BA = { CHANGED(SBA,0) } + BUS_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + BUS_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + TRISTATE: + ENABLE LO OEBABAR + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + CLOCK_BA & TRN_LH, DELAY(4.5NS,7NS,11.5NS), + SELECT_BA & TRN_LH, DELAY(4NS,7NS,11.5NS), + CLOCK_BA & TRN_HL, DELAY(4NS,6.5NS,10NS), + SELECT_BA & TRN_HL, DELAY(4NS,6.5NS,9NS), + BUS_B & TRN_LH, DELAY(2NS,5NS,9NS), + BUS_B & TRN_HL, DELAY(2NS,4.5NS,9NS), + TRN_ZH, DELAY(3.5NS,7NS,10NS), + TRN_ZL, DELAY(4.5NS,8.5NS,11NS), + TRN_$Z, DELAY(4NS,8NS,10.5NS), + DELAY(5NS,8NS,12NS) + ) + } + TRISTATE: + ENABLE HI OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + CLOCK_AB & TRN_LH, DELAY(4.5NS,7NS,11.5NS), + SELECT_AB & TRN_LH, DELAY(4NS,7NS,11.5NS), + CLOCK_AB & TRN_HL, DELAY(4NS,6.5NS,10NS), + SELECT_AB & TRN_HL, DELAY(4NS,6.5NS,9NS), + BUS_A & TRN_LH, DELAY(2NS,5NS,9NS), + BUS_A & TRN_HL, DELAY(2NS,4.5NS,9NS), + TRN_ZH, DELAY(3.5NS,7NS,10NS), + TRN_ZL, DELAY(4.5NS,8.5NS,11NS), + TRN_$Z, DELAY(4NS,8NS,10.5NS), + DELAY(5NS,8NS,12NS) + ) + } + FREQ: + NODE = CPBA + MAXFREQ = 80MEG + FREQ: + NODE = CPAB + MAXFREQ = 80MEG + WIDTH: + NODE = CPBA + MIN_LO = 6.5NS + MIN_HI = 4.5NS + WIDTH: + NODE = CPAB + MIN_LO = 6.5NS + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B4 B5 B6 B7 + CLOCK LH = CPBA + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEBABAR + CLOCK LH = OEAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEAB + CLOCK HL = OEBABAR + SETUPTIME = 5NS * .ENDS * *$ *--------- * 74F653 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH OPEN-COLLECTOR OUTPUTS * * FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTORS * TC 09/08/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC IS ADDED TO MODEL THE BIDIRECTIONAL PINS AND THE * FUNCTION OF OEBABAR IN CONTROLLING THE OPEN-COLLECTOR A BUS. .SUBCKT 74F653 OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 DFF(8) DPWR DGND $D_HI $D_HI CPAB + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F U2 DFF(8) DPWR DGND $D_HI $D_HI CPBA + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_F U3 BUF3A(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 OEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F U4 BUF3A(8) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O IOEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F U5 BUF3A(8) DPWR DGND + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O OEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F U6 BUF3A(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 IOEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F UF653LOG LOGICEXP(38,40) DPWR DGND + OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 + OEBABAR OEAB CPBA SBA CPAB SAB + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O IOEAB IOEBABAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBABAR = { OEBABAR_I } + OEAB = { OEAB_I } + CPBA = { CPBA_I } + SBA = { SBA_I } + CPAB = { CPAB_I } + SAB = { SAB_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IOEAB = { ~OEAB } + IOEBABAR = { ~OEBABAR } + A0_O = { ~((SBA & QA0) | (ISBA & B0)) | OEBABAR } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) | OEBABAR } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) | OEBABAR } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) | OEBABAR } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) | OEBABAR } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) | OEBABAR } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) | OEBABAR } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) | OEBABAR } + B0_O = { ~((SAB & QB0) | (ISAB & A0)) } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } UF653DLY_1 PINDLY(8,0,11) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O + OEBABAR CPBA SBA B0 B1 B2 B3 B4 B5 B6 B7 + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CPBA,0) } + ENABLE = { CHANGED(OEBABAR,0) } + SEL_BA = { CHANGED(SBA,0) } + BUS_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + PINDLY: + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + ENABLE & TRN_LH, DELAY(6NS,16NS,23NS), + SEL_BA & TRN_LH, DELAY(4.5NS,15NS,21.5NS), + CLOCK_BA & TRN_LH, DELAY(5.5NS,14.5NS,21NS), + BUS_B & TRN_LH, DELAY(4NS,14NS,20NS), + ENABLE & TRN_HL, DELAY(6NS,10NS,14NS), + CLOCK_BA & TRN_HL, DELAY(5.5NS,8NS,11.5NS), + SEL_BA & TRN_HL, DELAY(4.5NS,7.5NS,11.5NS), + BUS_B & TRN_HL, DELAY(4NS,7NS,10.5NS), + DELAY(7NS,17NS,24NS) + ) + } UF653DLY_2 PINDLY(8,1,10) DPWR DGND + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + OEAB + CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CPAB,0) } + SEL_AB = { CHANGED(SAB,0) } + BUS_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + TRISTATE: + ENABLE HI OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + CLOCK_AB & TRN_HL, DELAY(5.5NS,8NS,12NS), + CLOCK_AB & TRN_LH, DELAY(5NS,7.5NS,12NS), + SEL_AB & TRN_LH, DELAY(4.5NS,7NS,12NS), + BUS_A & TRN_LH, DELAY(3.5NS,6NS,11NS), + SEL_AB & TRN_HL, DELAY(4.5NS,7NS,10.5NS), + BUS_A & TRN_HL, DELAY(4NS,6.5NS,10NS), + TRN_ZH, DELAY(4NS,6.5NS,10NS), + TRN_ZL, DELAY(5.5NS,8NS,11.5NS), + TRN_HZ, DELAY(6NS,9.5NS,14.5NS), + TRN_LZ, DELAY(5.5NS,9NS,14.5NS), + DELAY(7NS,10NS,15NS) + ) + } UF653CON CONSTRAINT(20) DPWR DGND + OEBABAR OEAB CPAB CPBA A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + IO_F + FREQ: + NODE = CPAB + MAXFREQ = 85MEG + FREQ: + NODE = CPBA + MAXFREQ = 45MEG + WIDTH: + NODE = CPAB + MIN_LO = 6.5NS + MIN_HI = 4.5NS + WIDTH: + NODE = CPBA + MIN_LO = 6.5NS + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPAB + SETUPTIME_LO = 5NS + SETUPTIME_HI = 5.5NS + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B4 B5 B6 B7 + CLOCK LH = CPBA + SETUPTIME_LO = 5NS + SETUPTIME_HI = 5.5NS + SETUP_HOLD: + DATA(1) = OEBABAR + CLOCK LH = OEAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEAB + CLOCK HL = OEBABAR + SETUPTIME = 5NS .ENDS *$ *--------- * 74F654 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH OPEN-COLLECTOR OUTPUTS * * FAST LOGIC DATA HANDBOOK, 1989, PHILIPS SEMICONDUCTORS * TC 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC IS ADDED TO MODEL THE BIDIRECTIONAL PINS AND THE * FUNCTION OF OEBABAR IN CONTROLLING THE OPEN-COLLECTOR A BUS. .SUBCKT 74F654 OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 DFF(8) DPWR DGND $D_HI $D_HI CPAB + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB0BAR QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR + D0_EFF IO_F U2 DFF(8) DPWR DGND $D_HI $D_HI CPBA + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA0BAR QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR + D0_EFF IO_F U3 BUF3A(8) DPWR DGND + A0 A1 A2 A3 A4 A5 A6 A7 OEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F U4 BUF3A(8) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O IOEBABAR + A0_IO A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO + D0_TGATE IO_F U5 BUF3A(8) DPWR DGND + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O OEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F U6 BUF3A(8) DPWR DGND + B0 B1 B2 B3 B4 B5 B6 B7 IOEAB + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + D0_TGATE IO_F UF654LOG LOGICEXP(38,40) DPWR DGND + OEBABAR_I OEAB_I CPBA_I SBA_I CPAB_I SAB_I + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + QA0BAR QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR + QB0BAR QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR + OEBABAR OEAB CPBA SBA CPAB SAB + A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O + B0_O B1_O B2_O B3_O B4_O B5_O B6_O B7_O IOEAB IOEBABAR + D0_GATE IO_F IO_LEVEL={IO_LEVEL} + LOGIC: + OEBABAR = { OEBABAR_I } + OEAB = { OEAB_I } + CPBA = { CPBA_I } + SBA = { SBA_I } + CPAB = { CPAB_I } + SAB = { SAB_I } + A0 = { A0_B } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + B0 = { B0_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IOEAB = { ~OEAB } + IOEBABAR = { ~OEBABAR } + A0_O = { ~((SBA & QA0BAR) | (ISBA & ~B0)) | OEBABAR } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) | OEBABAR } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) | OEBABAR } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) | OEBABAR } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) | OEBABAR } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) | OEBABAR } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) | OEBABAR } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) | OEBABAR } + B0_O = { ~((SAB & QB0BAR) | (ISAB & ~A0)) } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } UF654DLY_1 PINDLY(8,0,11) DPWR DGND + A0_O A1_O A2_O A3_O A4_O A5_O A6_O A7_O + OEBABAR CPBA SBA B0 B1 B2 B3 B4 B5 B6 B7 + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B + IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CPBA,0) } + ENABLE = { CHANGED(OEBABAR,0) } + SEL_BA = { CHANGED(SBA,0) } + BUS_B = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | + CHANGED(B4,0) | CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) } + PINDLY: + A0_B A1_B A2_B A3_B A4_B A5_B A6_B A7_B = { + CASE( + ENABLE & TRN_LH, DELAY(6NS,16NS,23NS), + SEL_BA & TRN_LH, DELAY(4.5NS,15NS,21.5NS), + CLOCK_BA & TRN_LH, DELAY(5.5NS,14.5NS,21NS), + BUS_B & TRN_LH, DELAY(4NS,14NS,20NS), + ENABLE & TRN_HL, DELAY(6NS,10NS,14NS), + CLOCK_BA & TRN_HL, DELAY(5.5NS,8NS,11.5NS), + SEL_BA & TRN_HL, DELAY(4.5NS,7.5NS,11.5NS), + BUS_B & TRN_HL, DELAY(4NS,7NS,10.5NS), + DELAY(7NS,17NS,24NS) + ) + } UF654DLY_2 PINDLY(8,1,10) DPWR DGND + B0_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO + OEAB + CPAB SAB A0 A1 A2 A3 A4 A5 A6 A7 + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B + IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CPAB,0) } + SEL_AB = { CHANGED(SAB,0) } + BUS_A = { CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | + CHANGED(A4,0) | CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) } + TRISTATE: + ENABLE HI OEAB + B0_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B = { + CASE( + CLOCK_AB & TRN_HL, DELAY(5.5NS,8NS,12NS), + CLOCK_AB & TRN_LH, DELAY(5NS,7.5NS,12NS), + SEL_AB & TRN_LH, DELAY(4.5NS,7NS,12NS), + BUS_A & TRN_LH, DELAY(3.5NS,6NS,11NS), + SEL_AB & TRN_HL, DELAY(4.5NS,7NS,10.5NS), + BUS_A & TRN_HL, DELAY(4NS,6.5NS,10NS), + TRN_ZH, DELAY(4NS,6.5NS,10NS), + TRN_ZL, DELAY(5.5NS,8NS,11.5NS), + TRN_HZ, DELAY(6NS,9.5NS,14.5NS), + TRN_LZ, DELAY(5.5NS,9NS,14.5NS), + DELAY(7NS,10NS,15NS) + ) + } UF654CON CONSTRAINT(20) DPWR DGND + OEBABAR OEAB CPAB CPBA A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 + IO_F + FREQ: + NODE = CPAB + MAXFREQ = 85MEG + FREQ: + NODE = CPBA + MAXFREQ = 45MEG + WIDTH: + NODE = CPAB + MIN_LO = 6.5NS + MIN_HI = 4.5NS + WIDTH: + NODE = CPBA + MIN_LO = 6.5NS + MIN_HI = 4.5NS + SETUP_HOLD: + DATA(8) = A0 A1 A2 A3 A4 A5 A6 A7 + CLOCK LH = CPAB + SETUPTIME_LO = 5NS + SETUPTIME_HI = 5.5NS + SETUP_HOLD: + DATA(8) = B0 B1 B2 B3 B4 B5 B6 B7 + CLOCK LH = CPBA + SETUPTIME_LO = 5NS + SETUPTIME_HI = 5.5NS + SETUP_HOLD: + DATA(1) = OEBABAR + CLOCK LH = OEAB + SETUPTIME = 5NS + SETUP_HOLD: + DATA(1) = OEAB + CLOCK HL = OEBABAR + SETUPTIME = 5NS .ENDS *$ *--------- * 74F670 REGISTER FILES 4X4 WITH 3-STATE OUTPUTS * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 7-14-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F670 WEBAR_I REBAR_I WA_I WB_I RA_I RB_I D0_I D1_I D2_I D3_I + Q0_O Q1_O Q2_O Q3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UA DLTCH(4) DPWR DGND + $D_HI $D_HI GATEA + D0 D1 D2 D3 + AQ0 AQ1 AQ2 AQ3 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_F UB DLTCH(4) DPWR DGND + $D_HI $D_HI GATEB + D0 D1 D2 D3 + BQ0 BQ1 BQ2 BQ3 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_F UC DLTCH(4) DPWR DGND + $D_HI $D_HI GATEC + D0 D1 D2 D3 + CQ0 CQ1 CQ2 CQ3 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_F UD DLTCH(4) DPWR DGND + $D_HI $D_HI GATED + D0 D1 D2 D3 + DQ0 DQ1 DQ2 DQ3 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_F * UF670LOG LOGICEXP (26,18) DPWR DGND + WEBAR_I REBAR_I WA_I WB_I RA_I RB_I D0_I D1_I D2_I D3_I + AQ0 AQ1 AQ2 AQ3 BQ0 BQ1 BQ2 BQ3 CQ0 CQ1 CQ2 CQ3 DQ0 DQ1 DQ2 DQ3 + WEBAR REBAR WA WB RA RB D0 D1 D2 D3 + GATEA GATEB GATEC GATED Q0 Q1 Q2 Q3 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + WEBAR = { WEBAR_I } + REBAR = { REBAR_I } + WA = { WA_I } + WB = { WB_I } + RA = { RA_I } + RB = { RB_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + ENABLE2 = { ~(WEBAR | WB) } + ENABLE1 = { ~(WEBAR | ENABLE2) } + GATEA = { ENABLE2 & ~WA } + GATEB = { ENABLE2 & WA } + GATEC = { ENABLE1 & ~WA } + GATED = { ENABLE1 & WA } + Q0 = { (AQ0 & ~RA & ~RB) | + (BQ0 & RA & ~RB) | + (CQ0 & ~RA & RB) | + (DQ0 & RA & RB) + } + Q1 = { (AQ1 & ~RA & ~RB) | + (BQ1 & RA & ~RB) | + (CQ1 & ~RA & RB) | + (DQ1 & RA & RB) + } + Q2 = { (AQ2 & ~RA & ~RB) | + (BQ2 & RA & ~RB) | + (CQ2 & ~RA & RB) | + (DQ2 & RA & RB) + } + Q3 = { (AQ3 & ~RA & ~RB) | + (BQ3 & RA & ~RB) | + (CQ3 & ~RA & RB) | + (DQ3 & RA & RB) + } * UF670DLY PINDLY (4,1,9) DPWR DGND + Q0 Q1 Q2 Q3 + REBAR + WEBAR RA RB D0 D1 D2 D3 WA WB + Q0_O Q1_O Q2_O Q3_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + WRITEEN = { CHANGED(WEBAR,0) } + READ = { CHANGED(RA,0) | CHANGED(RB,0) } + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | + CHANGED(D2,0) | CHANGED(D3,0) } + + TRISTATE: + ENABLE LO REBAR + Q0_O Q1_O Q2_O Q3_O = { + CASE ( + TRN_ZH, DELAY(2.5NS,7.0NS,13.0NS), + TRN_ZL, DELAY(4.0NS,6.5NS,10.0NS), + TRN_HZ, DELAY(1.5NS,3.0NS, 7.5NS), + TRN_LZ, DELAY(3.0NS,5.0NS, 8.5NS), + READ & TRN_LH, DELAY(3.0NS,5.5NS,10.0NS), + READ & TRN_HL, DELAY(3.5NS,5.5NS, 9.0NS), + DATA & TRN_LH, DELAY(3.0NS,6.0NS, 9.5NS), + DATA & TRN_HL, DELAY(5.5NS,8.0NS,12.5NS), + WRITEEN & TRN_LH, DELAY(4.5NS,7.0NS,11.0NS), + WRITEEN & TRN_HL, DELAY(6.0NS,8.5NS,12.5NS), + DELAY(6.0NS,8.5NS,12.5NS) + ) + } + + WIDTH: + NODE = REBAR + MIN_LO = 8.5NS + WIDTH: + NODE = WEBAR + MIN_LO = 7NS + SETUP_HOLD: + DATA(4) = D0 D1 D2 D3 + CLOCK LH = WEBAR + SETUPTIME_HI = 1.5NS + SETUPTIME_LO = 7.0NS + HOLDTIME_LO = 1.0NS + GENERAL: + WHEN = { WEBAR!='1 & (CHANGED(WA,0NS) | CHANGED(WB,0NS)) } + MESSAGE = "WA AND WB MUST BE STABLE WHILE WEBAR IS LOW" * .ENDS * *$ *--------- * 74F881 ALU / FUNCTION GENERATOR * * IC15 FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-11-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74F881 A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I + B3BAR_I S0_I S1_I S2_I S3_I M_I CN_I F0BAR_O F1BAR_O F2BAR_O F3BAR_O + AEQUALB_O PBAR_O GBAR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UF881LOG LOGICEXP (14,22) DPWR DGND + A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I B3BAR_I + S0_I S1_I S2_I S3_I M_I CN_I + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR + S0 S1 S2 S3 M CN + F0BAR F1BAR F2BAR F3BAR AEQUALB PBAR GBAR CN+4 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + A0BAR = { A0BAR_I } + A1BAR = { A1BAR_I } + A2BAR = { A2BAR_I } + A3BAR = { A3BAR_I } + B0BAR = { B0BAR_I } + B1BAR = { B1BAR_I } + B2BAR = { B2BAR_I } + B3BAR = { B3BAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + S3 = { S3_I } + M = { M_I } + CN = { CN_I } + + TOP3 = { ~( (A3BAR & B3BAR & S3) | (A3BAR & ~B3BAR & S2) ) } + BOT3 = { ~( (~B3BAR & S1) | A3BAR | (B3BAR & S0) ) } + TOP2 = { ~( (A2BAR & B2BAR & S3) | (A2BAR & ~B2BAR & S2) ) } + BOT2 = { ~( (~B2BAR & S1) | A2BAR | (B2BAR & S0) ) } + TOP1 = { ~( (A1BAR & B1BAR & S3) | (A1BAR & ~B1BAR & S2) ) } + BOT1 = { ~( (~B1BAR & S1) | A1BAR | (B1BAR & S0) ) } + TOP0 = { ~( (A0BAR & B0BAR & S3) | (A0BAR & ~B0BAR & S2) ) } + BOT0 = { ~( (~B0BAR & S1) | A0BAR | (B0BAR & S0) ) } + MBAR = { ~M } + + F3BAR = { (TOP3 ^ BOT3) ^ ~( ( CN & MBAR & TOP2 & TOP1 & TOP0) | + (BOT0 & MBAR & TOP2 & TOP1) | + (BOT1 & MBAR & TOP2) | + (BOT2 & MBAR) ) } + F2BAR = { (TOP2 ^ BOT2) ^ ~( ( CN & MBAR & TOP1 & TOP0) | + (BOT0 & MBAR & TOP1) | + (BOT1 & MBAR) ) } + F1BAR = { (TOP1 ^ BOT1) ^ ~( ( CN & MBAR & TOP0) | + (BOT0 & MBAR) ) } + F0BAR = { (TOP0 ^ BOT0) ^ ~( CN & MBAR) } + AEQUALB = { F3BAR & F2BAR & F1BAR & F0BAR } + PBAR = { ~( (M & F3BAR & F2BAR & F1BAR & F0BAR) | + (MBAR & TOP3 & TOP2 & TOP1 & TOP0) ) } + GBAR = { ~(MBAR & ((BOT0 & TOP3 & TOP2 & TOP1) | + (BOT1 & TOP3 & TOP2) | + (BOT2 & TOP3) | + BOT3) ) } + CN+4 = { ~GBAR | (~PBAR & CN) } UF881DLY PINDLY (7,0,14) DPWR DGND + F0BAR F1BAR F2BAR F3BAR PBAR GBAR CN+4 + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M CN + F0BAR_O F1BAR_O F2BAR_O F3BAR_O PBAR_O GBAR_O CN+4_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + NOTM = { M=='0 } + CARRY = { CHANGED(CN,0) } + MODE = { CHANGED(S3,0) | CHANGED(S2,0) | + CHANGED(S1,0) | CHANGED(S0,0) } + SUM = { S0=='1 & S1=='0 & S2=='0 & S3=='1 } + DIF = { S0=='0 & S1=='1 & S2=='1 & S3=='0 } + LOGSUM = { CHANGED(M,0) & SUM } + LOGDIF = { CHANGED(M,0) & DIF } + SUMNOTM = { SUM & NOTM } + DIFNOTM = { DIF & NOTM } + OPER3 = { (CHANGED(A3BAR,0) | CHANGED(B3BAR,0)) } + OPER2 = { (CHANGED(A2BAR,0) | CHANGED(B2BAR,0)) } + OPER1 = { (CHANGED(A1BAR,0) | CHANGED(B1BAR,0)) } + OPER0 = { (CHANGED(A0BAR,0) | CHANGED(B0BAR,0)) } + OPER = { OPER3 | OPER2 | OPER1 | OPER0 } + CHECK1 = { CN=='1 & M=='1 & SUM } + CHECK2 = { CN=='1 & M=='1 & S0=='0 & S1=='0 & S2=='1 & S3=='0 } + + PINDLY: + F3BAR_O = { + CASE ( + CARRY , DELAY(2.5NS,5.5NS, 9.0NS), + MODE & TRN_LH, DELAY(2.0NS,6.0NS,11.0NS), + MODE & TRN_HL, DELAY(3.0NS,6.5NS,11.0NS), + LOGSUM & TRN_LH, DELAY(3.0NS,7.0NS,10.5NS), + LOGSUM & TRN_HL, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_LH, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_HL, DELAY(3.0NS,6.0NS,10.5NS), + OPER3 & SUMNOTM & TRN_LH, DELAY(2.0NS,4.5NS, 8.5NS), + OPER3 & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS, 9.5NS), + OPER3 & DIFNOTM & TRN_LH, DELAY(2.0NS,5.0NS, 8.5NS), + OPER3 & DIFNOTM & TRN_HL, DELAY(3.0NS,6.0NS, 9.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,6.0NS,10.5NS), + OPER & M=='1 & TRN_HL, DELAY(2.5NS,5.5NS, 9.5NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.5NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.5NS,7.0NS,11.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.0NS,7.0NS,11.5NS), + OPER & DIFNOTM & TRN_HL, DELAY(3.5NS,7.5NS,11.5NS), + DELAY(3.5NS,7.5NS,11.5NS) + ) + } + F2BAR_O = { + CASE ( + CARRY , DELAY(2.5NS,5.5NS, 9.0NS), + MODE & TRN_LH, DELAY(2.0NS,6.0NS,11.0NS), + MODE & TRN_HL, DELAY(3.0NS,6.5NS,11.0NS), + LOGSUM & TRN_LH, DELAY(3.0NS,7.0NS,10.5NS), + LOGSUM & TRN_HL, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_LH, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_HL, DELAY(3.0NS,6.0NS,10.5NS), + OPER2 & SUMNOTM & TRN_LH, DELAY(2.0NS,4.5NS, 8.5NS), + OPER2 & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS, 9.5NS), + OPER2 & DIFNOTM & TRN_LH, DELAY(2.0NS,5.0NS, 8.5NS), + OPER2 & DIFNOTM & TRN_HL, DELAY(3.0NS,6.0NS, 9.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,6.0NS,10.5NS), + OPER & M=='1 & TRN_HL, DELAY(2.5NS,5.5NS, 9.5NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.5NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.5NS,7.0NS,11.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.0NS,7.0NS,11.5NS), + OPER & DIFNOTM & TRN_HL, DELAY(3.5NS,7.5NS,11.5NS), + DELAY(3.5NS,7.5NS,11.5NS) + ) + } + F1BAR_O = { + CASE ( + CARRY , DELAY(2.5NS,5.5NS, 9.0NS), + MODE & TRN_LH, DELAY(2.0NS,6.0NS,11.0NS), + MODE & TRN_HL, DELAY(3.0NS,6.5NS,11.0NS), + LOGSUM & TRN_LH, DELAY(3.0NS,7.0NS,10.5NS), + LOGSUM & TRN_HL, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_LH, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_HL, DELAY(3.0NS,6.0NS,10.5NS), + OPER1 & SUMNOTM & TRN_LH, DELAY(2.0NS,4.5NS, 8.5NS), + OPER1 & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS, 9.5NS), + OPER1 & DIFNOTM & TRN_LH, DELAY(2.0NS,5.0NS, 8.5NS), + OPER1 & DIFNOTM & TRN_HL, DELAY(3.0NS,6.0NS, 9.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,6.0NS,10.5NS), + OPER & M=='1 & TRN_HL, DELAY(2.5NS,5.5NS, 9.5NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.5NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.5NS,7.0NS,11.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.0NS,7.0NS,11.5NS), + OPER & DIFNOTM & TRN_HL, DELAY(3.5NS,7.5NS,11.5NS), + DELAY(3.5NS,7.5NS,11.5NS) + ) + } + F0BAR_O = { + CASE ( + CARRY , DELAY(2.5NS,5.5NS, 9.0NS), + MODE & TRN_LH, DELAY(2.0NS,6.0NS,11.0NS), + MODE & TRN_HL, DELAY(3.0NS,6.5NS,11.0NS), + LOGSUM & TRN_LH, DELAY(3.0NS,7.0NS,10.5NS), + LOGSUM & TRN_HL, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_LH, DELAY(3.0NS,6.5NS,10.5NS), + LOGDIF & TRN_HL, DELAY(3.0NS,6.0NS,10.5NS), + OPER0 & SUMNOTM & TRN_LH, DELAY(2.0NS,4.5NS, 8.5NS), + OPER0 & SUMNOTM & TRN_HL, DELAY(3.0NS,5.5NS, 9.5NS), + OPER0 & DIFNOTM & TRN_LH, DELAY(2.0NS,5.0NS, 8.5NS), + OPER0 & DIFNOTM & TRN_HL, DELAY(3.0NS,6.0NS, 9.5NS), + OPER & M=='1 & TRN_LH, DELAY(3.0NS,6.0NS,10.5NS), + OPER & M=='1 & TRN_HL, DELAY(2.5NS,5.5NS, 9.5NS), + OPER & SUMNOTM & TRN_LH, DELAY(3.0NS,6.5NS,11.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(3.5NS,7.0NS,11.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(3.0NS,7.0NS,11.5NS), + OPER & DIFNOTM & TRN_HL, DELAY(3.5NS,7.5NS,11.5NS), + DELAY(3.5NS,7.5NS,11.5NS) + ) + } + PBAR_O = { + CASE ( + MODE & TRN_LH, DELAY(2.0NS, 7.5NS,14.0NS), + MODE & TRN_HL, DELAY(3.5NS, 7.0NS,12.0NS), + CHECK1 & TRN_LH, DELAY(6.0NS, 9.5NS,14.5NS), + CHECK1 & TRN_HL, DELAY(4.0NS, 7.0NS,12.0NS), + CHECK2 & TRN_LH, DELAY(6.0NS,10.0NS,14.5NS), + CHECK2 & TRN_HL, DELAY(4.0NS, 7.5NS,12.0NS), + OPER & SUMNOTM & TRN_LH, DELAY(2.0NS, 4.5NS, 8.5NS), + OPER & SUMNOTM & TRN_HL, DELAY(2.0NS, 5.0NS, 8.5NS), + OPER & DIFNOTM & TRN_LH, DELAY(2.0NS, 5.0NS, 9.5NS), + OPER & DIFNOTM & TRN_HL, DELAY(2.0NS, 5.5NS, 9.5NS), + DELAY(6.0NS,10.0NS,14.5NS) + ) + } + GBAR_O = { + CASE ( + OPER & SUMNOTM | MODE , DELAY(2.5NS, 5.0NS, 9.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(2.5NS, 5.0NS, 9.5NS), + OPER & DIFNOTM & TRN_HL, DELAY(2.5NS, 5.5NS, 9.5NS), + DELAY(2.5NS, 5.5NS, 9.5NS) + ) + } + CN+4_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.0NS, 5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(2.0NS, 6.5NS, 9.0NS), + MODE & TRN_LH, DELAY(4.0NS,10.0NS,14.0NS), + MODE & TRN_HL, DELAY(4.0NS, 7.5NS,11.0NS), + CHECK1 & TRN_LH, DELAY(4.5NS, 9.0NS,14.0NS), + CHECK1 & TRN_HL, DELAY(4.5NS,10.0NS,14.0NS), + CHECK2 & TRN_LH, DELAY(4.5NS, 9.0NS,14.0NS), + CHECK2 & TRN_HL, DELAY(4.5NS,10.5NS,15.0NS), + OPER & SUMNOTM & TRN_LH, DELAY(5.0NS,10.0NS,14.0NS), + OPER & SUMNOTM & TRN_HL, DELAY(5.0NS, 8.5NS,14.0NS), + OPER & DIFNOTM & TRN_LH, DELAY(5.0NS,10.5NS,15.0NS), + OPER & DIFNOTM & TRN_HL, DELAY(5.0NS, 9.0NS,14.0NS), + DELAY(5.0NS,10.5NS,15.0NS) + ) + } UF881DLY_OC PINDLY (1,0,13) DPWR DGND + AEQUALB + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M + AEQUALB_O + IO_F_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + LOGIC = { CHANGED(M,0) } + MODE = { CHANGED(S3,0) | CHANGED(S2,0) | CHANGED(S1,0) | CHANGED(S0,0) } + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + DIF = { OPER & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + AEQUALB_O = { + CASE ( + MODE & TRN_LH, DELAY(11.0NS,16.5NS,24.0NS), + MODE & TRN_HL, DELAY( 5.0NS, 9.0NS,14.0NS), + LOGIC & TRN_LH, DELAY(12.0NS,16.5NS,24.0NS), + LOGIC & TRN_HL, DELAY( 5.0NS, 9.5NS,13.5NS), + DIF & NOTM & TRN_LH, DELAY( 8.0NS,14.5NS,22.0NS), + DIF & NOTM & TRN_HL, DELAY( 6.0NS, 9.0NS,14.0NS), + DELAY(12.0NS,16.5NS,24.0NS) + ) + } .ENDS *$ *-------- * 74F882 LOOK-AHEAD CARRY GENERATOR * * FAST TTL LOGIC SERIES, 1990, PHILIPS SEMICONDUCTORS * JLS 9-18-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74F882 CN_I + P0BAR_I P1BAR_I P2BAR_I P3BAR_I P4BAR_I P5BAR_I P6BAR_I P7BAR_I + G0BAR_I G1BAR_I G2BAR_I G3BAR_I G4BAR_I G5BAR_I G6BAR_I G7BAR_I + CN+8_O CN+16_O CN+24_O CN+32_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UF882LOG LOGICEXP (17,5) DPWR DGND + P0BAR_I P1BAR_I P2BAR_I P3BAR_I P4BAR_I P5BAR_I P6BAR_I P7BAR_I + G0BAR_I G1BAR_I G2BAR_I G3BAR_I G4BAR_I G5BAR_I G6BAR_I G7BAR_I CN_I + CN CN+8 CN+16 CN+24 CN+32 + D0_GATE IO_F + IO_LEVEL={IO_LEVEL} + + LOGIC: + P0BAR = { P0BAR_I } + P1BAR = { P1BAR_I } + P2BAR = { P2BAR_I } + P3BAR = { P3BAR_I } + P4BAR = { P4BAR_I } + P5BAR = { P5BAR_I } + P6BAR = { P6BAR_I } + P7BAR = { P7BAR_I } + G0BAR = { G0BAR_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3BAR = { G3BAR_I } + G4BAR = { G4BAR_I } + G5BAR = { G5BAR_I } + G6BAR = { G6BAR_I } + G7BAR = { G7BAR_I } + CN = { CN_I } + + STEP08 = { G0BAR & G1BAR } + W08C = { ~CN & STEP08 } + W080 = { P0BAR & STEP08 } + W081 = { P1BAR & G1BAR } + STEP16 = { G2BAR & G3BAR } + W16C = { W08C & STEP16 } + W160 = { W080 & STEP16 } + W161 = { W081 & STEP16 } + W162 = { P2BAR & STEP16 } + W163 = { P3BAR & G3BAR } + STEP24 = { G4BAR & G5BAR } + W24C = { W16C & STEP24 } + W240 = { W160 & STEP24 } + W241 = { W161 & STEP24 } + W242 = { W162 & STEP24 } + W243 = { W163 & STEP24 } + W244 = { P4BAR & STEP24 } + W245 = { P5BAR & G5BAR } + STEP32 = { G6BAR & G7BAR } + W32C = { W24C & STEP32 } + W320 = { W240 & STEP32 } + W321 = { W241 & STEP32 } + W322 = { W242 & STEP32 } + W323 = { W243 & STEP32 } + W324 = { W244 & STEP32 } + W325 = { W245 & STEP32 } + W326 = { P6BAR & STEP32 } + W327 = { P7BAR & G7BAR } + + CN+8 = { ~(W08C | W080 | W081) } + CN+16 = { ~(W16C | W160 | W161 | W162 | W163) } + CN+24 = { ~(W24C | W240 | W241 | W242 | W243 | W244 | W245) } + CN+32 = { ~(W32C | W320 | W321 | W322 | W323 | W324 | W325 | W326 | W327) } * UF882DLY PINDLY (4,0,1) DPWR DGND + CN+8 CN+16 CN+24 CN+32 + CN + CN+8_O CN+16_O CN+24_O CN+32_O + IO_F + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + + PINDLY: + CN+8_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + TRN_LH, DELAY(1.0NS,3.5NS, 7.0NS), + TRN_HL, DELAY(1.0NS,2.5NS, 6.0NS), + DELAY(3.0NS,5.5NS,10NS) + ) + } + CN+16_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + TRN_LH, DELAY(2.0NS,4.0NS, 8.0NS), + TRN_HL, DELAY(1.0NS,2.5NS, 7.0NS), + DELAY(3.0NS,5.5NS,10NS) + ) + } + CN+24_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + DELAY(1.5NS,4.0NS, 8.5NS) + ) + } + CN+32_O = { + CASE ( + CARRY & TRN_LH, DELAY(2.0NS,5.0NS, 9.0NS), + CARRY & TRN_HL, DELAY(3.0NS,5.5NS,10.0NS), + DELAY(1.0NS,4.5NS, 8.5NS) + ) + } * .ENDS * *$