* Library of 74LS Family Digital Models * * Copyright OrCAD, Inc. 1998 All Rights Reserved. * * * $Revision: 1.4 $ * $Author: RPEREZ $ * $Date: 17 Apr 1998 09:57:46 $ * * *$ *--------- * 74LS00 Quadruple 2-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS00 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS00 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS00 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *--------- * 74LS01 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS01 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS01 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS01 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *$ *--------- * 74LS02 Quadruple 2-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS02 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_LS02 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS02 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *--------- * 74LS03 Quadruple 2-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS03 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS03 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS03 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *$ *--------- * 74LS04 Hex Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS04 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_LS04 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS04 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *--------- * 74LS05 Hex Inverters with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS05 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 inv DPWR DGND + A Y + D_LS05 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS05 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *$ *--------- * 74LS08 Quadruple 2-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS08 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_LS08 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS08 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=10ns tphlmx=20ns + ) *$ *--------- * 74LS09 Quadruple 2-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS09 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(2) DPWR DGND + A B Y + D_LS09 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS09 ugate ( + tplhty=20ns tplhmx=35ns + tphlty=17ns tphlmx=35ns + ) *$ *--------- * 74LS10 Triple 3-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS10 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_LS10 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS10 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *--------- * 74LS11 Triple 3-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS11 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_LS11 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS11 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=10ns tphlmx=20ns + ) *$ *--------- * 74LS12 Triple 3-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS12 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(3) DPWR DGND + A B C Y + D_LS12 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS12 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *$ *--------- * 74LS13 Dual 4-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS13 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled in the AtoD interface * U1 nand(4) DPWR DGND + A B C D Y + D_LS13 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS13 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=18ns tphlmx=27ns + ) *$ *--------- * 74LS14 Hex Schmitt-Trigger Inverters * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/23/89 Update interface and model names * .subckt 74LS14 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface * U1 inv DPWR DGND + A Y + D_LS14 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS14 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *$ *--------- * 74LS15 Triple 3-input Positive-And Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS15 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(3) DPWR DGND + A B C Y + D_LS15 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS15 ugate ( + tplhty=20ns tplhmx=35ns + tphlty=17ns tphlmx=35ns + ) *$ *------------------------------------------------------------------------- * 74LS18 Schmitt-Trigger 4-input Positive-Nand Gates with Totem-Pole Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS18 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters * Hysteresis is modeled in the AtoD interface * U1 nand(4) DPWR DGND + A B C D Y + D_LS18 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS18 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=37ns tphlmx=55ns + ) *$ *------------------------------------------------------------------------- * 74LS19 Schmitt-Trigger Inverters with Totem-Pole Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS19 A Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple inverters. * Hysteresis is modeled in the AtoD interface. * U1 inv DPWR DGND + A Y + D_LS19 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS19 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=18ns tphlmx=30ns + ) *$ *--------- * 74LS20 Dual 4-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS20 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_LS20 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS20 ugate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *--------- * 74LS21 Dual 4-input Positive-And Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS21 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 and(4) DPWR DGND + A B C D Y + D_LS21 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS21 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=10ns tphlmx=20ns + ) *$ *--------- * 74LS22 Dual 4-input Positive-Nand Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS22 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_LS22 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS22 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *$ *------------------------------------------------------------------------- * 74LS24 Schmitt-Trigger 2-input Positive-Nand Gates w/ Totem-Pole Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS24 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled in the AtoD interface. * U1 nand(2) DPWR DGND + A B Y + D_LS24 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS24 ugate ( + tplhty=13ns tplhmx=20ns + tphlty=25ns tphlmx=40ns + ) *$ *--------- * 74LS26 High-Voltage Interface Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS26 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS26 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS26 ugate ( + tplhty=17ns tplhmx=32ns + tphlty=15ns tphlmx=28ns + ) *$ *--------- * 74LS27 Triple 3-input Positive-Nor Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS27 A B C Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(3) DPWR DGND + A B C Y + D_LS27 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS27 ugate ( + tplhty=10ns tplhmx=15ns + tphlty=10ns tphlmx=15ns + ) *$ *--------- * 74LS28 Quadruple 2-input Positive-Nor Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS28 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_LS28 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS28 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *--------- * 74LS30 8-input Positive-Nand Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS30 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(8) DPWR DGND + A B C D E F G H Y + D_LS30 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS30 ugate ( + tplhty=8ns tplhmx=15ns + tphlty=13ns tphlmx=20ns + ) *$ *------------------------------------------------------------------------- * 74LS31 Delay Elements * * The TTL Data Book, Vol 2, 1985, TI * tdn 8/10/89 Update interface and model names * .subckt 74LS31 1A 2A 3A 3B 1Y 2Y 3Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: In this IC, there are 2 inverting, & 2 non-inverting delay gates, and * 2 2-input NAND gates. However, the model here only contains 1 gate per type. * If more gates are needed, please call the SUBCKT twice. * U1 inv DPWR DGND + 1A 1Y + D_LS31_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf DPWR DGND + 2A 2Y + D_LS31_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 nand(2) DPWR DGND + 3A 3B 3Y + D_LS31_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS31_1 ugate ( + tplhmn=22ns tplhty=32ns + tplhmx=65ns tphlmn=13ns + tphlty=23ns tphlmx=45ns + ) .model D_LS31_2 ugate ( + tplhmn=31ns tplhty=45ns + tplhmx=80ns tphlmn=30ns + tphlty=48ns tphlmx=95ns + ) .model D_LS31_3 ugate ( + tplhmn=2ns tplhty=6ns + tplhmx=15ns tphlmn=2ns + tphlty=6ns tphlmx=15ns + ) *$ *--------- * 74LS32 Quadruple 2-input Positive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS32 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 or(2) DPWR DGND + A B Y + D_LS32 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS32 ugate ( + tplhty=14ns tplhmx=22ns + tphlty=14ns tphlmx=22ns + ) *$ *--------- * 74LS33 Quadruple 2-input Positive-Nor Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS33 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nor(2) DPWR DGND + A B Y + D_LS33 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS33 ugate ( + tplhty=20ns tplhmx=32ns + tphlty=18ns tphlmx=28ns + ) *$ *--------- * 74LS37 Quadruple 2-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS37 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS37 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS37 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *--------- * 74LS38 Quadruple 2-input Positive-Nand Buffers w/ Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS38 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(2) DPWR DGND + A B Y + D_LS38 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS38 ugate ( + tplhty=20ns tplhmx=32ns + tphlty=18ns tphlmx=28ns + ) *$ *--------- * 74LS40 Dual 4-input Positive-Nand Buffers * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/26/89 Update interface and model names * .subckt 74LS40 A B C D Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nand(4) DPWR DGND + A B C D Y + D_LS40 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS40 ugate ( + tplhty=12ns tplhmx=24ns + tphlty=12ns tphlmx=24ns + ) *$ *-------- * 74LS42 DECODER BCD-DECIMAL 4-10 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS42 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS42LOG LOGICEXP (4,14) DPWR DGND + A_I B_I C_I D_I + A B C D + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(DBAR & CBAR & BBAR & ABAR ) } + Y1 = { ~(DBAR & CBAR & BBAR & A ) } + Y2 = { ~(DBAR & CBAR & B & ABAR ) } + Y3 = { ~(DBAR & CBAR & B & A ) } + Y4 = { ~(DBAR & C & BBAR & ABAR ) } + Y5 = { ~(DBAR & C & BBAR & A ) } + Y6 = { ~(DBAR & C & B & ABAR ) } + Y7 = { ~(DBAR & C & B & A ) } + Y8 = { ~(D & CBAR & BBAR & ABAR ) } + Y9 = { ~(D & CBAR & BBAR & A ) } * ULS42DLY PINDLY (10,0,4) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + A B C D + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC = { CHANGED(C,0) } + ADDRD = { CHANGED(D,0) } + + PINDLY: + Y0_O = { DELAY(-1,15NS,25NS) } + Y1_O = { + CASE ( + ADDRA , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y2_O = { + CASE ( + ADDRB , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y3_O = { + CASE ( + ADDRA | ADDRB , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y4_O = { + CASE ( + ADDRC , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y5_O = { + CASE ( + ADDRA | ADDRC , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y6_O = { + CASE ( + ADDRB | ADDRC , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y7_O = { + CASE ( + ADDRA | ADDRB | ADDRC , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y8_O = { + CASE ( + ADDRD , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } + Y9_O = { + CASE ( + ADDRA | ADDRD , DELAY(-1,20NS,30NS), + DELAY(-1,15NS,25NS) + ) + } * .ENDS * *$ *--------- * 74LS47 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS47 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} * ULS47LOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { (BBI & DBI) | (ALT & CBI) | (ABI & BLT & CLT & DLT) } + OUTB = { (BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI) } + OUTC = { (CBI & DBI) | (ALT & BBI & CLT) } + OUTD = { (ABI & BLT & CLT) | (ALT & BLT & CBI) | (ABI & BBI & CBI) } + OUTE = { ABI | (BLT & CBI) } + OUTF = { (ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT) } + OUTG = { (ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR) } * ULS47DLY_OC PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } * .ENDS * *$ *-------- * 74LS48 DECODER/DRIVER BCD-7 SEGMENT WITH INTERNAL PULLUPS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS48 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} * ULS48LOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { ~((BBI & DBI) | (ALT & CBI) | (ABI & BLT & CLT & DLT)) } + OUTB = { ~((BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI)) } + OUTC = { ~((CBI & DBI) | (ALT & BBI & CLT)) } + OUTD = { ~((ABI & BLT & CLT) | (ALT & BLT & CBI) | (ABI & BBI & CBI)) } + OUTE = { ~( ABI | (BLT & CBI)) } + OUTF = { ~((ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT)) } + OUTG = { ~((ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR)) } * ULS48DLY PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } * .ENDS * *$ *-------- * 74LS49 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS49 INA_I INB_I INC_I IND_I BIBAR_I + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS49LOG LOGICEXP (5,7) DPWR DGND + INA_I INB_I INC_I IND_I BIBAR_I + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + BIBAR = { BIBAR_I } + + ABAR = { ~INA } + BBAR = { ~INB } + CBAR = { ~INC } + DBAR = { ~IND } + ABI = { ~(ABAR & BIBAR) } + BBI = { ~(BBAR & BIBAR) } + CBI = { ~(CBAR & BIBAR) } + DBI = { ~(DBAR & BIBAR) } + + OUTA = { ~((BBI & DBI) | (ABAR & CBI) | (ABI & BBAR & CBAR & DBAR)) } + OUTB = { ~((BBI & DBI) | (ABI & BBAR & CBI) | (ABAR & BBI & CBI)) } + OUTC = { ~((CBI & DBI) | (ABAR & BBI & CBAR)) } + OUTD = { ~((ABI & BBAR & CBAR) | (ABAR & BBAR & CBI) | + (ABI & BBI & CBI)) } + OUTE = { ~( ABI | (BBAR & CBI)) } + OUTF = { ~((ABI & BBI) | (BBI & CBAR) | (ABI & CBAR & DBAR)) } + OUTG = { ~((ABI & BBI & CBI) | (BBAR & CBAR & DBAR)) } * ULS49DLY_OC PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } * .ENDS * *$ *--------- * 74LS51 And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names * .subckt 74LS51 1A 1B 1C 1D 1E 1F 1Y 2A 2B 2C 2D 2Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,2) DPWR DGND + 1A 1B 1C 1D 1E 1F 1Y + D_LS51 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 aoi(2,2) DPWR DGND + 2A 2B 2C 2D 2Y + D_LS51 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS51 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=12.5ns tphlmx=20ns + ) *$ *--------- * 74LS54 4-wide And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names * .subckt 74LS54 A B C D E F G H I J Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(3,4) DPWR DGND + A B $D_HI + C D E + F G H + I J $D_HI + Y + D_LS54 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS54 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=12.5ns tphlmx=20ns + ) *$ *--------- * 74LS55 2-wide 4-input And-Or-Invert Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/27/89 Update interface and model names * .subckt 74LS55 A B C D E F G H Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 aoi(4,2) DPWR DGND + A B C D E F G H Y + D_LS55 IO_L MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS55 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=12.5ns tphlmx=20ns + ) *$ *------------------------------------------------------------------------- * 74LS56 Frequency Dividers(5 to 1, 5 to 1, and 10 to 1) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/10/89 Update interface and model names * .subckt 74LS56 CLR CLKA CLKB QA QB QC + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + CLKA CLKB CLKA_BUF CLKB_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + CLR CLRB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1 CLRB CLKA_BUF QAD DPWR DGND 56DIV5 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLRB CLKB_BUF QBD DPWR DGND 56DIV5 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 CLRB QB1 QC DPWR DGND 56DIV2 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + QBD QBD QB QB1 + D_LS56_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 buf DPWR DGND + QAD QA + D_LS56_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt 56DIV5 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(2) DPWR DGND + $D_HI CLR CLK + QB Q1 QB Q1 + Q1 Q2 $D_NC $D_NC + D_LS56_3 IO_LS MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + $D_HI CLR CLK EN EN Q QB + D_LS56_4 IO_LS MNTYMXDLY={MNTYMXDLY} U3 ao(2,2) DPWR DGND + Q1 Q2 Q $D_HI EN + D0_GATE IO_LS .ends * .subckt 56DIV2 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(1) DPWR DGND + $D_HI CLR CLK $D_HI $D_HI Q $D_NC + D_LS56_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS56_1 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) .model D_LS56_2 ugate ( + tplhty=9ns tplhmx=10ns + tphlty=5ns tphlmx=5ns + ) .model D_LS56_3 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=12ns + tppcqhlmx=25ns tpclkqhlty=1ns + tpclkqhlmx=1ns tpclkqlhty=1ns + tpclkqlhmx=1ns + ) .model D_LS56_4 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=12ns + tppcqhlmx=25ns tpclkqlhty=3ns + tpclkqlhmx=10ns tpclkqhlty=9ns + tpclkqhlmx=20ns + ) .model D_LS56_5 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=30ns tpclkqlhty=4ns + tpclkqlhmx=5ns tpclkqhlty=10ns + tpclkqhlmx=10ns + ) *$ *------------------------------------------------------------------------- * 74LS57 Frequency Dividers(6 to 1, 5 to 1, and 10 to 1) * * The TTL Data Book, Vol 2, 1985, TI * tdn 08/10/89 Update interface and model names * .subckt 74LS57 CLR CLKA CLKB QA QB QC + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + CLKA CLKB CLKA_BUF CLKB_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + CLR CLRB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1 CLRB CLKA_BUF QA DPWR DGND 57DIV6 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 CLRB CLKB_BUF QBD DPWR DGND 57DIV5 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 CLRB QB1 QC DPWR DGND 57DIV2 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + QBD QBD QB QB1 + D_LS57_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt 57DIV5 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(2) DPWR DGND + $D_HI CLR CLK + QB Q1 QB Q1 + Q1 Q2 $D_NC $D_NC + D_LS57_2 IO_LS MNTYMXDLY={MNTYMXDLY} UE2 jkff(1) DPWR DGND + $D_HI CLR CLK EN EN Q QB + D_LS57_3 IO_LS MNTYMXDLY={MNTYMXDLY} U3 ao(2,2) DPWR DGND + Q1 Q2 Q $D_HI EN + D0_GATE IO_LS .ends * .subckt 57DIV2 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(1) DPWR DGND + $D_HI CLR CLK $D_HI $D_HI Q $D_NC + D_LS57_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt 57DIV6 CLR CLK Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UE1 jkff(2) DPWR DGND + $D_HI CLR CLK + $D_HI J2 $D_HI J2 + Q1 Q2 $D_NC $D_NC + D_LS57_2 IO_LS MNTYMXDLY={MNTYMXDLY} UE3 jkff(1) DPWR DGND + $D_HI CLR CLK EN EN Q QB + D_LS57_5 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U1 ao(2,2) DPWR DGND + QB Q2 Q1 $D_HI J2 + D0_GATE IO_LS U2 ao(2,2) DPWR DGND + Q1 Q2 QB Q2 EN + D0_GATE IO_LS .ends * .model D_LS57_1 ugate ( + tplhty=5ns tplhmx=5ns + tphlty=5ns tphlmx=5ns + ) .model D_LS57_2 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=25ns tpclkqhlty=1ns + tpclkqhlmx=1ns tpclkqlhty=1ns + tpclkqlhmx=1ns + ) .model D_LS57_3 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=12ns + tppcqhlmx=25ns tpclkqlhty=3ns + tpclkqlhmx=10ns tpclkqhlty=9ns + tpclkqhlmx=20ns + ) .model D_LS57_4 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=30ns tpclkqlhty=4ns + tpclkqlhmx=5ns tpclkqhlty=10ns + tpclkqhlmx=10ns + ) .model D_LS57_5 ueff ( + twclkhmn=30ns twclklmn=30ns + tsupcclkhmn=25ns tppcqhlty=17ns + tppcqhlmx=30ns tpclkqlhty=14ns + tpclkqlhmx=25ns tpclkqhlty=18ns + tpclkqhlmx=30ns + ) *$ *------------------------------------------------------------------------- * 74LS68 COUNTER DECADE 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-3-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS68 1CLRBAR_I 1CLKA_I 1CLKB_I 1QA_O 1QB_O 1QC_O 1QD_O + 2CLRBAR_I 2CLK_I 2QA_O 2QB_O 2QC_O 2QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1CLKA $D_HI $D_HI 1QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1CLOCK2 $D_HI $D_HI 1QB 1QBBAR + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1QB $D_HI $D_HI 1QC 1QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1CLOCK4 $D_HI $D_HI 1QD 1QDBAR + D0_EFF IO_LS U5 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2CLK $D_HI $D_HI 2QA $D_NC + D0_EFF IO_LS U6 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2CLOCK2 $D_HI $D_HI 2QB 2QBBAR + D0_EFF IO_LS U7 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2QB $D_HI $D_HI 2QC 2QCBAR + D0_EFF IO_LS U8 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2CLOCK4 $D_HI $D_HI 2QD 2QDBAR + D0_EFF IO_LS * ULS68LOG LOGICEXP (12,9) DPWR DGND + 1CLRBAR_I 1CLKA_I 1CLKB_I 1QBBAR 1QCBAR 1QDBAR + 2CLRBAR_I 2CLK_I 2QA 2QBBAR 2QCBAR 2QDBAR + 1CLRBAR 1CLKA 1CLKB 1CLOCK2 1CLOCK4 2CLRBAR 2CLK 2CLOCK2 2CLOCK4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + 1CLRBAR = { 1CLRBAR_I } + 1CLKA = { 1CLKA_I } + 1CLKB = { 1CLKB_I } + 1CLOCK2 = { 1CLKB & 1QDBAR } + 1CLOCK4 = { ~( (1QBBAR & 1QDBAR) | (1QCBAR & 1QDBAR) ) & 1CLKB } + 2CLRBAR = { 2CLRBAR_I } + 2CLK = { 2CLK_I } + 2CLOCK2 = { 2QA & 2QDBAR } + 2CLOCK4 = { ~( (2QBBAR & 2QDBAR) | (2QCBAR & 2QDBAR) ) & 2QA } * ULS68DLY PINDLY (8,0,5) DPWR DGND + 1QA 1QB 1QC 1QD 2QA 2QB 2QC 2QD + 1CLRBAR 1CLKA 1CLKB 2CLRBAR 2CLK + 1QA_O 1QB_O 1QC_O 1QD_O 2QA_O 2QB_O 2QC_O 2QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED1A = { CHANGED_HL(1CLKA,0) } + CLOCKED1B = { CHANGED_HL(1CLKB,0) } + CLOCKED2 = { CHANGED_HL(2CLK,0) } + CLEAR1 = { CHANGED_HL(1CLRBAR,0) } + CLEAR2 = { CHANGED_HL(2CLRBAR,0) } + + PINDLY: + 1QA_O = { + CASE ( + TRN_LH, DELAY(-1, 7NS,11NS), + CLOCKED1A & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,20NS,30NS) + ) + } + 1QB_O = { + CASE ( + TRN_LH, DELAY(-1, 8NS,12NS), + CLOCKED1B & TRN_HL, DELAY(-1,12NS,18NS), + DELAY(-1,20NS,30NS) + ) + } + 1QC_O = { + CASE ( + TRN_LH, DELAY(-1,15NS,23NS), + CLEAR1, DELAY(-1,20NS,30NS), + DELAY(-1,21NS,32NS) + ) + } + 1QD_O = { + CASE ( + TRN_LH, DELAY(-1, 8NS,12NS), + CLOCKED1B & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,20NS,30NS) + ) + } + 2QA_O = { + CASE ( + TRN_LH, DELAY(-1, 7NS,11NS), + CLOCKED2 & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,20NS,30NS) + ) + } + 2QB_O 2QD_O = { + CASE ( + TRN_LH, DELAY(-1,16NS,24NS), + CLOCKED2 & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,20NS,30NS) + ) + } + 2QC_O = { + CASE ( + CLEAR2, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,23NS,35NS), + DELAY(-1,27NS,40NS) + ) + } + + FREQ: + NODE = 1CLKA + MAXFREQ = 50MEGHZ + FREQ: + NODE = 1CLKB + MAXFREQ = 20MEGHZ + FREQ: + NODE = 2CLK + MAXFREQ = 40MEGHZ + WIDTH: + NODE = 1CLKA + MIN_LO = 10NS + MIN_HI = 10NS + WIDTH: + NODE = 1CLKB + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = 2CLK + MIN_LO = 13NS + MIN_HI = 13NS + WIDTH: + NODE = 1CLRBAR + MIN_LO = 15NS + WIDTH: + NODE = 2CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(1) = 1CLRBAR + CLOCK HL = 1CLKA + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(1) = 1CLRBAR + CLOCK HL = 1CLKB + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(1) = 2CLRBAR + CLOCK HL = 2CLK + RELEASETIME_LH = 25NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS69 COUNTER BINARY 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-6-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS69 1CLRBAR_I 1CLKA_I 1CLKB_I 1QA_O 1QB_O 1QC_O 1QD_O + 2CLRBAR_I 2CLK_I 2QA_O 2QB_O 2QC_O 2QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1CLKA $D_HI $D_HI 1QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1CLKB $D_HI $D_HI 1QB $D_NC + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1QB $D_HI $D_HI 1QC $D_NC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + $D_HI 1CLRBAR 1QC $D_HI $D_HI 1QD $D_NC + D0_EFF IO_LS U5 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2CLK $D_HI $D_HI 2QA $D_NC + D0_EFF IO_LS U6 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2QA $D_HI $D_HI 2QB $D_NC + D0_EFF IO_LS U7 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2QB $D_HI $D_HI 2QC $D_NC + D0_EFF IO_LS U8 JKFF(1) DPWR DGND + $D_HI 2CLRBAR 2QC $D_HI $D_HI 2QD $D_NC + D0_EFF IO_LS U9 BUFA(5) DPWR DGND + 1CLRBAR_I 1CLKA_I 1CLKB_I 2CLRBAR_I 2CLK_I + 1CLRBAR 1CLKA 1CLKB 2CLRBAR 2CLK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * ULS69DLY PINDLY (8,0,5) DPWR DGND + 1QA 1QB 1QC 1QD 2QA 2QB 2QC 2QD + 1CLRBAR 1CLKA 1CLKB 2CLRBAR 2CLK + 1QA_O 1QB_O 1QC_O 1QD_O 2QA_O 2QB_O 2QC_O 2QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED1A = { CHANGED_HL(1CLKA,0) } + CLOCKED1B = { CHANGED_HL(1CLKB,0) } + CLOCKED2 = { CHANGED_HL(2CLK,0) } + CLEARED1 = { CHANGED_HL(1CLRBAR,0) } + CLEARED2 = { CHANGED_HL(2CLRBAR,0) } + + PINDLY: + 1QA_O = { + CASE ( + TRN_LH, DELAY(-1, 7NS,11NS), + CLOCKED1A & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,20NS,30NS) + ) + } + 1QB_O = { + CASE ( + TRN_LH, DELAY(-1, 7NS,11NS), + CLOCKED1B & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,20NS,30NS) + ) + } + 1QC_O = { + CASE ( + TRN_LH, DELAY(-1,16NS,24NS), + CLEARED1, DELAY(-1,20NS,30NS), + DELAY(-1,21NS,32NS) + ) + } + 1QD_O = { + CASE ( + CLEARED1, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,25NS,38NS), + DELAY(-1,30NS,45NS) + ) + } + 2QA_O = { + CASE ( + TRN_LH, DELAY(-1, 7NS,11NS), + CLOCKED2 & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,20NS,30NS) + ) + } + 2QB_O = { + CASE ( + TRN_LH, DELAY(-1,14NS,21NS), + CLOCKED2 & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,20NS,30NS) + ) + } + 2QC_O = { + CASE ( + CLEARED2, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,23NS,35NS), + DELAY(-1,27NS,40NS) + ) + } + 2QD_O = { + CASE ( + CLEARED2, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,32NS,48NS), + DELAY(-1,36NS,54NS) + ) + } + + FREQ: + NODE = 1CLKA + MAXFREQ = 50MEGHZ + FREQ: + NODE = 1CLKB + MAXFREQ = 25MEGHZ + FREQ: + NODE = 2CLK + MAXFREQ = 50MEGHZ + WIDTH: + NODE = 1CLKA + MIN_LO = 10NS + MIN_HI = 10NS + WIDTH: + NODE = 1CLKB + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = 2CLK + MIN_LO = 10NS + MIN_HI = 10NS + WIDTH: + NODE = 1CLRBAR + MIN_LO = 15NS + WIDTH: + NODE = 2CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(1) = 1CLRBAR + CLOCK HL = 1CLKA + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(1) = 1CLRBAR + CLOCK HL = 1CLKB + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(1) = 2CLRBAR + CLOCK HL = 2CLK + RELEASETIME_LH = 25NS * .ENDS * *$ *--------- * 74LS73A Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS73A CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CLRBAR CLK J K Q QBAR + D_LS73A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS73A ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=20ns tsudclkty=20ns + ) *$ *--------- * 74LS74 Dual D-Type Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS74A 1CLRBAR 1D 1CLK 1PREBAR 1Q 1QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UFF1 dff(1) DPWR DGND + 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR + D_LS74 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS74 ueff ( + twpclmn=25ns twclkhmn=25ns + tsudclkmn=20ns thdclkmn=5ns + tppcqlhmx=25ns tppcqlhty=13ns + tppcqhlmx=40ns tppcqhlty=25ns + tpclkqlhty=13ns tpclkqlhmx=25ns + tpclkqhlty=25ns tpclkqhlmx=40ns + ) *$ *--------- * 74LS75 4-bit bistable latches (dual 2-bit common clock) * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS75 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + 1D 2D C 1D_BUF 2D_BUF C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U12 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF 1Q 2Q $D_NC $D_NC + D_LS75_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12B dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D_BUF 2D_BUF $D_NC $D_NC 1QBAR 2QBAR + D_LS75_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS75_1 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=15ns + tpgqlhmx=27ns tpgqhlty=14ns + tpgqhlmx=25ns tpdqlhty=15ns + tpdqlhmx=27ns tpdqhlty=9ns + tpdqhlmx=17ns + ) .model D_LS75_2 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=16ns + tpgqlhmx=30ns tpgqhlty=7ns + tpgqhlmx=15ns tpdqlhty=12ns + tpdqlhmx=20ns tpdqhlty=7ns + tpdqhlmx=15ns + ) *$ *--------- * 74LS76A Dual J-K Flip-Flops with Preset and Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS76A CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 *--NOTE-- * These Flip-Flops are negative-edge-triggered * U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_LS76 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS76 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmn=20ns twpclmn=20ns + tsudclkmn=20ns + ) *$ *--------- * 74LS77 4-bit bistable latches * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS77 1D 2D C 1Q 2Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF buf DPWR DGND + C C_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 dltch(2) DPWR DGND + $D_HI $D_HI C_BUF 1D 2D 1Q 2Q $D_NC $D_NC + D_LS77 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS77 ugff ( + twghmx=20ns tsudgmx=20ns + thdgmx=5ns tpgqlhty=10ns + tpgqlhmx=18ns tpgqhlty=10ns + tpgqhlmx=18ns tpdqlhty=11ns + tpdqlhmx=19ns tpdqhlty=9ns + tpdqhlmx=17ns + ) *$ *--------- * 74LS78A Dual J-K Flip-Flops with Preset, Common Clear and Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/28/89 Update interface and model names * .subckt 74LS78A CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_LS78 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_LS78 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS78 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=20ns twpclty=20ns + tsudclkmx=20ns tsudclkty=20ns + ) * *$ *--------- * 74LS83A 4-BIT BINARY FULL ADDERS WITH FAST CARRY * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/26/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS83A C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I C4_O + SUM1_O SUM2_O SUM3_O SUM4_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS83ALOG LOGICEXP(9,14) DPWR DGND + C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I + C0 A1 A2 A3 A4 B1 B2 B3 B4 C4 SUM1 SUM2 SUM3 SUM4 + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + C0 = { C0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + B1 = { B1_I } + B2 = { B2_I } + B3 = { B3_I } + B4 = { B4_I } + + NAND4 = { ~(A4 & B4) } + NAND3 = { ~(A3 & B3) } + NAND2 = { ~(A2 & B2) } + NAND1 = { ~(A1 & B1) } + NOR4 = { ~(A4 | B4) } + NOR3 = { ~(A3 | B3) } + NOR2 = { ~(A2 | B2) } + NOR1 = { ~(A1 | B1) } + C0BAR = { ~C0 } + + SUM1 = { (NAND1 & ~NOR1) ^ C0 } + SUM2 = { (NAND2 & ~NOR2) ^ (~(NOR1 | (NAND1 & C0BAR))) } + SUM3 = { (NAND3 & ~NOR3) ^ (~(NOR2 | (NOR1 & NAND2) | + (NAND2 & NAND1 & C0BAR))) } + SUM4 = { (NAND4 & ~NOR4) ^ (~(NOR3 | (NOR2 & NAND3) | + (NOR1 & NAND3 & NAND2) | (NAND3 & NAND2 & NAND1 & C0BAR))) } + C4 = { ~( NOR4 | (NOR3 & NAND4) | (NOR2 & NAND4 & NAND3) | + (NOR1 & NAND4 & NAND3 & NAND2) | + (NAND4 & NAND3 & NAND2 & NAND1 & C0BAR) ) } * ULS83ADLY PINDLY (5,0,9) DPWR DGND + SUM1 SUM2 SUM3 SUM4 C4 + C0 A1 A2 A3 A4 B1 B2 B3 B4 + SUM1_O SUM2_O SUM3_O SUM4_O C4_O + IO_LS MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_AB = { CHANGED(A1,0) | CHANGED(B1,0) | CHANGED(A2,0) | + CHANGED(B2,0) | CHANGED(A3,0) | CHANGED(B3,0) | + CHANGED(A4,0) | CHANGED(B4,0) } + + + PINDLY: + SUM1_O SUM2_O SUM3_O SUM4_O = { + CASE( + ANY_CH_AB, DELAY(-1,15NS,24NS), + CHANGED(C0,0) & TRN_LH, DELAY(-1,16NS,24NS), + CHANGED(C0,0) & TRN_HL, DELAY(-1,15NS,24NS), + DELAY(-1,17NS,25NS) ;DEFAULT + ) + } + C4_O = { + CASE( + CHANGED(C0,0) & TRN_HL, DELAY(-1,15NS,22NS), + ANY_CH_AB & TRN_HL, DELAY(-1,12NS,17NS), + (ANY_CH_AB | CHANGED(C0,0)) & TRN_LH, DELAY(-1,11NS,17NS), + DELAY(-1,16NS,23NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS85 4-BIT MAGNITUDE COMPARATOR * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-20-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS85 A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + AGBIN_I AEBIN_I ALBIN_I AGBOUT_O AEBOUT_O ALBOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS85LOG LOGICEXP(11,14) DPWR DGND + A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I AGBIN_I AEBIN_I ALBIN_I + A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN + AGBOUT AEBOUT ALBOUT + D0_GATE + IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + A3 = { A3_I } + A2 = { A2_I } + A1 = { A1_I } + A0 = { A0_I } + B3 = { B3_I } + B2 = { B2_I } + B1 = { B1_I } + B0 = { B0_I } + AGBIN = { AGBIN_I } + AEBIN = { AEBIN_I } + ALBIN = { ALBIN_I } + * INTERMEDIATE TERMS: + C3 = { ~(A3 & B3) } + C2 = { ~(A2 & B2) } + C1 = { ~(A1 & B1) } + C0 = { ~(A0 & B0) } + A3C3 = { A3 & C3 } + A2C2 = { A2 & C2 } + A1C1 = { A1 & C1 } + A0C0 = { A0 & C0 } + B3C3 = { B3 & C3 } + B2C2 = { B2 & C2 } + B1C1 = { B1 & C1 } + B0C0 = { B0 & C0 } + D3 = { ~(A3C3 | B3C3) } + D2 = { ~(A2C2 | B2C2) } + D1 = { ~(A1C1 | B1C1) } + D0 = { ~(A0C0 | B0C0) } + D32 = { D3 & D2 } + D31 = { D32 & D1 } + D30 = { D31 & D0 } + * OUTPUT ASSIGNMENTS: + AGBOUT = { ~B3C3 & ~(B2C2 & D3) & ~(B1C1 & D32) & ~(B0C0 & D31) & + ~(ALBIN & D30) & ~(AEBIN & D30) } + AEBOUT = { D30 & AEBIN } + ALBOUT = { ~(AEBIN & D30) & ~(AGBIN & D30) & ~(A0C0 & D31) & + ~(A1C1 & D32) & ~(A2C2 & D3) & ~A3C3 } * ULS85DLY PINDLY (3,0,11) DPWR DGND + AGBOUT AEBOUT ALBOUT + A3 A2 A1 A0 B3 B2 B1 B0 AGBIN AEBIN ALBIN + AGBOUT_O AEBOUT_O ALBOUT_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATA_CHANGE = { CHANGED(A3,0) | CHANGED(A2,0) | CHANGED(A1,0) | CHANGED(A0,0) + | CHANGED(B3,0) | CHANGED(B2,0) | CHANGED(B1,0) | CHANGED(B0,0) } + AEBIN_CHANGE = { CHANGED(AEBIN,0) } + ABIN_CHANGE = { AEBIN_CHANGE | CHANGED(ALBIN,0) | CHANGED(AGBIN,0) } + + PINDLY: + AGBOUT_O ALBOUT_O = { ;AGBOUT & ALBOUT HAS THE SAME DELAY SO CAN BE GROUPPED + CASE( + DATA_CHANGE & TRN_LH, DELAY(-1,24NS,36NS), + DATA_CHANGE & TRN_HL, DELAY(-1,20NS,30NS), + ABIN_CHANGE & TRN_LH, DELAY(-1,14NS,22NS), + ABIN_CHANGE & TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,25NS,37NS) ;DEFAULT + ) + } + AEBOUT_O = { + CASE( + DATA_CHANGE & TRN_LH, DELAY(-1,27NS,45NS), + DATA_CHANGE & TRN_HL, DELAY(-1,23NS,45NS), + AEBIN_CHANGE & TRN_LH, DELAY(-1,13NS,20NS), + AEBIN_CHANGE & TRN_HL, DELAY(-1,13NS,26NS), + DELAY(-1,28NS,46NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS86 Quadruple 2-input Exclusive-Or Gates * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names * .subckt 74LS86A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(2) DPWR DGND + A B A_BUF B_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 or(2) DPWR DGND + A_BUF B_BUF C + D_LS86_1 IO_LS MNTYMXDLY={MNTYMXDLY} U2 nand(2) DPWR DGND + A_BUF B_BUF D + D_LS86_2 IO_LS MNTYMXDLY={MNTYMXDLY} U3 and(2) DPWR DGND + C D Y + D_LS86_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS86_1 ugate ( + tplhty=12ns tplhmx=23ns + ) .model D_LS86_2 ugate ( + tplhty=20ns tplhmx=30ns + tphlty=3ns tphlmx=5ns + ) .model D_LS86_3 ugate ( + tphlty=10ns tphlmx=17ns + ) *$ *--------- * 74LS90 COUNTER DECADE 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-2-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS90 R91_I R92_I CKA_I CKB_I R01_I R02_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + SET9BAR CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI CLRBAR23 CKB QDBAR $D_HI QB $D_NC + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI CLRBAR23 QB $D_HI $D_HI QC $D_NC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + SET9BAR CLRBAR CKB J4 QD QD QDBAR + D0_EFF IO_LS ULS90LOG LOGICEXP (8,10) DPWR DGND + R91_I R92_I CKA_I CKB_I R01_I R02_I QB QC + R91 R92 CKA CKB R01 R02 J4 SET9BAR CLRBAR CLRBAR23 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + R91 = { R91_I } + R92 = { R92_I } + CKA = { CKA_I } + CKB = { CKB_I } + R01 = { R01_I } + R02 = { R02_I } + SET9BAR = { ~(R91 & R92) } + CLRBAR = { ~(R01 & R02) } + CLRBAR23 = { CLRBAR & SET9BAR } + J4 = { QB & QC } * ULS90DLY PINDLY (4,0,8) DPWR DGND + QA QB QC QD + CKA CKB CLRBAR SET9BAR R01 R02 R91 R92 + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + SETNINE = { CHANGED_HL(SET9BAR,0) } + + PINDLY: + QA_O = { + CASE ( + CLOCKEDA & TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDA & TRN_HL, DELAY(-1,12NS,18NS), + SETNINE, DELAY(-1,20NS,30NS), + DELAY(-1,26NS,40NS) + ) + } + QB_O = { + CASE ( + CLOCKEDB & TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,26NS,40NS) + ) + } + QC_O = { + CASE ( + CLOCKEDB & TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } + QD_O = { + CASE ( + SETNINE, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } + + FREQ: + NODE = CKA + MAXFREQ = 32MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 16MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CKB + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = R01 + MIN_LO = 30NS + WHEN = { SET9BAR!='0 } + WIDTH: + NODE = R02 + MIN_LO = 30NS + WHEN = { SET9BAR!='0 } + WIDTH: + NODE = R91 + MIN_LO = 30NS + WIDTH: + NODE = R92 + MIN_LO = 30NS + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKA + RELEASETIME_LH = 25NS + WHEN = { SET9BAR!='0 & CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKB + RELEASETIME_LH = 25NS + WHEN = { SET9BAR!='0 & CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R91 R92 + CLOCK HL = CKA + RELEASETIME_LH = 25NS + WHEN = { CHANGED(SET9BAR,25NS) } + SETUP_HOLD: + DATA(2) = R91 R92 + CLOCK HL = CKB + RELEASETIME_LH = 25NS + WHEN = { CHANGED(SET9BAR,25NS) } * .ENDS * *$ *--------- * 74LS91 8-BIT SHIFT REGISTERS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTKKY DATA BOOK, 1988, TI * NH 7/23/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS91 CLK_I A_I B_I QH_O QHBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(3) DPWR DGND CLK_I A_I B_I CLK A B + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U2 NAND(2) DPWR DGND A B KA + D0_GATE IO_LS * U3 INVA(2) DPWR DGND CLK KA CLKBAR JA + D0_GATE IO_LS * U5 JKFF(8) DPWR DGND $D_HI $D_HI CLKBAR + JA QA QB QC QD QE QF QG KA QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR + QA QB QC QD QE QF QG QH QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR QHBAR + D0_EFF IO_LS * ULS91DLY PINDLY (2,0,3) DPWR DGND + QH QHBAR + CLK A B + QH_O QHBAR_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QH_O QHBAR_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,24NS,40NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,27NS,40NS), + DELAY(-1,28NS,41NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 10MEG + + WIDTH: + NODE = CLK + MIN_HI = 25NS + MIN_LO = 25NS + + SETUP_HOLD: + DATA(2) A B + CLOCK LH = CLK + SETUPTIME = 25NS * .ENDS * *$ *--------- * 74LS92 COUNTER DIVIDE-BY-12 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-3-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE -- THE CKA TO QA PIN DELAY IS NOT INCLUDED IN THIS MODEL SINCE * THE DIV2 AND DIV8 SECTIONS OF THE COUNTER ACT INDEPENDENTLY. * .SUBCKT 74LS92 CKA_I CKB_I R01_I R02_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI CLRBAR CKB QCBAR $D_HI QB $D_NC + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI CLRBAR CKB QB $D_HI QC QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + $D_HI CLRBAR QC $D_HI $D_HI QD $D_NC + D0_EFF IO_LS U5 BUFA(4) DPWR DGND + CKA_I CKB_I R01_I R02_I CKA CKB R01 R02 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U6 NAND(2) DPWR DGND + R01 R02 CLRBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * ULS92DLY PINDLY (4,0,5) DPWR DGND + QA QB QC QD + CKA CKB CLRBAR R01 R02 + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + CLEARED = { CHANGED_HL(CLRBAR,0) } + + PINDLY: + QA_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDA & TRN_HL, DELAY(-1,12NS,18NS), + DELAY(-1,26NS,40NS) + ) + } + QB_O QC_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,26NS,40NS) + ) + } + QD_O = { + CASE ( + TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } + + FREQ: + NODE = CKA + MAXFREQ = 32MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 16MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CKB + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = R01 + MIN_HI = 30NS + WIDTH: + NODE = R02 + MIN_HI = 30NS + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKA + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKB + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } * .ENDS * *$ *--------- * 74LS93 COUNTER BINARY 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 6-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE -- THE CKA TO QA PIN DELAY IS NOT INCLUDED IN THIS MODEL SINCE * THE DIV2 AND DIV8 SECTIONS OF THE COUNTER ACT INDEPENDENTLY. * .SUBCKT 74LS93 CKA_I CKB_I R01_I R02_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI CLRBAR CKB $D_HI $D_HI QB $D_NC + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI CLRBAR QB $D_HI $D_HI QC $D_NC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + $D_HI CLRBAR QC $D_HI $D_HI QD $D_NC + D0_EFF IO_LS U5 BUFA(4) DPWR DGND + CKA_I CKB_I R01_I R02_I CKA CKB R01 R02 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U6 NAND(2) DPWR DGND + R01 R02 CLRBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * ULS93DLY PINDLY (4,0,5) DPWR DGND + QA QB QC QD + CKA CKB CLRBAR R01 R02 + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + CLEARED = { CHANGED_HL(CLRBAR,0) } + + PINDLY: + QA_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDA & TRN_HL, DELAY(-1,12NS,18NS), + DELAY(-1,26NS,40NS) + ) + } + QB_O = { + CASE ( + TRN_LH, DELAY(-1,10NS,16NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,26NS,40NS) + ) + } + QC_O = { + CASE ( + TRN_LH, DELAY(-1,21NS,32NS), + CLOCKEDB & TRN_HL, DELAY(-1,23NS,35NS), + DELAY(-1,26NS,40NS) + ) + } + QD_O = { + CASE ( + CLEARED, DELAY(-1,26NS,40NS), + DELAY(-1,34NS,51NS) + ) + } + + FREQ: + NODE = CKA + MAXFREQ = 32MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 16MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CKB + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = R01 + MIN_HI = 30NS + WIDTH: + NODE = R02 + MIN_HI = 30NS + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKA + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } + SETUP_HOLD: + DATA(2) = R01 R02 + CLOCK HL = CKB + RELEASETIME_HL = 25NS + WHEN = { CHANGED(CLRBAR,25NS) } * .ENDS * *$ *-------- * 74LS95B 4-BIT PARALLEL SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-2-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS95B MODE_I CLK1_I CLK2_I SER_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS95BLOG LOGICEXP(11,13) DPWR DGND + MODE_I CLK1_I CLK2_I SER_I A_I B_I C_I D_I QA QB QC + MODE CLK1 CLK2 SER A B C D CLK DA DB DC DD + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: + MODE = { MODE_I } + CLK1 = { CLK1_I } + CLK2 = { CLK2_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERM + MODEBAR = { ~MODE } + + CLK = { ~((MODEBAR & CLK1) | (MODE & CLK2)) } + DA = { (MODEBAR & SER) | (MODE & A) } + DB = { (MODEBAR & QA) | (MODE & B) } + DC = { (MODEBAR & QB) | (MODE & C) } + DD = { (MODEBAR & QC) | (MODE & D) } * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD + $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS95BDLY PINDLY (4,0,8) DPWR DGND + QA QB QC QD + CLK1 CLK2 MODE SER A B C D + QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLK = { CHANGED_HL(CLK1,0) | CHANGED_HL(CLK2,0) } + + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLK & TRN_LH, DELAY(-1,18NS,27NS), + CLK & TRN_HL, DELAY(-1,21NS,32NS), + DELAY(-1,22NS,33NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK1 + MAXFREQ = 25MEG + + FREQ: + NODE = CLK2 + MAXFREQ = 25MEG + + WIDTH: + NODE = CLK1 + MIN_HI = 20NS + + WIDTH: + NODE = CLK2 + MIN_HI = 20NS + + SETUP_HOLD: + DATA(4) A B C D + CLOCK HL = CLK2 + SETUPTIME = 20NS + HOLDTIME = 10NS + WHEN = { (MODE != '0 ^ CHANGED(MODE,0)) } + + SETUP_HOLD: + DATA(1) SER + CLOCK HL = CLK1 + SETUPTIME = 20NS + HOLDTIME = 10NS + WHEN = { (MODE != '1 ^ CHANGED(MODE,0)) } + + SETUP_HOLD: ; T_ENABLE1 + DATA(1) MODE + CLOCK HL = CLK1 + SETUPTIME_LO = 20NS + MESSAGE = "TENABLE1 IS NOT MET" + + SETUP_HOLD: ; T_ENABLE2 + DATA(1) MODE + CLOCK HL = CLK2 + SETUPTIME_HI = 20NS + MESSAGE = "TENABLE2 IS NOT MET" + + SETUP_HOLD: ; T_INHIBIT1 + DATA(1) MODE + CLOCK LH = CLK1 + SETUPTIME_HI = 20NS + MESSAGE = "TINHIBIT1 IS NOT MET" + + SETUP_HOLD: ; T_INHIBIT2 + DATA(1) MODE + CLOCK LH = CLK2 + SETUPTIME_LO = 20NS + MESSAGE = "TINHIBIT2 IS NOT MET" * .ENDS * *$ *--------- *74LS96 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-1-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS96 CLRBAR_I CLK_I SER_I PRE_I A_I B_I C_I D_I E_I + QA_O QB_O QC_O QD_O QE_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * * U1 BUFA(9) DPWR DGND + CLRBAR_I CLK_I SER_I PRE_I A_I B_I C_I D_I E_I + CLRBAR CLK SER PRE A B C D E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U2 NANDA(2,5) DPWR DGND + PRE A PRE B PRE C PRE D PRE E + OUT_A OUT OUT_C OUT_D OUT_E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U3 DFF(1) DPWR DGND + OUT_A CLRBAR CLK + SER + QA + $D_NC + D0_EFF IO_LS * U4 DFF(1) DPWR DGND + OUT CLRBAR CLK + QA + QB + $D_NC + D0_EFF IO_LS * U5 DFF(1) DPWR DGND + OUT_C CLRBAR CLK + QB + QC + $D_NC + D0_EFF IO_LS * U6 DFF(1) DPWR DGND + OUT_D CLRBAR CLK + QC + QD + $D_NC + D0_EFF IO_LS * U7 DFF(1) DPWR DGND + OUT_E CLRBAR CLK + QD + QE + $D_NC + D0_EFF IO_LS * ULS96DLY PINDLY (5,0,4) DPWR DGND + QA QB QC QD QE + CLRBAR PRE CLK SER + QA_O QB_O QC_O QD_O QE_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O QE_O = { + CASE( + CHANGED_LH(PRE,0), DELAY(-1,28NS,35NS), + CHANGED_LH(CLK,0), DELAY(-1,25NS,40NS), + CHANGED_HL(CLRBAR,0), DELAY(-1,-1,55NS), + DELAY(-1,-1,56NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 25MEG * + WIDTH: + NODE = CLK + MIN_HI = 20NS + MIN_LO = 20NS * + WIDTH: + NODE = CLRBAR + MIN_LO = 30NS * + WIDTH: + NODE = PRE + MIN_HI = 30NS * + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { (CLRBAR != '0) & (PRE != '1) } * .ENDS * *$ *--------- * 74LS107A Dual J-K Flip-Flops with Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/29/89 Update interface and model names * .subckt 74LS107A CLK CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + $D_HI CLRBAR CLK J K Q QBAR + D_LS107 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS107 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhmn=20ns + twpclmx=20ns twpclmn=20ns + tsudclkmx=20ns tsudclkmn=20ns + thdclkmn=20ns thdclkmx=20ns + ) *$ *--------- * 74LS109A Dual J-KBar Positive-Edge-Triggered Flip-Flops w/ Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 06/30/89 Update interface and model names * .subckt 74LS109A CLK PREBAR CLRBAR J KBAR Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(3) DPWR DGND + PREBAR CLRBAR J PREBAR_BUF CLRBAR_BUF J_BUF + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + PREBAR_BUF CLRBAR_BUF CLKBAR J1 K1 Q QBAR + D_LS109A_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inva(2) DPWR DGND + CLK KBAR CLKBAR K + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U3 bufa(2) DPWR DGND + J_BUF K J1 K1 + D0_GATE IO_LS U4 bufa(2) DPWR DGND + J_BUF K J1 K1 + D_LS109A_2 IO_LS MNTYMXDLY={MNTYMXDLY} .ends * .model D_LS109A_1 ueff ( + tppcqlhty=13ns tppcqlhmx=25ns + tppcqhlty=25ns tppcqhlmx=40ns + tpclkqlhty=13ns tpclkqlhmx=25ns + tpclkqhlty=25ns tpclkqhlmx=40ns + twclkhmx=25ns twclklmx=25ns + twclkhmn=25ns twclklmn=25ns + twpclmx=25ns twpclmn=25ns + tsudclkmx=25ns tsudclkmn=25ns + thdclkmx=5ns thdclkmn=5ns + ) .model D_LS109A_2 ugate ( + tplhmn=10ns tplhmx=10ns + ) *$ *--------- * 74LS112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Clear * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * muw 03/13/90 Correct timing - Data book has LS and S timing reversed * .subckt 74LS112A CLK PREBAR CLRBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * NOTE: Spec allows tsu pre-clk to be 20ns, this model requires 25ns, the same as tsu clr-clk * U1 jkff(1) DPWR DGND + PREBAR CLRBAR CLK J K Q QBAR + D_LS112 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS112 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkty=20ns + tsupcclkhmx=25ns tsupcclkhty=25ns + ) *$ *--------- * 74LS113A Dual J-K Negative-Edge-Triggered Flip-Flops with Preset * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * .subckt 74LS113A CLK PREBAR J K Q QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 jkff(1) DPWR DGND + PREBAR $D_HI CLK J K Q QBAR + D_LS113 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS113 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkmn=20ns + tsupcclkhmx=20ns tsupcclkhmn=20ns + ) *$ *--------- * 74LS114 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset & Common Clear, & Common Clock * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * .subckt 74LS114A CLK CLRBAR 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UIBUF bufa(4) DPWR DGND + CLK CLRBAR 1PREBAR 2PREBAR CLK_BUF CLRBAR_BUF 1PREB 2PREB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 jkff(1) DPWR DGND + 1PREB CLRBAR_BUF CLK_BUF 1J 1K 1Q 1QBAR + D_LS114 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 jkff(1) DPWR DGND + 2PREB CLRBAR_BUF CLK_BUF 2J 2K 2Q 2QBAR + D_LS114 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS114 ueff ( + tppcqlhty=15ns tppcqlhmx=20ns + tppcqhlty=15ns tppcqhlmx=20ns + tpclkqlhty=15ns tpclkqlhmx=20ns + tpclkqhlty=15ns tpclkqhlmx=20ns + twclkhmx=20ns twclkhty=20ns + twpclmx=25ns twpclty=25ns + tsudclkmx=20ns tsudclkty=20ns + tsupcclkhty=25ns tsupcclkhmx=25ns + ) *$ *--------- * 74LS125A Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * .subckt 74LS125A A GBAR Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_LS125A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv DPWR DGND + GBAR G + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} .ends * .model D_LS125A utgate ( + tplhty=9ns tplhmx=15ns + tphlty=7ns tphlmx=18ns + tpzhty=12ns tpzhmx=20ns + tpzlty=15ns tpzlmx=25ns + tphzty=20ns tphzmx=20ns + tplzty=20ns tplzmx=20ns + ) *$ *--------- * 74LS126A Quadruple Bus Buffer with 3-state Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * .subckt 74LS126A A G Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 buf3 DPWR DGND + A G Y + D_LS126A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS126A utgate ( + tplhty=9ns tplhmx=15ns + tphlty=8ns tphlmx=18ns + tpzhty=16ns tpzhmx=25ns + tpzlty=21ns tpzlmx=35ns + tphzty=25ns tphzmx=25ns + tplzty=25ns tplzmx=25ns + ) *$ *--------- * 74LS132 Quadruple 2-input Positive-Nand Schmitt Triggers * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * .subckt 74LS132 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: These devices are modeled as simple Nand gates. * Hysteresis is modeled by the AtoD interface. * U1 nand(2) DPWR DGND + A B Y + D_LS132 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS132 ugate ( + tplhty=15ns tplhmx=22ns + tphlty=15ns tphlmx=22ns + ) *$ *--------- * 74LS136 Quadruple 2-input Exclusive-Or Gates with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * tdn 07/05/89 Update interface and model names * .subckt 74LS136 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 xor DPWR DGND + A B Y + D_LS136 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends 74LS136 * .model D_LS136 ugate ( + tplhty=18ns tplhmx=30ns + tphlty=18ns tphlmx=30ns + ) * *$ *--------- * 74LS137 DECODER/DEMULTIPLEXER 3-8 LINE WITH ADDRESS LATCHES * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS137 G1_I G2BAR_I GLBAR_I A_I B_I C_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DLTCH(3) DPWR DGND + $D_HI $D_HI LATCHEN + A B C + QA QB QC + QABAR QBBAR QCBAR + D0_GFF IO_LS * ULS137LOG LOGICEXP (12,16) DPWR DGND + G1_I G2BAR_I GLBAR_I A_I B_I C_I QA QB QC QABAR QBBAR QCBAR + G1 G2BAR GLBAR A B C LATCHEN ENABLE + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1 = { G1_I } + G2BAR = { G2BAR_I } + GLBAR = { GLBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + LATCHEN = { ~GLBAR } + ENABLE = { G1 & ~G2BAR } + Y0 = { ~(ENABLE & QCBAR & QBBAR & QABAR) } + Y1 = { ~(ENABLE & QCBAR & QBBAR & QA ) } + Y2 = { ~(ENABLE & QCBAR & QB & QABAR) } + Y3 = { ~(ENABLE & QCBAR & QB & QA ) } + Y4 = { ~(ENABLE & QC & QBBAR & QABAR) } + Y5 = { ~(ENABLE & QC & QBBAR & QA ) } + Y6 = { ~(ENABLE & QC & QB & QABAR) } + Y7 = { ~(ENABLE & QC & QB & QA ) } * ULS137DLY PINDLY (8,0,7) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + G1 G2BAR GLBAR A B C ENABLE + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE1 = { CHANGED(ENABLE,0) & CHANGED(G1,0) } + ABLE2 = { CHANGED(ENABLE,0) & CHANGED(G2BAR,0) } + ABLEL = { CHANGED(GLBAR,0) } + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC = { CHANGED(C,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + + PINDLY: + Y0_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y1_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDRA , DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y2_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDRB , DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y3_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDRA , DELAY(-1,25NS,38NS), + ADDRB , DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y4_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDRC , DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y5_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDRA , DELAY(-1,25NS,38NS), + ADDRC , DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y6_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDRB , DELAY(-1,25NS,38NS), + ADDRC , DELAY(-1,25NS,38NS), + ADDR & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,25NS,38NS) + ) + } + Y7_O = { + CASE ( + ABLE2 & TRN_LH, DELAY(-1,13NS,21NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,21NS), + ABLE2 & TRN_HL, DELAY(-1,16NS,27NS), + ABLE1 & TRN_HL, DELAY(-1,18NS,27NS), + ABLEL & TRN_LH, DELAY(-1,18NS,27NS), + ABLEL & TRN_HL, DELAY(-1,25NS,38NS), + ADDR , DELAY(-1,25NS,38NS), + DELAY(-1,25NS,38NS) + ) + } + + WIDTH: + NODE = GLBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(3) = A B C + CLOCK LH = GLBAR + SETUPTIME = 10NS + HOLDTIME = 10NS * .ENDS * *$ *--------- * 74LS138 DECODER/DEMULTIPLEXER 3-8 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS138 G1_I G2ABAR_I G2BBAR_I A_I B_I C_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS138LOG LOGICEXP (6,15) DPWR DGND + G1_I G2ABAR_I G2BBAR_I A_I B_I C_I + G1 G2ABAR G2BBAR A B C ENABLE + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1 = { G1_I } + G2ABAR = { G2ABAR_I } + G2BBAR = { G2BBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + ENABLE = { ~G2ABAR & ~G2BBAR & G1 } + Y0 = { ~(ENABLE & CBAR & BBAR & ABAR) } + Y1 = { ~(ENABLE & CBAR & BBAR & A ) } + Y2 = { ~(ENABLE & CBAR & B & ABAR) } + Y3 = { ~(ENABLE & CBAR & B & A ) } + Y4 = { ~(ENABLE & C & BBAR & ABAR) } + Y5 = { ~(ENABLE & C & BBAR & A ) } + Y6 = { ~(ENABLE & C & B & ABAR) } + Y7 = { ~(ENABLE & C & B & A ) } * ULS138DLY PINDLY (8,0,7) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 + ENABLE G1 G2ABAR G2BBAR A B C + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE1 = { CHANGED(ENABLE,0) & CHANGED(G1,0) } + ABLE2 = { CHANGED(ENABLE,0) & (CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)) } + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC = { CHANGED(C,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + + PINDLY: + Y0_O = { + CASE ( + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,20NS,41NS) + ) + } + Y1_O = { + CASE ( + ADDRA & TRN_LH, DELAY(-1,21NS,27NS), + ADDRA & TRN_HL, DELAY(-1,20NS,39NS), + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } + Y2_O = { + CASE ( + ADDRB & TRN_LH, DELAY(-1,21NS,27NS), + ADDRB & TRN_HL, DELAY(-1,20NS,39NS), + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } + Y3_O = { + CASE ( + ADDRA & TRN_LH, DELAY(-1,21NS,27NS), + ADDRA & TRN_HL, DELAY(-1,20NS,39NS), + ADDRB & TRN_LH, DELAY(-1,21NS,27NS), + ADDRB & TRN_HL, DELAY(-1,20NS,39NS), + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } + Y4_O = { + CASE ( + ADDRC & TRN_LH, DELAY(-1,21NS,27NS), + ADDRC & TRN_HL, DELAY(-1,20NS,39NS), + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } + Y5_O = { + CASE ( + ADDRA & TRN_LH, DELAY(-1,21NS,27NS), + ADDRA & TRN_HL, DELAY(-1,20NS,39NS), + ADDRC & TRN_LH, DELAY(-1,21NS,27NS), + ADDRC & TRN_HL, DELAY(-1,20NS,39NS), + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } + Y6_O = { + CASE ( + ADDRB & TRN_LH, DELAY(-1,21NS,27NS), + ADDRB & TRN_HL, DELAY(-1,20NS,39NS), + ADDRC & TRN_LH, DELAY(-1,21NS,27NS), + ADDRC & TRN_HL, DELAY(-1,20NS,39NS), + ADDR & TRN_LH, DELAY(-1,11NS,20NS), + ADDR & TRN_HL, DELAY(-1,18NS,41NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } + Y7_O = { + CASE ( + ADDR & TRN_LH, DELAY(-1,21NS,27NS), + ADDR & TRN_HL, DELAY(-1,20NS,39NS), + ABLE1 & TRN_LH, DELAY(-1,14NS,26NS), + ABLE1 & TRN_HL, DELAY(-1,13NS,38NS), + ABLE2 & TRN_LH, DELAY(-1,12NS,18NS), + ABLE2 & TRN_HL, DELAY(-1,20NS,32NS), + DELAY(-1,21NS,41NS) + ) + } * .ENDS * *$ *-------- * 74LS139A DECODER/DEMULTIPLEXER 2-4 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-31-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS139A GBAR_I A_I B_I Y0_O Y1_O Y2_O Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS139LOG LOGICEXP (3,7) DPWR DGND + GBAR_I A_I B_I + GBAR A B + Y0 Y1 Y2 Y3 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + ABAR = { ~A } + BBAR = { ~B } + ENABLE = { ~GBAR } + Y0 = { ~(ENABLE & BBAR & ABAR ) } + Y1 = { ~(ENABLE & BBAR & A ) } + Y2 = { ~(ENABLE & B & ABAR ) } + Y3 = { ~(ENABLE & B & A ) } * ULS139DLY PINDLY (4,0,3) DPWR DGND + Y0 Y1 Y2 Y3 + GBAR A B + Y0_O Y1_O Y2_O Y3_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(GBAR,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) } + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + + PINDLY: + Y0_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,16NS,24NS), + ABLE & TRN_HL, DELAY(-1,21NS,32NS), + ADDR & TRN_LH, DELAY(-1,13NS,20NS), + ADDR & TRN_HL, DELAY(-1,22NS,33NS), + DELAY(-1,22NS,33NS) + ) + } + Y1_O = { + CASE ( + ADDRB & TRN_LH, DELAY(-1,13NS,20NS), + ABLE & TRN_LH, DELAY(-1,16NS,24NS), + ADDRA & TRN_LH, DELAY(-1,18NS,29NS), + ABLE & TRN_HL, DELAY(-1,21NS,32NS), + ADDRB & TRN_HL, DELAY(-1,22NS,33NS), + ADDRA & TRN_HL, DELAY(-1,25NS,38NS), + DELAY(-1,25NS,38NS) + ) + } + Y2_O = { + CASE ( + ADDRA & TRN_LH, DELAY(-1,13NS,20NS), + ABLE & TRN_LH, DELAY(-1,16NS,24NS), + ADDRB & TRN_LH, DELAY(-1,18NS,29NS), + ABLE & TRN_HL, DELAY(-1,21NS,32NS), + ADDRA & TRN_HL, DELAY(-1,22NS,33NS), + ADDRB & TRN_HL, DELAY(-1,25NS,38NS), + DELAY(-1,25NS,38NS) + ) + } + Y3_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,16NS,24NS), + ADDR & TRN_LH, DELAY(-1,18NS,29NS), + ABLE & TRN_HL, DELAY(-1,21NS,32NS), + ADDR & TRN_HL, DELAY(-1,25NS,38NS), + DELAY(-1,25NS,38NS) + ) + } * .ENDS * *$ *--------- * 74LS145 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS145 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS145LOG LOGICEXP (4,10) DPWR DGND + A_I B_I C_I D_I + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(DBAR & CBAR & BBAR & ABAR ) } + Y1 = { ~(DBAR & CBAR & BBAR & A ) } + Y2 = { ~(DBAR & CBAR & B & ABAR ) } + Y3 = { ~(DBAR & CBAR & B & A ) } + Y4 = { ~(DBAR & C & BBAR & ABAR ) } + Y5 = { ~(DBAR & C & BBAR & A ) } + Y6 = { ~(DBAR & C & B & ABAR ) } + Y7 = { ~(DBAR & C & B & A ) } + Y8 = { ~(D & CBAR & BBAR & ABAR ) } + Y9 = { ~(D & CBAR & BBAR & A ) } * ULS145DLY PINDLY (10,0,0) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 + + + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O = + { DELAY(-1,-1,50NS) } * .ENDS * *$ *--------- * 74LS147 PRIORITY ENCODER 10-4 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS147 IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I IN8_I IN9_I + A_O B_O C_O D_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS147LOG LOGICEXP (9,13) DPWR DGND + IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I IN8_I IN9_I + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + A B C D + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + IN1 = { IN1_I } + IN2 = { IN2_I } + IN3 = { IN3_I } + IN4 = { IN4_I } + IN5 = { IN5_I } + IN6 = { IN6_I } + IN7 = { IN7_I } + IN8 = { IN8_I } + IN9 = { IN9_I } + IN1BAR = { ~IN1 } + IN2BAR = { ~IN2 } + IN3BAR = { ~IN3 } + IN4BAR = { ~IN4 } + IN5BAR = { ~IN5 } + IN6BAR = { ~IN6 } + IN7BAR = { ~IN7 } + IN8BAR = { ~IN8 } + IN9BAR = { ~IN9 } + + D = { IN8 & IN9 } + C = { ~(D & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) } + B = { ~(D & ((IN2BAR & IN4 & IN5) | + (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) } + A = { ~(IN9BAR | D & ((IN1BAR & IN2 & IN4 & IN6) | + (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) } * ULS147DLY PINDLY (4,0,9) DPWR DGND + A B C D + IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 + A_O B_O C_O D_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATAHI = { IN9=='1 & IN8=='1 & IN7=='1 & IN6=='1 & IN5=='1 & + IN4=='1 & IN3=='1 & IN2=='1 & IN1=='1 } + + PINDLY: + A_O B_O C_O D_O = { + CASE ( + DATAHI, DELAY(-1,12NS,18NS), + TRN_HL, DELAY(-1,12NS,18NS), + TRN_LH, DELAY(-1,21NS,33NS), + DELAY(-1,21NS,33NS) + ) + } * .ENDS * *$ *--------- * 74LS148 PRIORITY ENCODER 8-3 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS148 IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I + A0_O A1_O A2_O GS_O EO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS148LOG LOGICEXP (9,14) DPWR DGND + IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I EI_I + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0 A1 A2 GS EO + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + IN0 = { IN0_I } + IN1 = { IN1_I } + IN2 = { IN2_I } + IN3 = { IN3_I } + IN4 = { IN4_I } + IN5 = { IN5_I } + IN6 = { IN6_I } + IN7 = { IN7_I } + EI = { EI_I } + IN0BAR = { ~IN0 } + IN1BAR = { ~IN1 } + IN2BAR = { ~IN2 } + IN3BAR = { ~IN3 } + IN4BAR = { ~IN4 } + IN5BAR = { ~IN5 } + IN6BAR = { ~IN6 } + IN7BAR = { ~IN7 } + EIBAR = { ~EI } + + A0 = { ~(EIBAR & ((IN1BAR & IN2 & IN4 & IN6) | + (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) } + A1 = { ~(EIBAR & ((IN2BAR & IN4 & IN5) | + (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) } + A2 = { ~(EIBAR & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) } + EO = { ~(IN0 & IN1 & IN2 & IN3 & IN4 & IN5 & IN6 & IN7 & EIBAR) } + GS = { ~(EO & EIBAR) } * ULS148DLY PINDLY (5,0,9) DPWR DGND + A0 A1 A2 GS EO + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0_O A1_O A2_O GS_O EO_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATAHI = { IN7=='1 & IN6=='1 & IN5=='1 & IN4=='1 & + IN3=='1 & IN2=='1 & IN1=='1 & IN0=='1 } + ENABLE = { CHANGED(EI,0) } + + PINDLY: + A2_O A1_O A0_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,16NS,25NS), + ENABLE & TRN_HL, DELAY(-1,12NS,25NS), + DATAHI , DELAY(-1,14NS,18NS), + TRN_HL, DELAY(-1,15NS,25NS), + TRN_LH, DELAY(-1,20NS,36NS), + DELAY(-1,20NS,36NS) + ) + } + GS_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,12NS,17NS), + ENABLE & TRN_HL, DELAY(-1,14NS,36NS), + TRN_LH, DELAY(-1,35NS,55NS), + TRN_HL, DELAY(-1, 9NS,21NS), + DELAY(-1,18NS,30NS) + ) + } + EO_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,12NS,21NS), + ENABLE & TRN_HL, DELAY(-1,23NS,35NS), + TRN_LH, DELAY(-1, 7NS,18NS), + TRN_HL, DELAY(-1,25NS,40NS), + DELAY(-1,25NS,40NS) + ) + } * .ENDS * *$ *--------- * 74LS151 MULTIPLEXER/DATA SELECTOR 8-1 LINE * * THE TTL DATA BOOK, 1988, TI * TC 08/20/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74LS151 GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS151LOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + IG = { ~GBAR } + ID0 = { D0 & IA & IB & IC & IG } + ID1 = { D1 & A & IB & IC & IG } + ID2 = { D2 & IA & B & IC & IG } + ID3 = { D3 & A & B & IC & IG } + ID4 = { D4 & IA & IB & C & IG } + ID5 = { D5 & A & IB & C & IG } + ID6 = { D6 & IA & B & C & IG } + ID7 = { D7 & A & B & C & IG } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } * ULS151DLY PINDLY (2,0,12) DPWR DGND + W Y + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y_O = { + CASE( + SELECT & TRN_LH, DELAY(-1,27NS,43NS), + ENABLE & TRN_LH, DELAY(-1,26NS,42NS), + DATA & TRN_LH, DELAY(-1,20NS,32NS), + ENABLE & TRN_HL, DELAY(-1,20NS,32NS), + SELECT & TRN_HL, DELAY(-1,18NS,30NS), + DATA & TRN_HL, DELAY(-1,16NS,26NS), + DELAY(-1,28NS,44NS) + ) + } + W_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,20NS,32NS), + ENABLE & TRN_HL, DELAY(-1,18NS,30NS), + ENABLE & TRN_LH, DELAY(-1,15NS,24NS), + SELECT & TRN_LH, DELAY(-1,14NS,23NS), + DATA & TRN_LH, DELAY(-1,13NS,21NS), + DATA & TRN_HL, DELAY(-1,12NS,20NS), + DELAY(-1,21NS,33NS) + ) + } * .ENDS * *$ *--------- * 54LS152 MULTIPLEXER/DATA SELECTOR 8-1 LINE * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL,1985, TI * TC 08/24/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 54LS152 A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS152LOG LOGICEXP(11,12) DPWR DGND + A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + A B C D0 D1 D2 D3 D4 D5 D6 D7 W + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + ID0 = { D0 & IA & IB & IC } + ID1 = { D1 & A & IB & IC } + ID2 = { D2 & IA & B & IC } + ID3 = { D3 & A & B & IC } + ID4 = { D4 & IA & IB & C } + ID5 = { D5 & A & IB & C } + ID6 = { D6 & IA & B & C } + ID7 = { D7 & A & B & C } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } * ULS152DLY PINDLY (1,0,11) DPWR DGND + W + A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + PINDLY: + W_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,20NS,32NS), + SELECT & TRN_LH, DELAY(-1,14NS,23NS), + DATA & TRN_LH, DELAY(-1,13NS,21NS), + DATA & TRN_HL, DELAY(-1,12NS,20NS), + DELAY(-1,21NS,33NS) + ) + } * .ENDS * *$ *--------- * 74LS153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The TTL Data Book, 1988, TI * JSW 8/12/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS153 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS153LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * ULS153DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,25NS,38NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(-1,21NS,32NS), + SELECT & TRN_LH, DELAY(-1,19NS,29NS), + DATA1 & TRN_HL, DELAY(-1,17NS,26NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(-1,16NS,24NS), + DATA1 & TRN_LH, DELAY(-1,10NS,15NS), + DELAY(-1,26NS,39NS) + ) + } + Y2_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,25NS,38NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(-1,21NS,32NS), + SELECT & TRN_LH, DELAY(-1,19NS,29NS), + DATA2 & TRN_HL, DELAY(-1,17NS,26NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(-1,16NS,24NS), + DATA2 & TRN_LH, DELAY(-1,10NS,15NS), + DELAY(-1,26NS,39NS) + ) + } * .ENDS * *$ *--------- * 74LS154 DECODER/DEMULTIPLEXER 4-16 LINE * * LS/S TTL LOGIC DATABOOK, 1989, NATIONAL SEMICONDUCTOR * JLS 8-6-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS154 G1BAR_I G2BAR_I A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + Y8_O Y9_O Y10_O Y11_O Y12_O Y13_O Y14_O Y15_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS154LOG LOGICEXP (6,21) DPWR DGND + G1BAR_I G2BAR_I A_I B_I C_I D_I + ENABLE A B C D + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + ENABLE = { ~(G1BAR | G2BAR) } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ABAR = { ~A } + BBAR = { ~B } + CBAR = { ~C } + DBAR = { ~D } + Y0 = { ~(ENABLE & DBAR & CBAR & BBAR & ABAR) } + Y1 = { ~(ENABLE & DBAR & CBAR & BBAR & A ) } + Y2 = { ~(ENABLE & DBAR & CBAR & B & ABAR) } + Y3 = { ~(ENABLE & DBAR & CBAR & B & A ) } + Y4 = { ~(ENABLE & DBAR & C & BBAR & ABAR) } + Y5 = { ~(ENABLE & DBAR & C & BBAR & A ) } + Y6 = { ~(ENABLE & DBAR & C & B & ABAR) } + Y7 = { ~(ENABLE & DBAR & C & B & A ) } + Y8 = { ~(ENABLE & D & CBAR & BBAR & ABAR) } + Y9 = { ~(ENABLE & D & CBAR & BBAR & A ) } + Y10 = { ~(ENABLE & D & CBAR & B & ABAR) } + Y11 = { ~(ENABLE & D & CBAR & B & A ) } + Y12 = { ~(ENABLE & D & C & BBAR & ABAR) } + Y13 = { ~(ENABLE & D & C & BBAR & A ) } + Y14 = { ~(ENABLE & D & C & B & ABAR) } + Y15 = { ~(ENABLE & D & C & B & A ) } * ULS154DLY PINDLY (16,0,1) DPWR DGND + Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 + ENABLE + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + Y8_O Y9_O Y10_O Y11_O Y12_O Y13_O Y14_O Y15_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { CHANGED(ENABLE,0) } + + PINDLY: + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O + Y8_O Y9_O Y10_O Y11_O Y12_O Y13_O Y14_O Y15_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,-1,25NS), + DELAY(-1,-1,35NS) + ) + } * .ENDS * *$ *--------- * 74LS155A DECODER/DEMULTIPLEXER 2-4 LINE * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-29-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS155A G1BAR_I G2BAR_I A_I B_I C1_I C2BAR_I + 1Y0_O 1Y1_O 1Y2_O 1Y3_O 2Y0_O 2Y1_O 2Y2_O 2Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS155ALOG LOGICEXP (6,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I C1_I C2BAR_I + G1BAR A B C1 ENABLE1 ENABLE2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + C1 = { C1_I } + C2BAR = { C2BAR_I } + ABAR = { ~A } + BBAR = { ~B } + ENABLE1 = { ~G1BAR & C1 } + ENABLE2 = { ~G2BAR & ~C2BAR } + + 1Y0 = { ~(ENABLE1 & BBAR & ABAR) } + 1Y1 = { ~(ENABLE1 & BBAR & A ) } + 1Y2 = { ~(ENABLE1 & B & ABAR) } + 1Y3 = { ~(ENABLE1 & B & A ) } + + 2Y0 = { ~(ENABLE2 & BBAR & ABAR) } + 2Y1 = { ~(ENABLE2 & BBAR & A ) } + 2Y2 = { ~(ENABLE2 & B & ABAR) } + 2Y3 = { ~(ENABLE2 & B & A ) } * ULS155ADLY PINDLY (8,0,6) DPWR DGND + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + G1BAR A B C1 ENABLE1 ENABLE2 + 1Y0_O 1Y1_O 1Y2_O 1Y3_O 2Y0_O 2Y1_O 2Y2_O 2Y3_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { (CHANGED(G1BAR,0) & CHANGED(ENABLE1,0)) + | CHANGED(ENABLE2,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) } + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC1 = { CHANGED(C1,0) & CHANGED(ENABLE1,0) } + + PINDLY: + 1Y0_O 2Y0_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,10NS,15NS), + ADDR & TRN_LH, DELAY(-1,10NS,15NS), + ADDRC1 , DELAY(-1,18NS,27NS), + ABLE & TRN_HL, DELAY(-1,19NS,30NS), + ADDR & TRN_HL, DELAY(-1,19NS,30NS), + DELAY(-1,19NS,30NS) + ) + } + 1Y1_O 2Y1_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,10NS,15NS), + ADDRA & TRN_LH, DELAY(-1,17NS,26NS), + ADDRB & TRN_LH, DELAY(-1,10NS,15NS), + ADDRC1 , DELAY(-1,18NS,27NS), + ABLE & TRN_HL, DELAY(-1,19NS,30NS), + ADDR , DELAY(-1,19NS,30NS), + DELAY(-1,19NS,30NS) + ) + } + 1Y2_O 2Y2_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,10NS,15NS), + ADDRB & TRN_LH, DELAY(-1,17NS,26NS), + ADDRA & TRN_LH, DELAY(-1,10NS,15NS), + ADDRC1 , DELAY(-1,18NS,27NS), + ABLE & TRN_HL, DELAY(-1,19NS,30NS), + ADDR , DELAY(-1,19NS,30NS), + DELAY(-1,19NS,30NS) + ) + } + 1Y3_O 2Y3_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,10NS,15NS), + ADDR & TRN_LH, DELAY(-1,17NS,26NS), + ADDRC1 , DELAY(-1,18NS,27NS), + ABLE & TRN_HL, DELAY(-1,19NS,30NS), + ADDR & TRN_HL, DELAY(-1,19NS,30NS), + DELAY(-1,19NS,30NS) + ) + } * .ENDS * *$ *--------- * 74LS156 DECODER/DEMULTIPLEXER 2-4 LINE WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS156 G1BAR_I G2BAR_I A_I B_I C1_I C2BAR_I + 1Y0_O 1Y1_O 1Y2_O 1Y3_O 2Y0_O 2Y1_O 2Y2_O 2Y3_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS156LOG LOGICEXP (6,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I C1_I C2BAR_I + G1BAR A B C1 ENABLE1 ENABLE2 + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + C1 = { C1_I } + C2BAR = { C2BAR_I } + ABAR = { ~A } + BBAR = { ~B } + ENABLE1 = { ~G1BAR & C1 } + ENABLE2 = { ~G2BAR & ~C2BAR } + + 1Y0 = { ~(ENABLE1 & BBAR & ABAR) } + 1Y1 = { ~(ENABLE1 & BBAR & A ) } + 1Y2 = { ~(ENABLE1 & B & ABAR) } + 1Y3 = { ~(ENABLE1 & B & A ) } + + 2Y0 = { ~(ENABLE2 & BBAR & ABAR) } + 2Y1 = { ~(ENABLE2 & BBAR & A ) } + 2Y2 = { ~(ENABLE2 & B & ABAR) } + 2Y3 = { ~(ENABLE2 & B & A ) } * ULS156DLY PINDLY (8,0,6) DPWR DGND + 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 + G1BAR A B C1 ENABLE1 ENABLE2 + 1Y0_O 1Y1_O 1Y2_O 1Y3_O 2Y0_O 2Y1_O 2Y2_O 2Y3_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + ABLE = { (CHANGED(G1BAR,0) & CHANGED(ENABLE1,0)) + | CHANGED(ENABLE2,0) } + ADDR = { CHANGED(A,0) | CHANGED(B,0) } + ADDRA = { CHANGED(A,0) } + ADDRB = { CHANGED(B,0) } + ADDRC1 = { CHANGED(C1,0) & CHANGED(ENABLE1,0) } + + PINDLY: + 1Y0_O 2Y0_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,25NS,40NS), + ADDR & TRN_LH, DELAY(-1,25NS,40NS), + ADDRC1 , DELAY(-1,32NS,48NS), + ABLE & TRN_HL, DELAY(-1,34NS,51NS), + ADDR & TRN_HL, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + 1Y1_O 2Y1_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,25NS,40NS), + ADDRA & TRN_LH, DELAY(-1,31NS,46NS), + ADDRB & TRN_LH, DELAY(-1,25NS,40NS), + ADDRC1 , DELAY(-1,32NS,48NS), + ABLE & TRN_HL, DELAY(-1,34NS,51NS), + ADDR , DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + 1Y2_O 2Y2_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,25NS,40NS), + ADDRB & TRN_LH, DELAY(-1,31NS,46NS), + ADDRA & TRN_LH, DELAY(-1,25NS,40NS), + ADDRC1 , DELAY(-1,32NS,48NS), + ABLE & TRN_HL, DELAY(-1,34NS,51NS), + ADDR , DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + 1Y3_O 2Y3_O = { + CASE ( + ABLE & TRN_LH, DELAY(-1,25NS,40NS), + ADDR & TRN_LH, DELAY(-1,31NS,46NS), + ADDRC1 , DELAY(-1,32NS,48NS), + ABLE & TRN_HL, DELAY(-1,34NS,51NS), + ADDR & TRN_HL, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } * .ENDS * *$ *--------- * 74LS157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The TTL Data Book, 1988, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS157 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS157LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SEL1 = { ~GBAR & ~SEL } + SEL2 = { ~GBAR & SEL } + Y1 = { (1A & SEL1) | (1B & SEL2) } + Y2 = { (2A & SEL1) | (2B & SEL2) } + Y3 = { (3A & SEL1) | (3B & SEL2) } + Y4 = { (4A & SEL1) | (4B & SEL2) } * ULS157DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,18NS,27NS), + SELECT & TRN_LH, DELAY(-1,15NS,23NS), + ENABLE & TRN_HL, DELAY(-1,14NS,21NS), + ENABLE & TRN_LH, DELAY(-1,13NS,20NS), + DATA, DELAY(-1,9NS,14NS), + DELAY(-1,19NS,28NS) + ) + } * .ENDS * *$ *--------- * 74LS158 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The TTL Data Book, 1988, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS158 GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS158LOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SEL1 = { ~GBAR & ~SEL } + SEL2 = { ~GBAR & SEL } + Y1 = { ~((1A & SEL1) | (1B & SEL2)) } + Y2 = { ~((2A & SEL1) | (2B & SEL2)) } + Y3 = { ~((3A & SEL1) | (3B & SEL2)) } + Y4 = { ~((4A & SEL1) | (4B & SEL2)) } * ULS158DLY PINDLY (4,0,10) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + Y1_O Y2_O Y3_O Y4_O = { + CASE( + ENABLE & TRN_HL, DELAY(-1,18NS,24NS), + SELECT & TRN_HL, DELAY(-1,16NS,24NS), + SELECT & TRN_LH, DELAY(-1,13NS,20NS), + ENABLE & TRN_LH, DELAY(-1,11NS,17NS), + DATA & TRN_HL, DELAY(-1,10NS,15NS), + DATA & TRN_LH, DELAY(-1,7NS,12NS), + DELAY(-1,19NS,25NS) + ) + } * .ENDS * *$ *--------- * 74LS160A Synchronous 4-bit Decade Counters with asynchronous clear * * The TTL Data Book, 1986, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS160A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS160ALOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD EN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~LOADBAR } ;Logic expressions + EN = { ENP & ENT & LOADBAR } + QAB = { ~QA } + QBB = { ~QB } + QCB = { ~QC } + QDB = { ~QD } + DA = { (~EN & LOADBAR & QA) | (EN & QAB) | (LOAD & A) } + DB = { (QB & ~(QA & EN) & LOADBAR) | (QA & EN & QDB & QBB) + | (LOAD & B) } + DC = { (QC & ~(QB & QA & EN) & LOADBAR) | (QB & QA & EN & QCB) + | (LOAD & C) } + DD = { (QD & ~(QA & EN) & LOADBAR) | (QC & QB & QA & EN & QDB) + | (LOAD & D) } + RCO = { ENT & QA & QD } * UDFF DFF(4) DPWR DGND $D_HI CLRBAR CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_LS * ULS160ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK LOADBAR ENT CLRBAR ENP A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENT,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(-1,13NS,24NS), + CLOCK & TRN_HL, DELAY(-1,18NS,27NS), + CHANGED_HL(CLRBAR,0), DELAY(-1,20NS,28NS), + DELAY(-1,20NS,28NS) + ) + } + RCO_O = { + CASE( + CNTENT, DELAY(-1,9NS,14NS), + CLOCK & TRN_LH, DELAY(-1,20NS,35NS), + CLOCK & TRN_HL, DELAY(-1,18NS,35NS), + DELAY(-1,20NS,35NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = CLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { CLRBAR!='0 & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) + & CHANGED(EN,20NS) } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { CLRBAR!='0 & (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 25NS * .ENDS * *$ *--------- * 74LS161A Synchronous 4-bit Binary Counter with Direct Clear * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 06/30/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS161A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CLRBAR CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_LS * ULS161ALOG LOGICEXP(17,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + ILD = { ~LOADBAR } + IA1 = { LOADBAR & QA & ~IEN } + IA2 = { IEN & QABAR } + IB1 = { QB & ~(QA & IEN) & LOADBAR } + IB2 = { QA & IEN & QBBAR } + IC1 = { QC & ~(QB & QA & IEN) & LOADBAR } + IC2 = { QB & QA & IEN & QCBAR } + ID1 = { QD & ~(QC & QB & QA & IEN) & LOADBAR } + ID2 = { QC & QB & QA & IEN & QDBAR } + RCO = { QD & QC & QB & QA & ENT } + DA = { IA1 | IA2 | (ILD & A) } + DB = { IB1 | IB2 | (ILD & B) } + DC = { IC1 | IC2 | (ILD & C) } + DD = { ID1 | ID2 | (ILD & D) } * ULS161ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT ENP CLRBAR LOADBAR A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(-1,13NS,24NS), + CLOCK & TRN_HL, DELAY(-1,18NS,27NS), + DELAY(-1,20NS,28NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,9NS,14NS), + CLOCK & TRN_HL, DELAY(-1,18NS,35NS), + CLOCK & TRN_LH, DELAY(-1,20NS,35NS), + DELAY(-1,20NS,35NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = CLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CLRBAR!='0 & + CHANGED(IEN,20NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 25NS * .ENDS * *$ *--------- * 74LS162A Synchronous 4-bit Decade Counters with synchronous clear * * The TTL Data Book, 1986, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS162A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS162ALOG LOGICEXP(13,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD EN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~LOADBAR & ~CLRBAR } ;Logic expressions + ICLR = { ~(~CLRBAR | LOAD) } + EN = { ENP & ENT & LOADBAR & CLRBAR } + QAB = { ~QA } + QBB = { ~QB } + QCB = { ~QC } + QDB = { ~QD } + DA = { (~EN & ICLR & QA) | (EN & QAB) | (LOAD & A) } + DB = { (QB & ~(QA & EN) & ICLR) | (QA & EN & QDB & QBB) + | (LOAD & B) } + DC = { (QC & ~(QB & QA & EN) & ICLR) | (QB & QA & EN & QCB) + | (LOAD & C) } + DD = { (QD & ~(QA & EN) & ICLR) | (QC & QB & QA & EN & QDB) + | (LOAD & D) } + RCO = { ENT & QA & QD } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_LS * ULS162ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT ENP CLRBAR LOADBAR A B C D EN + RCO_O QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(-1,13NS,24NS), + CLOCK & TRN_HL, DELAY(-1,18NS,27NS), + DELAY(-1,18NS,27NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,9NS,14NS), + CLOCK & TRN_LH, DELAY(-1,20NS,35NS), + CLOCK & TRN_HL, DELAY(-1,18NS,35NS), + DELAY(-1,20NS,35NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { CHANGED(EN,20NS) & (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + NOTCLEAR } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 20NS + SETUPTIME_HI = 25NS + HOLDTIME = 3NS * .ENDS * *$ *--------- * 74LS163A Synchronous 4-bit Binary Counter with Direct Clear * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 06/30/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT Devices * .SUBCKT 74LS163A CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_LS * ULS163ALOG LOGICEXP(17,15) DPWR DGND + CLK_I ENP_I ENT_I CLRBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK ENP ENT CLRBAR LOADBAR A B C D RCO DA DB DC DD IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + ENP = { ENP_I } + ENT = { ENT_I } + CLRBAR = { CLRBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { CLRBAR & LOADBAR & ENP & ENT } + ILD = { CLRBAR & ~LOADBAR } + ILC = { ~(~CLRBAR | ILD) } + IA1 = { ILC & QA & ~IEN } + IA2 = { IEN & QABAR } + IB1 = { QB & ~(QA & IEN) & ILC } + IB2 = { QA & IEN & QBBAR } + IC1 = { QC & ~(QB & QA & IEN) & ILC } + IC2 = { QB & QA & IEN & QCBAR } + IDB = { QD & ~(QC & QB & QA & IEN) & ILC } + IDC = { QC & QB & QA & IEN & QDBAR } + RCO = { QD & QC & QB & QA & ENT } + DA = { IA1 | IA2 | (ILD & A) } + DB = { IB1 | IB2 | (ILD & B) } + DC = { IC1 | IC2 | (ILD & C) } + DD = { IDB | IDC | (ILD & D) } * ULS163ADLY PINDLY (5,0,10) DPWR DGND + RCO QA QB QC QD + CLK ENT ENP CLRBAR LOADBAR A B C D IEN + RCO_O QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(-1,13NS,24NS), + CLOCK & TRN_HL, DELAY(-1,18NS,27NS), + DELAY(-1,18NS,27NS) + ) + } + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,9NS,14NS), + CLOCK & TRN_HL, DELAY(-1,18NS,35NS), + CLOCK & TRN_LH, DELAY(-1,20NS,35NS), + DELAY(-1,20NS,35NS) + ) + } + BOOLEAN: + NOTCLEAR = { CLRBAR!='0 ^ CHANGED(CLRBAR,0) } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOTCLEAR } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & NOTCLEAR & CHANGED(IEN,20NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 3NS + WHEN = { NOTCLEAR } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME_LO = 20NS + SETUPTIME_HI = 25NS + HOLDTIME = 3NS * .ENDS * *$ *--------- *74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 6-30-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS164 CLRBAR_I CLK_I A_I B_I QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(4) DPWR DGND + CLRBAR_I CLK_I A_I B_I CLRBAR CLK A B + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U2 AND(2) DPWR DGND + A B IN + D0_GATE IO_LS * U3 DFF(8) DPWR DGND + $D_HI CLRBAR CLK + IN QA QB QC QD QE QF QG + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * * ULS164DLY PINDLY (8,0,4) DPWR DGND + QA QB QC QD QE QF QG QH + CLRBAR CLK A B + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(8NS,17NS,27NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(10NS,21NS,32NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,24NS,36NS), + DELAY(11NS,25NS,37NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 25MEG + + WIDTH: + NODE = CLK + MIN_HIGH = 20NS + MIN_LOW = 20NS + + WIDTH: + NODE = CLRBAR + MIN_LOW = 20NS + + SETUP_HOLD: + CLOCK LH = CLK + DATA(2) A B + SETUPTIME = 15NS + HOLDTIME = 5NS + WHEN = { CLRBAR != '0 } + + SETUP_HOLD: + CLOCK LH = CLK + DATA(1) CLRBAR + RELEASETIME_LH = 20NS * .ENDS * *$ *--------- * 74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 7/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS165A SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + QH_O QHBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS165LOG LOGICEXP(12,29) DPWR DGND + SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + SH/LDBAR CLK_INH CLK SER A B C D E F G H SA SB SC SD SE SF SG SH + RA RB RC RD RE RF RG RH CK + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + + SH/LDBAR = { SH/LDBAR_I } + CLK_INH = { CLK_INH_I } + CLK = { CLK_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + * INTERMEDIATE TERM + LOAD = { ~SH/LDBAR } + + SA = { ~(LOAD & A) } + SB = { ~(LOAD & B) } + SC = { ~(LOAD & C) } + SD = { ~(LOAD & D) } + SE = { ~(LOAD & E) } + SF = { ~(LOAD & F) } + SG = { ~(LOAD & G) } + SH = { ~(LOAD & H) } + + RA = { ~(LOAD & SA) } + RB = { ~(LOAD & SB) } + RC = { ~(LOAD & SC) } + RD = { ~(LOAD & SD) } + RE = { ~(LOAD & SE) } + RF = { ~(LOAD & SF) } + RG = { ~(LOAD & SG) } + RH = { ~(LOAD & SH) } + + CK = { CLK_INH | CLK } * U1 DFF(1) DPWR DGND SA RA CK SER QA $D_NC + D0_EFF IO_LS * U2 DFF(1) DPWR DGND SB RB CK QA QB $D_NC + D0_EFF IO_LS * U3 DFF(1) DPWR DGND SC RC CK QB QC $D_NC + D0_EFF IO_LS * U4 DFF(1) DPWR DGND SD RD CK QC QD $D_NC + D0_EFF IO_LS * U5 DFF(1) DPWR DGND SE RE CK QD QE $D_NC + D0_EFF IO_LS * U6 DFF(1) DPWR DGND SF RF CK QE QF $D_NC + D0_EFF IO_LS * U7 DFF(1) DPWR DGND SG RG CK QF QG $D_NC + D0_EFF IO_LS * U8 DFF(1) DPWR DGND SH RH CK QG QH QHBAR + D0_EFF IO_LS * ULS165DLY PINDLY (2,0,12) DPWR DGND + QH QHBAR + SH/LDBAR CLK H CLK_INH SER A B C D E F G + QH_O QHBAR_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + LMODE = { SH/LDBAR=='0 } + SMODE = { SH/LDBAR=='1 } + CH_H = { CHANGED(H,0) } + CLOCK = { CHANGED_LH(CLK,0) } + LOAD = { CHANGED_HL(SH/LDBAR,0) } + + PINDLY: + QH_O = { + CASE( + CLOCK & SMODE & TRN_LH, DELAY(-1,14NS,25NS), + CLOCK & SMODE & TRN_HL, DELAY(-1,16NS,25NS), + CH_H & LMODE & TRN_LH, DELAY(-1,13NS,25NS), + CH_H & LMODE & TRN_HL, DELAY(-1,24NS,30NS), + LOAD & TRN_LH, DELAY(-1,21NS,35NS), + LOAD & TRN_HL, DELAY(-1,26NS,35NS), + DELAY(-1,27NS,36NS) ;DEFAULT + ) + } + + QHBAR_O = { + CASE( + CLOCK & SMODE & TRN_LH, DELAY(-1,14NS,25NS), + CLOCK & SMODE & TRN_HL, DELAY(-1,16NS,25NS), + CH_H & LMODE & TRN_HL, DELAY(-1,17NS,25NS), + CH_H & LMODE & TRN_LH, DELAY(-1,19NS,30NS), + LOAD & TRN_LH, DELAY(-1,21NS,35NS), + LOAD & TRN_HL, DELAY(-1,26NS,35NS), + DELAY(-1,27NS,36NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 25MEG + + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 15NS + + WIDTH: + NODE = SH/LDBAR + MIN_LO = 25NS + WHEN = { CLK!='0 } + + WIDTH: + NODE = SH/LDBAR + MIN_LO = 17NS + WHEN = { CLK!='1 } + + SETUP_HOLD: + DATA(1) = CLK_INH + CLOCK LH = CLK + SETUPTIME_LO = 30NS + MESSAGE = "CLOCK ENABLE SETUP TIME IS NOT MET" + + SETUP_HOLD: + DATA(1) = SH/LDBAR + CLOCK LH = CLK + SETUPTIME_HI = 45NS + + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { (SH/LDBAR!='0 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: + DATA(8) = A B C D E F G H + CLOCK LH = SH/LDBAR + SETUPTIME = 10NS * .ENDS * *$ *--------- * 74LS166A PARALLEL LOAD 8-BIT SHIFT REGISTERS * * THE TTL DATABOOK, VOL 2, 1985, TI * NH 7-22-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS166A CLRBAR_I SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I + F_I G_I H_I QH_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS166LOG LOGICEXP(20,22) DPWR DGND + CLRBAR_I SH/LDBAR_I CLK_INH_I CLK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + QA QB QC QD QE QF QG + CLRBAR SH/LDBAR CLK_INH CLK SER A B C D E F G H DA DB DC DD DE DF DG DH CK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + CLRBAR = { CLRBAR_I } + SH/LDBAR = { SH/LDBAR_I } + CLK_INH = { CLK_INH_I } + CLK = { CLK_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + * INTERMEDIATE TERM + LOAD = { ~SH/LDBAR } + + DA = { (SH/LDBAR & SER) | (LOAD & A) } + DB = { (SH/LDBAR & QA) | (LOAD & B) } + DC = { (SH/LDBAR & QB) | (LOAD & C) } + DD = { (SH/LDBAR & QC) | (LOAD & D) } + DE = { (SH/LDBAR & QD) | (LOAD & E) } + DF = { (SH/LDBAR & QE) | (LOAD & F) } + DG = { (SH/LDBAR & QF) | (LOAD & G) } + DH = { (SH/LDBAR & QG) | (LOAD & H) } + CK = { CLK | CLK_INH } * U1 DFF(8) DPWR DGND $D_HI CLRBAR CK + DA DB DC DD DE DF DG DH QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS166DLY PINDLY (1,0,13) DPWR DGND + QH + CLRBAR CLK SH/LDBAR CLK_INH SER A B C D E F G H + QH_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QH_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(5NS,11NS,20NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(7NS,14NS,25NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,19NS,30NS), + DELAY(-1,20NS,30NS) ;DEFAULT + ) + } + + BOOLEAN: + ACTIVE_MODE = { CLRBAR!='0 & CLK_INH!='1 } + + FREQ: + NODE = CLK + MAXFREQ = 25MEG + + WIDTH: + NODE = CLK + MIN_HI = 25NS + MIN_LO = 25NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 20NS + + SETUP_HOLD: + DATA(1) SH/LDBAR + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { ACTIVE_MODE } + + SETUP_HOLD: + DATA(8) A B C D E F G H + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { ACTIVE_MODE & (SH/LDBAR!='1 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: + DATA(1) SER + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { ACTIVE_MODE & (SH/LDBAR!='0 ^ CHANGED(SH/LDBAR,0)) } * .ENDS * *$ *--------- * 74LS169B Synchronous 4-Bit Up/Down Binary Counter * * TTL LOGIC DATA BOOK, 1986, TI * tc 07/21/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS169B CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_LS * ULS169BLOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D DA DB DC DD RCOBAR IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + U/DBAR = { U/DBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { ~(ENPBAR | ENTBAR | ~LOADBAR) } + UP = { U/DBAR } + DN = { ~U/DBAR } + IA1 = { QA & IEN } + IA2 = { ~IEN & LOADBAR & QABAR } + IA3 = { (QA & UP) | (DN & QABAR) } + IB1 = { QB & IEN & IA3 } + IB2 = { ~(IEN & IA3) & LOADBAR & QBBAR } + IB3 = { (QB & UP) | (DN & QBBAR) } + IC1 = { QC & IEN & IA3 & IB3 } + IC2 = { ~(IEN & IA3 & IB3) & LOADBAR & QCBAR } + IC3 = { (QC & UP) | (DN & QCBAR) } + ID1 = { QD & IEN & IA3 & IB3 & IC3 } + ID2 = { ~(IEN & IA3 & IB3 & IC3) & LOADBAR & QDBAR } + ID3 = { (QD & UP) | (DN & QDBAR) } + DA = { ~(IA1 | IA2 | ~(LOADBAR | A)) } + DB = { ~(IB1 | IB2 | ~(LOADBAR | B)) } + DC = { ~(IC1 | IC2 | ~(LOADBAR | C)) } + DD = { ~(ID1 | ID2 | ~(LOADBAR | D)) } + RCOBAR = { ~(IA3 & IB3 & IC3 & ID3 & ~ENTBAR) } * ULS169BDLY PINDLY (5,0,10) DPWR DGND + QA QB QC QD RCOBAR + CLK ENTBAR U/DBAR ENPBAR LOADBAR A B C D IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(-1,16NS,25NS), + DELAY(-1,17NS,25NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0) & TRN_HL, DELAY(-1,11NS,20NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED(ENTBAR,0) & TRN_LH, DELAY(-1,15NS,25NS), + CLOCK & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK & TRN_LH, DELAY(-1,26NS,40NS), + DELAY(-1,26NS,40NS) + ) + } + BOOLEAN: + NOTLOADING = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + ENABLE = { (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } + FREQ: + NODE = CLK + MAXFREQ = 20MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { NOTLOADING & CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 35NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 35NS + WHEN = { NOTLOADING & ENABLE } * .ENDS * *$ *--------- * 74LS170 REGISTER FILES 4X4 WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, 1988, TI * JLS 7-23-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS170 GWBAR_I WA_I WB_I GRBAR_I RA_I RB_I D1_I D2_I D3_I D4_I + Q1_O Q2_O Q3_O Q4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UA DLTCH(4) DPWR DGND + $D_HI $D_HI GATEA + D1 D2 D3 D4 + AQ1 AQ2 AQ3 AQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS UB DLTCH(4) DPWR DGND + $D_HI $D_HI GATEB + D1 D2 D3 D4 + BQ1 BQ2 BQ3 BQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS UC DLTCH(4) DPWR DGND + $D_HI $D_HI GATEC + D1 D2 D3 D4 + CQ1 CQ2 CQ3 CQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS UD DLTCH(4) DPWR DGND + $D_HI $D_HI GATED + D1 D2 D3 D4 + DQ1 DQ2 DQ3 DQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS * ULS170LOG LOGICEXP (26,18) DPWR DGND + GWBAR_I WA_I WB_I GRBAR_I RA_I RB_I D1_I D2_I D3_I D4_I + AQ1 AQ2 AQ3 AQ4 BQ1 BQ2 BQ3 BQ4 CQ1 CQ2 CQ3 CQ4 DQ1 DQ2 DQ3 DQ4 + GWBAR WA WB GRBAR RA RB D1 D2 D3 D4 + GATEA GATEB GATEC GATED Q1 Q2 Q3 Q4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + GWBAR = { GWBAR_I } + WA = { WA_I } + WB = { WB_I } + GRBAR = { GRBAR_I } + RA = { RA_I } + RB = { RB_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + ENABLE2 = { ~(GWBAR | WB) } + ENABLE1 = { ~(GWBAR | ENABLE2) } + GATEA = { ENABLE2 & ~WA } + GATEB = { ENABLE2 & WA } + GATEC = { ENABLE1 & ~WA } + GATED = { ENABLE1 & WA } + Q1 = { (AQ1 & ~RA & ~RB) | + (BQ1 & RA & ~RB) | + (CQ1 & ~RA & RB) | + (DQ1 & RA & RB) | + GRBAR + } + Q2 = { (AQ2 & ~RA & ~RB) | + (BQ2 & RA & ~RB) | + (CQ2 & ~RA & RB) | + (DQ2 & RA & RB) | + GRBAR + } + Q3 = { (AQ3 & ~RA & ~RB) | + (BQ3 & RA & ~RB) | + (CQ3 & ~RA & RB) | + (DQ3 & RA & RB) | + GRBAR + } + Q4 = { (AQ4 & ~RA & ~RB) | + (BQ4 & RA & ~RB) | + (CQ4 & ~RA & RB) | + (DQ4 & RA & RB) | + GRBAR + } * ULS170DLY PINDLY (4,0,10) DPWR DGND + Q1 Q2 Q3 Q4 + GWBAR GRBAR RA RB D1 D2 D3 D4 WA WB + Q1_O Q2_O Q3_O Q4_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + WRITEEN = { CHANGED(GWBAR,0) } + READEN = { CHANGED(GRBAR,0) } + READ = { CHANGED(RA,0) | CHANGED(RB,0) } + DATA = { CHANGED(D1,0) | CHANGED(D2,0) | + CHANGED(D3,0) | CHANGED(D4,0) } + + PINDLY: + Q1_O Q2_O Q3_O Q4_O = { + CASE ( + READEN , DELAY(-1,20NS,30NS), + DATA & TRN_HL, DELAY(-1,22NS,35NS), + READ & TRN_HL, DELAY(-1,24NS,40NS), + WRITEEN & TRN_HL, DELAY(-1,26NS,40NS), + READ & TRN_LH, DELAY(-1,25NS,40NS), + DATA & TRN_LH, DELAY(-1,30NS,45NS), + WRITEEN & TRN_LH, DELAY(-1,30NS,45NS), + DELAY(-1,30NS,45NS) + ) + } + + WIDTH: + NODE = GWBAR + MIN_LO = 25NS + WIDTH: + NODE = GRBAR + MIN_LO = 25NS + SETUP_HOLD: + DATA(4) = D1 D2 D3 D4 + CLOCK LH = GWBAR + SETUPTIME = 10NS + HOLDTIME = 15NS + SETUP_HOLD: + DATA(2) = WA WB + CLOCK HL = GWBAR + SETUPTIME = 15NS + HOLDTIME = .1NS ;WA,WB MUST BE STABLE WHILE GWBAR IS LOW + SETUP_HOLD: + DATA(2) = WA WB + CLOCK LH = GWBAR + SETUPTIME = .1NS ;WA,WB MUST BE STABLE WHILE GWBAR IS LOW + HOLDTIME = 5NS + GENERAL: + WHEN = { GWBAR!='1 & (CHANGED(WA,0NS) | CHANGED(WB,0NS)) } + MESSAGE = "WA AND WB MUST BE STABLE WHILE GWBAR IS LOW" * .ENDS * *$ *------------------------------------------------------------------------ * 74LS171 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR * * The TTL Data Book, Vol 2, 1985, TI * tvh 08/16/89 Update interface and model names * .subckt 74LS171 CLRBAR CLK 1D 2D 3D 4D 1Q 2Q 3Q 4Q 1QBAR 2QBAR 3QBAR 4QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 dff(4) DPWR DGND + $D_HI CLRBAR CLK + 1D 2D 3D 4D + 1Q 2Q 3Q 4Q 1QBAR 2QBAR 3QBAR 4QBAR + D_LS171 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS171 ueff ( + TWCLKLMN=20NS TWCLKHMN=20NS + TWPCLMN=20NS TSUDCLKMN=20NS + TSUPCCLKHMN=25NS THDCLKMN=5NS + TPPCQLHTY=18NS TPPCQLHMX=30NS + TPPCQHLTY=24NS TPPCQHLMX=40NS + TPCLKQLHTY=15NS TPCLKQLHMX=25NS + TPCLKQHLTY=18NS TPCLKQHLMX=30NS + ) * *$ *--------- * 74LS173A REGISTERS D-TYPE 4-BIT WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-9-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS173A CLR_I CLK_I G1BAR_I G2BAR_I M_I N_I 1D_I 2D_I 3D_I 4D_I + 1Q_O 2Q_O 3Q_O 4Q_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND + $D_HI CLRBAR CLK + DFF1 DFF2 DFF3 DFF4 + 1Q 2Q 3Q 4Q + $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS173ALOG LOGICEXP (14,13) DPWR DGND + CLR_I CLK_I G1BAR_I G2BAR_I M_I N_I 1D_I 2D_I 3D_I 4D_I 1Q 2Q 3Q 4Q + CLR CLRBAR CLK DATEN OE 1D 2D 3D 4D + DFF1 DFF2 DFF3 DFF4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + CLR = { CLR_I } + CLRBAR = { ~CLR } + CLK = { CLK_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + M = { M_I } + N = { N_I } + 1D = { 1D_I } + 2D = { 2D_I } + 3D = { 3D_I } + 4D = { 4D_I } + + DATENBAR = { G1BAR | G2BAR } + DATEN = { ~DATENBAR } + OE = { ~(M | N) } + DFF1 = { (1D & DATEN) | (1Q & DATENBAR) } + DFF2 = { (2D & DATEN) | (2Q & DATENBAR) } + DFF3 = { (3D & DATEN) | (3Q & DATENBAR) } + DFF4 = { (4D & DATEN) | (4Q & DATENBAR) } * ULS173ADLY PINDLY (4,1,7) DPWR DGND + 1Q 2Q 3Q 4Q + OE + CLK CLR DATEN 1D 2D 3D 4D + 1Q_O 2Q_O 3Q_O 4Q_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED = { CHANGED_LH(CLK,0) } + + TRISTATE: + ENABLE HI OE + 1Q_O 2Q_O 3Q_O 4Q_O = { + CASE ( + TRN_ZH, DELAY(-1,15NS,23NS), + TRN_ZL, DELAY(-1,18NS,27NS), + TRN_HZ, DELAY(-1,11NS,20NS), + TRN_LZ, DELAY(-1,11NS,17NS), + TRN_LH, DELAY(-1,17NS,25NS), + CLOCKED & TRN_HL, DELAY(-1,22NS,30NS), + DELAY(-1,26NS,35NS) + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 30MEGHZ + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = CLR + MIN_HI = 25NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = CLK + RELEASETIME_HL = 10NS + SETUP_HOLD: + DATA(1) = DATEN + CLOCK LH = CLK + SETUPTIME = 35NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(4) = 1D 2D 3D 4D + CLOCK LH = CLK + SETUPTIME = 17NS + HOLDTIME = 3NS + WHEN = { CLR!='1 & (DATEN!='0 ^ CHANGED(DATEN,0)) } * .ENDS * *$ *---------- * 74LS174 HEX D-TYPE FLIP-FLOPS WITH CLEAR * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/27/89 Update interface and model names * .subckt 74LS174 CLRBAR CLK D1 D2 D3 D4 D5 D6 Q1 Q2 Q3 Q4 Q5 Q6 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(6) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 + Q1 Q2 Q3 Q4 Q5 Q6 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_LS174 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS174 ueff ( + TWCLKLMN=20NS TWCLKHMN=20NS + TWPCLMN=20NS TSUDCLKMN=20NS + TSUPCCLKHMN=25NS THDCLKMN=5NS + TPPCQHLTY=23NS TPPCQHLMX=35NS + TPCLKQLHTY=20NS TPCLKQLHMX=30NS + TPCLKQHLTY=21NS TPCLKQHLMX=30NS + ) *$ *---------- * 74LS175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/27/89 Update interface and model names * .subckt 74LS175 CLRBAR CLK D1 D2 D3 D4 Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(4) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 + Q1 Q2 Q3 Q4 Q1BAR Q2BAR Q3BAR Q4BAR + D_LS175 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS175 ueff ( + TWCLKLMN=20NS TWCLKHMN=20NS + TWPCLMN=20NS TSUDCLKMN=20NS + TSUPCCLKHMN=25NS THDCLKMN=5NS + TPPCQLHTY=20NS TPPCQLHMX=30NS + TPPCQHLTY=20NS TPPCQHLMX=30NS + TPCLKQLHTY=13NS TPCLKQLHMX=25NS + TPCLKQHLTY=16NS TPCLKQHLMX=25NS + ) *$ *--------- * 74LS181 ALU / FUNCTION GENERATOR * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-4-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES .SUBCKT 74LS181 A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I + B3BAR_I S0_I S1_I S2_I S3_I M_I CN_I F0BAR_O F1BAR_O F2BAR_O F3BAR_O + AEQUALB_O PBAR_O GBAR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 ULS181LOG LOGICEXP (14,22) DPWR DGND + A0BAR_I A1BAR_I A2BAR_I A3BAR_I B0BAR_I B1BAR_I B2BAR_I B3BAR_I + S0_I S1_I S2_I S3_I M_I CN_I + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR + S0 S1 S2 S3 M CN + F0BAR F1BAR F2BAR F3BAR AEQUALB PBAR GBAR CN+4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + A0BAR = { A0BAR_I } + A1BAR = { A1BAR_I } + A2BAR = { A2BAR_I } + A3BAR = { A3BAR_I } + B0BAR = { B0BAR_I } + B1BAR = { B1BAR_I } + B2BAR = { B2BAR_I } + B3BAR = { B3BAR_I } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + S3 = { S3_I } + M = { M_I } + CN = { CN_I } + + TOP3 = { ~( (A3BAR & B3BAR & S3) | (A3BAR & ~B3BAR & S2) ) } + BOT3 = { ~( (~B3BAR & S1) | A3BAR | (B3BAR & S0) ) } + TOP2 = { ~( (A2BAR & B2BAR & S3) | (A2BAR & ~B2BAR & S2) ) } + BOT2 = { ~( (~B2BAR & S1) | A2BAR | (B2BAR & S0) ) } + TOP1 = { ~( (A1BAR & B1BAR & S3) | (A1BAR & ~B1BAR & S2) ) } + BOT1 = { ~( (~B1BAR & S1) | A1BAR | (B1BAR & S0) ) } + TOP0 = { ~( (A0BAR & B0BAR & S3) | (A0BAR & ~B0BAR & S2) ) } + BOT0 = { ~( (~B0BAR & S1) | A0BAR | (B0BAR & S0) ) } + MBAR = { ~M } + + F3BAR = { (TOP3 ^ BOT3) ^ ~( ( CN & MBAR & TOP2 & TOP1 & TOP0) | + (BOT0 & MBAR & TOP2 & TOP1) | + (BOT1 & MBAR & TOP2) | + (BOT2 & MBAR) ) } + F2BAR = { (TOP2 ^ BOT2) ^ ~( ( CN & MBAR & TOP1 & TOP0) | + (BOT0 & MBAR & TOP1) | + (BOT1 & MBAR) ) } + F1BAR = { (TOP1 ^ BOT1) ^ ~( ( CN & MBAR & TOP0) | + (BOT0 & MBAR) ) } + F0BAR = { (TOP0 ^ BOT0) ^ ~( CN & MBAR) } + AEQUALB = { F3BAR & F2BAR & F1BAR & F0BAR } + PBAR = { ~( TOP3 & TOP2 & TOP1 & TOP0) } + GBAR = { ~( (BOT0 & TOP3 & TOP2 & TOP1) | + (BOT1 & TOP3 & TOP2) | + (BOT2 & TOP3) | + BOT3 ) } + CN+4 = { ~GBAR | (~PBAR & CN) } ULS181DLY PINDLY (7,0,14) DPWR DGND + F0BAR F1BAR F2BAR F3BAR PBAR GBAR CN+4 + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M CN + F0BAR_O F1BAR_O F2BAR_O F3BAR_O PBAR_O GBAR_O CN+4_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + SUM = { OPER & NOTM & S0=='1 & S1=='0 & S2=='0 & S3=='1 } + DIF = { OPER & NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + F0BAR_O F1BAR_O F2BAR_O F3BAR_O = { + CASE ( + NOTM & CARRY & TRN_LH, DELAY(-1,17NS,26NS), + NOTM & CARRY & TRN_HL, DELAY(-1,13NS,20NS), + SUM & TRN_LH, DELAY(-1,21NS,32NS), + SUM & TRN_HL, DELAY(-1,13NS,20NS), + DIF , DELAY(-1,21NS,32NS), + TRN_LH, DELAY(-1,22NS,33NS), + TRN_HL, DELAY(-1,26NS,38NS), + DELAY(-1,26NS,38NS) + ) + } + PBAR_O = { + CASE ( + SUM | TRN_LH, DELAY(-1,20NS,30NS), + DELAY(-1,22NS,33NS) + ) + } + GBAR_O = { + CASE ( + SUM & TRN_LH, DELAY(-1,19NS,29NS), + SUM & TRN_HL, DELAY(-1,15NS,23NS), + DELAY(-1,21NS,32NS) + ) + } + CN+4_O = { + CASE ( + CARRY & TRN_LH, DELAY(-1,18NS,27NS), + CARRY & TRN_HL, DELAY(-1,13NS,20NS), + SUM , DELAY(-1,25NS,38NS), + DELAY(-1,27NS,41NS) + ) + } ULS181DLY_OC PINDLY (1,0,13) DPWR DGND + AEQUALB + A0BAR A1BAR A2BAR A3BAR B0BAR B1BAR B2BAR B3BAR S0 S1 S2 S3 M + AEQUALB_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + OPER = { CHANGED(A3BAR,0) | CHANGED(B3BAR,0) | + CHANGED(A2BAR,0) | CHANGED(B2BAR,0) | + CHANGED(A1BAR,0) | CHANGED(B1BAR,0) | + CHANGED(A0BAR,0) | CHANGED(B0BAR,0) } + NOTM = { M=='0 } + DIF = { OPER & NOTM & S0=='0 & S1=='1 & S2=='1 & S3=='0 } + + PINDLY: + AEQUALB_O = { + CASE ( + DIF & TRN_LH, DELAY(-1,33NS,50NS), + DELAY(-1,41NS,62NS) + ) + } .ENDS *$ *--------- * 74LS183 DUAL CARRY-SAVE FULL ADDERS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/26/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS183 CN_I B_I A_I SUM_O CN+1_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS183LOG LOGICEXP(3,5) DPWR DGND + CN_I B_I A_I + CN B A SUM CN+1 + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + CN = { CN_I } + B = { B_I } + A = { A_I } + + CNBAR = { ~CN } + BBAR = { ~B } + ABAR = { ~A } + + CN+1 = { ~((CNBAR & BBAR) | (BBAR & ABAR) | (CNBAR & ABAR)) } + SUM = { ~((CN & BBAR & A) | (CNBAR & B & A) | (CNBAR & BBAR & ABAR) | + (CN & B & ABAR)) } * ULS183DLY PINDLY (2,0,3) DPWR DGND + SUM CN+1 + CN A B + SUM_O CN+1_O + IO_LS MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(CN,0) } + + PINDLY: + SUM_O CN+1_O = { + CASE( + ANY_CH & TRN_LH, DELAY(-1,9NS,15NS), + ANY_CH & TRN_HL, DELAY(-1,20NS,33NS), + DELAY(-1,21NS,34NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS190 Synchronous 4-bit Up/Down Decade Counters * * The TTL Data Book, 1988, TI * JSW 7/15/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS190 CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I + RCOBAR_O MXMNOUT_O QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS190 LOGICEXP (16,23) DPWR DGND + CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD QABAR QBBAR + QCBAR QDBAR + CLK CLKBAR DUBAR CTENBAR LOADBAR A B C D MXMNOUT RCOBAR + SA RA JKA SB RB JKB SC RC JKC SD RD JKD + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + CLK = { CLK_I } + CLKBAR = { ~CLK_I } + DUBAR = { DUBAR_I } + CTENBAR = { CTENBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + DU = { ~DUBAR } + LOAD = { ~LOADBAR } + CTEN = { ~CTENBAR } + CTD = { DUBAR & CTEN } + CTU = { DU & CTEN } + MXMNOUT = { (QA & QD & DU) | (QABAR & QBBAR & QCBAR & + QDBAR & DUBAR) } + RCOBAR = { ~(MXMNOUT & CTEN & CLKBAR) } + SA = { ~(A & LOAD) } + RA = { ~(SA & LOAD) } + JKA = { CTEN } + SB = { ~(B & LOAD) } + RB = { ~(SB & LOAD) } + IB = { ~(QBBAR & QCBAR & QDBAR) } + JKB = { (CTD & QABAR & IB) | (QA & QDBAR & CTU) } + SC = { ~(C & LOAD) } + RC = { ~(SC & LOAD) } + JKC = { (CTD & QABAR & QBBAR & IB) | (CTU & QB & QA) } + SD = { ~(D & LOAD) } + RD = { ~(SD & LOAD) } + JKD = { (CTD & QABAR & QBBAR & QCBAR) | (CTU & QD & QA) | + (CTU & QC & QB & QA) } * UJKFFA JKFF(1) DPWR DGND SA RA CLKBAR JKA JKA QA QABAR D0_EFF IO_LS UJKFFB JKFF(1) DPWR DGND SB RB CLKBAR JKB JKB QB QBBAR D0_EFF IO_LS UJKFFC JKFF(1) DPWR DGND SC RC CLKBAR JKC JKC QC QCBAR D0_EFF IO_LS UJKFFD JKFF(1) DPWR DGND SD RD CLKBAR JKD JKD QD QDBAR D0_EFF IO_LS * ULS190DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD RCOBAR MXMNOUT + A B C D CLK DUBAR CTENBAR LOADBAR + QA_O QB_O QC_O QD_O RCOBAR_O MXMNOUT_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + ABCD = { (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0)) + & LOADBAR!='1 } + CLOCK_LH = { CHANGED_LH(CLK,0) & TRN_LH } + CLOCK_HL = { CHANGED_LH(CLK,0) & TRN_HL } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK_LH, DELAY(-1,16NS,24NS), + ABCD & TRN_LH, DELAY(-1,20NS,32NS), + CHANGED_HL(LOADBAR,0) & TRN_LH, DELAY(-1,22NS,33NS), + CLOCK_HL, DELAY(-1,24NS,36NS), + CHANGED_HL(LOADBAR,0) & TRN_HL, DELAY(-1,33NS,50NS), + ABCD & TRN_HL, DELAY(-1,27NS,40NS), + DELAY(-1,35NS,50NS) + ) + } + RCOBAR_O = { + CASE( + CLOCK_LH, DELAY(-1,13NS,20NS), + CHANGED(CLK,0) & TRN_HL, DELAY(-1,16NS,24NS), + CHANGED(CTENBAR,0) & TRN_LH, DELAY(-1,21NS,33NS), + CHANGED(CTENBAR,0) & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(DUBAR,0), DELAY(-1,30NS,45NS), + DELAY(-1,30NS,45NS) + ) + } + MXMNOUT_O = { + CASE( + CHANGED(DUBAR,0) & TRN_LH, DELAY(-1,21NS,33NS), + CHANGED(DUBAR,0) & TRN_HL, DELAY(-1,22NS,33NS), + CLOCK_LH, DELAY(-1,28NS,42NS), + CLOCK_HL, DELAY(-1,37NS,52NS), + DELAY(-1,22NS,33NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 20MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = LOADBAR + MIN_LO = 35NS + SETUP_HOLD: + DATA(1) CTENBAR + CLOCK LH = CLK + SETUPTIME_LO = 40NS + WHEN = { LOADBAR!='0 } + MESSAGE = "Count Enable Time too short" + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + RELEASETIME_LH = 30NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS * .ENDS * *$ *--------- * 74LS191 Synchronous 4-bit Up/Down Binary Counters * * THE TTL DATA BOOK, 1988, TI * tc 7/23/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS191 CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I + RCOBAR_O MXMNOUT_O QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND SA RA MCLK JKA JKA QA QABAR + D0_EFF IO_LS U2 JKFF(1) DPWR DGND SB RB MCLK JKB JKB QB QBBAR + D0_EFF IO_LS U3 JKFF(1) DPWR DGND SC RC MCLK JKC JKC QC QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND SD RD MCLK JKD JKD QD QDBAR + D0_EFF IO_LS * ULS191LOG LOGICEXP (16,23) DPWR DGND + CLK_I DUBAR_I CTENBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK DUBAR CTENBAR LOADBAR A B C D MXMNOUT RCOBAR MCLK + SA RA JKA SB RB JKB SC RC JKC SD RD JKD + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + DUBAR = { DUBAR_I } + CTENBAR = { CTENBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN1 = { ~(DUBAR | CTENBAR) } + IEN2 = { ~(CTENBAR | ~DUBAR) } + ILD = { ~LOADBAR } + IM1 = { ~DUBAR & QA & QB & QC & QD } + IM2 = { DUBAR & QABAR & QBBAR & QCBAR & QDBAR } + IC1 = { IEN2 & QABAR & QBBAR } + IC2 = { IEN1 & QA & QB } + ID1 = { IEN2 & QABAR & QBBAR & QCBAR } + ID2 = { IEN1 & QA & QB & QC } + MCLK = { ~CLK } + SA = { ~(A & ILD) } + RA = { ~(SA & ILD) } + SB = { ~(B & ILD) } + RB = { ~(SB & ILD) } + SC = { ~(C & ILD) } + RC = { ~(SC & ILD) } + SD = { ~(D & ILD) } + RD = { ~(SD & ILD) } + JKA = { ~CTENBAR } + JKB = { (IEN2 & QABAR) | (QA & IEN1) } + JKC = { IC1 | IC2 } + JKD = { ID1 | ID2 } + MXMNOUT = { IM1 | IM2 } + RCOBAR = { ~(MCLK & JKA & MXMNOUT) } * ULS191DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD RCOBAR MXMNOUT + A B C D CLK DUBAR CTENBAR LOADBAR + QA_O QB_O QC_O QD_O RCOBAR_O MXMNOUT_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + DATA = { (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) | CHANGED(D,0)) + & LOADBAR!='1 } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLOCK & TRN_LH, DELAY(-1,16NS,24NS), + DATA & TRN_LH, DELAY(-1,20NS,32NS), + CHANGED_HL(LOADBAR,0) & TRN_LH, DELAY(-1,22NS,33NS), + CLOCK & TRN_HL, DELAY(-1,24NS,36NS), + CHANGED_HL(LOADBAR,0) & TRN_HL, DELAY(-1,33NS,50NS), + DATA & TRN_HL, DELAY(-1,27NS,40NS), + DELAY(-1,35NS,50NS) + ) + } + RCOBAR_O = { + CASE( + CHANGED(CLK,0) & TRN_LH, DELAY(-1,13NS,20NS), + CHANGED(CLK,0) & TRN_HL, DELAY(-1,16NS,24NS), + CHANGED(CTENBAR,0) & TRN_LH, DELAY(-1,21NS,33NS), + CHANGED(CTENBAR,0) & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(DUBAR,0), DELAY(-1,30NS,45NS), + DELAY(-1,30NS,45NS) + ) + } + MXMNOUT_O = { + CASE( + CHANGED(DUBAR,0) & TRN_LH, DELAY(-1,21NS,33NS), + CHANGED(DUBAR,0) & TRN_HL, DELAY(-1,22NS,33NS), + CLOCK & TRN_LH, DELAY(-1,28NS,42NS), + CLOCK & TRN_HL, DELAY(-1,37NS,52NS), + DELAY(-1,37NS,52NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 20MEG + WIDTH: + NODE = CLK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = LOADBAR + MIN_LO = 35NS + SETUP_HOLD: + DATA(1) = CTENBAR + CLOCK LH = CLK + SETUPTIME_LO = 40NS + WHEN = { LOADBAR!='0 } + MESSAGE = "Count Enable Time too short" + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + RELEASETIME_LH = 30NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS * .ENDS * *$ *--------- * 74LS192 Synchronous 4-bit Up/Down Decade Counters (Dual clock w/ clear) * * THE TTL DATA BOOK, 1988, TI * JSW 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS192 UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND SA RA TA $D_HI $D_HI QA QABAR + D0_EFF IO_LS U2 JKFF(1) DPWR DGND SB RB TB $D_HI $D_HI QB QBBAR + D0_EFF IO_LS U3 JKFF(1) DPWR DGND SC RC TC $D_HI $D_HI QC QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND SD RD TD $D_HI $D_HI QD QDBAR + D0_EFF IO_LS * ULS192LOG LOGICEXP (16,23) DPWR DGND + UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD QABAR QBBAR + QCBAR QDBAR + UP DOWN CLR LOADBAR A B C D TA TB TC TD BOBAR COBAR MCLR + SA RA SB RB SC RC SD RD + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + UP = { UP_I } + DOWN = { DOWN_I } + CLR = { CLR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ID = { ~DOWN } + IU = { ~UP } + ILD = { ~LOADBAR } + MCLR = { ~CLR } + IN1 = { ~(QBBAR & QCBAR & QDBAR) } + TA = { ID | IU } + TB = { (ID & QABAR & IN1) | (IU & QA & QDBAR) } + TC = { (ID & QABAR & QBBAR & IN1) | (IU & QA & QB) } + TD = { (ID & QABAR & QBBAR & QCBAR) | (IU & QD & QA ) | + (IU & QA & QB & QC) } + SA = { ~(A & ILD & MCLR) } + RA = { MCLR & ~(SA & ILD) } + SB = { ~(B & ILD & MCLR) } + RB = { MCLR & ~(SB & ILD) } + SC = { ~(C & ILD & MCLR) } + RC = { MCLR & ~(SC & ILD) } + SD = { ~(D & ILD & MCLR) } + RD = { MCLR & ~(SD & ILD) } + BOBAR = { ~(ID & QABAR & QBBAR & QCBAR & QDBAR) } + COBAR = { ~(IU & QA & QD) } * ULS192DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD BOBAR COBAR + UP DOWN LOADBAR CLR A B C D + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + UPDN = { (CHANGED_LH(UP,0) | CHANGED_LH(DOWN,0)) & LOADBAR!='0 + & CLR!='1 } + CLEAR = { CHANGED_LH(CLR,0) } + LOAD = { CHANGED_HL(LOADBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLEAR, DELAY(-1,23NS,35NS), + UPDN & TRN_LH, DELAY(-1,27NS,38NS), + LOAD & TRN_LH, DELAY(-1,24NS,40NS), + LOAD & TRN_HL, DELAY(-1,25NS,40NS), + UPDN & TRN_HL, DELAY(-1,30NS,47NS), + DELAY(-1,31NS,47NS) + ) + } + BOBAR_O = { + CASE( + CHANGED(DOWN,0) & TRN_HL, DELAY(-1,15NS,24NS), + CHANGED(DOWN,0) & TRN_LH, DELAY(-1,16NS,24NS), + CLEAR, DELAY(-1,23NS,35NS), + LOAD & TRN_LH, DELAY(24NS,-1,40NS), + LOAD & TRN_HL, DELAY(25NS,-1,40NS), + DELAY(25NS,-1,40NS) + ) + } + COBAR_O = { + CASE( + CHANGED(UP,0) & TRN_HL, DELAY(-1,18NS,24NS), + CHANGED(UP,0) & TRN_LH, DELAY(-1,17NS,26NS), + CLEAR, DELAY(-1,23NS,35NS), + LOAD & TRN_LH, DELAY(24NS,-1,40NS), + LOAD & TRN_HL, DELAY(25NS,-1,40NS), + DELAY(25NS,-1,40NS) + ) + } + FREQ: + NODE = UP + MAXFREQ = 25MEG + FREQ: + NODE = DOWN + MAXFREQ = 25MEG + WIDTH: + NODE = UP + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = DOWN + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + WHEN = { CLR!='1 } + WIDTH: + NODE = CLR + MIN_HI = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = UP + RELEASETIME_HL = 15NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = DOWN + RELEASETIME_HL = 15NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = UP + RELEASETIME_LH = 15NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = DOWN + RELEASETIME_LH = 15NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS + WHEN = { CLR!='1 } * .ENDS * *$ *--------- * 74LS193 Synchronous 4-bit Up/Down Binary Counters (Dual clock w/ clear) * * THE TTL DATA BOOK, 1988, TI * tc 7/27/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * * NOTE: The propagation delay from LOADBAR and CLR to COBAR and BOBAR was * assumed to be the same as the LOADBAR and CLR to Q delay. * .SUBCKT 74LS193 UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND SA RA TA $D_HI $D_HI QA QABAR + D0_EFF IO_LS U2 JKFF(1) DPWR DGND SB RB TB $D_HI $D_HI QB QBBAR + D0_EFF IO_LS U3 JKFF(1) DPWR DGND SC RC TC $D_HI $D_HI QC QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND SD RD TD $D_HI $D_HI QD QDBAR + D0_EFF IO_LS * ULS193LOG LOGICEXP (16,23) DPWR DGND + UP_I DOWN_I CLR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + UP DOWN CLR LOADBAR A B C D TA TB TC TD BOBAR COBAR MCLR + SA RA SB RB SC RC SD RD + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + UP = { UP_I } + DOWN = { DOWN_I } + CLR = { CLR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ID = { ~DOWN } + IU = { ~UP } + ILD = { ~LOADBAR } + MCLR = { ~CLR } + TA = { ID | IU } + TB = { (ID & QABAR) | (IU & QA) } + TC = { (ID & QABAR & QBBAR) | (IU & QA & QB) } + TD = { (ID & QABAR & QBBAR & QCBAR) | (IU & QA & QB & QC) } + SA = { ~(A & ILD & MCLR) } + RA = { MCLR & ~(SA & ILD) } + SB = { ~(B & ILD & MCLR) } + RB = { MCLR & ~(SB & ILD) } + SC = { ~(C & ILD & MCLR) } + RC = { MCLR & ~(SC & ILD) } + SD = { ~(D & ILD & MCLR) } + RD = { MCLR & ~(SD & ILD) } + BOBAR = { ~(ID & QABAR & QBBAR & QCBAR & QDBAR) } + COBAR = { ~(IU & QA & QB & QC & QD) } * ULS193DLY PINDLY (6,0,8) DPWR DGND + QA QB QC QD BOBAR COBAR + UP DOWN LOADBAR CLR A B C D + QA_O QB_O QC_O QD_O BOBAR_O COBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + UPDN = { (CHANGED_LH(UP,0) | CHANGED_LH(DOWN,0)) & LOADBAR!='0 + & CLR!='1 } + CLEAR = { CHANGED_LH(CLR,0) } + LOAD = { CHANGED_HL(LOADBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CLEAR, DELAY(-1,23NS,35NS), + UPDN & TRN_LH, DELAY(-1,27NS,38NS), + LOAD & TRN_LH, DELAY(-1,24NS,40NS), + LOAD & TRN_HL, DELAY(-1,25NS,40NS), + UPDN & TRN_HL, DELAY(-1,30NS,47NS), + DELAY(-1,31NS,47NS) + ) + } + BOBAR_O = { + CASE( + CHANGED(DOWN,0) & TRN_LH, DELAY(-1,16NS,24NS), + CHANGED(DOWN,0) & TRN_HL, DELAY(-1,15NS,24NS), + CLEAR, DELAY(-1,23NS,35NS), + LOAD & TRN_LH, DELAY(-1,24NS,40NS), + LOAD & TRN_HL, DELAY(-1,25NS,40NS), + DELAY(-1,25NS,40NS) + ) + } + COBAR_O = { + CASE( + CHANGED(UP,0) & TRN_LH, DELAY(-1,17NS,26NS), + CHANGED(UP,0) & TRN_HL, DELAY(-1,18NS,24NS), + CLEAR, DELAY(-1,23NS,35NS), + LOAD & TRN_LH, DELAY(-1,24NS,40NS), + LOAD & TRN_HL, DELAY(-1,25NS,40NS), + DELAY(-1,25NS,40NS) + ) + } + FREQ: + NODE = UP + MAXFREQ = 25MEG + FREQ: + NODE = DOWN + MAXFREQ = 25MEG + WIDTH: + NODE = UP + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = DOWN + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + WHEN = { CLR!='1 } + WIDTH: + NODE = CLR + MIN_HI = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = UP + RELEASETIME_HL = 15NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK LH = DOWN + RELEASETIME_HL = 15NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = UP + RELEASETIME_LH = 15NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = DOWN + RELEASETIME_LH = 15NS + WHEN = { CLR!='1 } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = LOADBAR + SETUPTIME = 20NS + HOLDTIME = 5NS + WHEN = { CLR!='1 } * .ENDS * *$ *--------- * 74LS194A 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1988, TI * NH 7/7/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS194A CLK_I CLRBAR_I S1_I S0_I SL_I SR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS194LOG LOGICEXP(14,19) DPWR DGND + CLK_I CLRBAR_I S1_I S0_I SL_I SR_I A_I B_I C_I D_I QA QB QC QD + CLK CLRBAR S1 S0 SL SR A B C D KA KB KC KD JA JB JC JD CLOCK + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: * * INTERMEDIATE TERM + LOAD = { S1_I & S0_I } + SRIGHT = { ~S1_I & S0_I } + SLEFT = { S1_I & ~S0_I } + HOLD = { ~S1_I & ~S0_I } * * OUTPUT ASSIGNMENT * + CLK = { CLK_I } + CLRBAR = { CLRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + SL = { SL_I } + SR = { SR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + + KA = { ~( (SR & SRIGHT) | (LOAD & A) | (SLEFT & QB) | (HOLD & QA) ) } + KB = { ~( (QA & SRIGHT) | (LOAD & B) | (SLEFT & QC) | (HOLD & QB) ) } + KC = { ~( (QB & SRIGHT) | (LOAD & C) | (SLEFT & QD) | (HOLD & QC) ) } + KD = { ~( (QC & SRIGHT) | (LOAD & D) | (SLEFT & SL) | (HOLD & QD) ) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } + CLOCK = { ~CLK } * U1 JKFF(4) DPWR DGND $D_HI CLRBAR CLOCK JA JB JC JD KA KB KC KD + QA QB QC QD $D_NC $D_NC $D-NC $D_NC + D0_EFF IO_LS * ULS194DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + CLK CLRBAR S0 S1 SL SR A B C D + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + CLEAR = { CLRBAR!='1 } + + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,14NS,22NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,17NS,26NS), + CHANGED_HL(CLRBAR,0), DELAY(-1,19NS,30NS), + DELAY(8NS,20NS,31NS) ;DEFAULT + ) + } + + BOOLEAN: + NOT_CLEAR = { CLRBAR!='0 } + + FREQ: + NODE = CLK + MAXFREQ = 25MEG + + WIDTH: + NODE = CLK + MIN_HI = 20NS + MIN_LO = 20NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 20NS + + SETUP_HOLD: + DATA(2) S0 S1 + CLOCK LH = CLK + SETUPTIME = 30NS + WHEN = { NOT_CLEAR } + + SETUP_HOLD: + DATA(1) SL + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { NOT_CLEAR & (S1!='0 ^ CHANGED(S1,0)) & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) SR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { NOT_CLEAR & (S1!='1 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(4) A B C D + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { NOT_CLEAR & (S1!='0 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 25NS * .ENDS * *$ *---------- * 74LS195A 4-BIT PARALLEL-ACCESS SHIFT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1988, STANDARD, LS, S, TI * NH 7/6/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS195A CLK_I SH/LDBAR_I CLRBAR_I J_I KBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O QDBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS195LOG LOGICEXP(13,18) DPWR DGND + CLK_I SH/LDBAR_I CLRBAR_I J_I KBAR_I A_I B_I C_I D_I QA QB QC QABAR + CLK SH/LDBAR CLRBAR J KBAR A B C D KA KB KC KD JA JB JC JD CLKBAR + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + CLK = { CLK_I } + SH/LDBAR = { SH/LDBAR_I } + CLRBAR = { CLRBAR_I } + J = { J_I } + KBAR = { KBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERM + LOAD = { ~SH/LDBAR } + + KA = { ~((QABAR & J & SH/LDBAR) | (SH/LDBAR & KBAR & QA) | (LOAD & A)) } + KB = { ~( (QA & SH/LDBAR) | (LOAD & B) ) } + KC = { ~( (QB & SH/LDBAR) | (LOAD & C) ) } + KD = { ~( (QC & SH/LDBAR) | (LOAD & D) ) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } + CLKBAR = { ~CLK } * U1 JKFF(4) DPWR DGND $D_HI CLRBAR CLKBAR JA JB JC JD KA KB KC KD + QA QB QC QD QABAR $D_NC $D_NC QDBAR + D0_EFF IO_LS * ULS195DLY PINDLY (5,0,9) DPWR DGND + QA QB QC QD QDBAR + CLK CLRBAR SH/LDBAR J KBAR A B C D + QA_O QB_O QC_O QD_O QDBAR_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + QA_O QB_O QC_O QD_O QDBAR_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,14NS,22NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,17NS,26NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,19NS,30NS), + DELAY(9NS,20NS,31NS) ;DEFAULT + ) + } + + BOOLEAN: + NOT_CLEAR = { CLRBAR!='0 } + + FREQ: + NODE = CLK + MAXFREQ = 30MEG + + WIDTH: + NODE = CLK + MIN_HI = 16NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 12NS + + SETUP_HOLD: + DATA(1) SH/LDBAR + CLOCK LH = CLK + SETUPTIME_LO = 25NS + SETUPTIME_HI = 20NS + WHEN = { NOT_CLEAR } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 25NS + + SETUP_HOLD: ;SHIFT MODE + DATA(2) J KBAR ;WHEN SH/LDBAR = 1 OR + CLOCK LH = CLK ;AT THE TRANSITION FROM H TO L + SETUPTIME = 15NS + WHEN = { NOT_CLEAR & (SH/LDBAR!='0 ^ CHANGED(SH/LDBAR,0)) } + + SETUP_HOLD: ;LOAD MODE + DATA(4) A B C D ;WHEN SH/LDBAR = 0 OR + CLOCK LH = CLK ;AT THE TRANSITION FROM L TO H + SETUPTIME = 15NS + WHEN = { NOT_CLEAR & (SH/LDBAR!='1 ^ CHANGED(SH/LDBAR,0)) } * .ENDS * *$ *--------- * 74LS196 4-Bit Presettable Decade Counter/Latch * * The TTL Data Book, 1988, TI * JSW 8/3/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS196 LOADBAR_I CLRBAR_I CLK1_I CLK2_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS196LOG LOGICEXP(10,17) DPWR DGND + LOADBAR_I CLRBAR_I CLK1_I CLK2_I A_I B_I C_I D_I QB QC + LOADBAR CLRBAR CLK1 CLK2 A B C D JD SA SB SC SD RA RB RC RD + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + LOADBAR = { LOADBAR_I } + CLRBAR = { CLRBAR_I } + CLK1 = { CLK1_I } + CLK2 = { CLK2_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~CLRBAR | ~LOADBAR } + SA = { ~(A & LOAD & CLRBAR) } + SB = { ~(B & LOAD & CLRBAR) } + SC = { ~(C & LOAD & CLRBAR) } + SD = { ~(D & LOAD & CLRBAR) } + RA = { ~(SA & LOAD) } + RB = { ~(SB & LOAD) } + RC = { ~(SC & LOAD) } + RD = { ~(SD & LOAD) } + JD = { QB & QC } * UJK1 JKFF(1) DPWR DGND SA RA CLK1 $D_HI $D_HI QA $D_NC D0_EFF IO_LS UJK2 JKFF(1) DPWR DGND SB RB CLK2 QDBAR QDBAR QB $D_NC D0_EFF IO_LS UJK3 JKFF(1) DPWR DGND SC RC QB $D_HI $D_HI QC $D_NC D0_EFF IO_LS UJK4 JKFF(1) DPWR DGND SD RD CLK2 JD QD QD QDBAR D0_EFF IO_LS * ULS196DLY PINDLY (4,0,8) DPWR DGND + QA QB QC QD + CLK1 CLK2 A B C D LOADBAR CLRBAR + QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLEAR = { CHANGED(CLRBAR,0) } + LOAD = { CHANGED(LOADBAR,0) } + CLOCK1 = { CHANGED_HL(CLK1,0) } + CLOCK2 = { CHANGED_HL(CLK2,0) } + PINDLY: + QA_O = { + CASE( + CLOCK1 & TRN_LH, DELAY(-1,8NS,15NS), + CLOCK1 & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,20NS,30NS), + LOAD & TRN_LH, DELAY(-1,27NS,41NS), + CHANGED(A,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + QB_O = { + CASE( + CLOCK2 & TRN_LH, DELAY(-1,16NS,24NS), + CHANGED(B,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,20NS,30NS), + CLOCK2 & TRN_HL, DELAY(-1,22NS,33NS), + LOAD & TRN_LH, DELAY(-1,27NS,41NS), + CHANGED(B,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + QC_O = { + CASE( + CHANGED(C,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,20NS,30NS), + LOAD & TRN_LH, DELAY(-1,27NS,41NS), + CHANGED(C,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + CLOCK2 & TRN_LH, DELAY(-1,38NS,57NS), + CLOCK2 & TRN_HL, DELAY(-1,41NS,62NS), + DELAY(-1,41NS,62NS) + ) + } + QD_O = { + CASE( + CLOCK2 & TRN_LH, DELAY(-1,12NS,18NS), + CHANGED(D,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,20NS,30NS), + LOAD & TRN_LH, DELAY(-1,27NS,41NS), + CHANGED(D,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + CLOCK2 & TRN_HL, DELAY(-1,30NS,45NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + FREQ: + NODE = CLK1 + MAXFREQ = 30MEG + FREQ: + NODE = CLK2 + MAXFREQ = 15MEG + WIDTH: + NODE = CLK1 + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CLK2 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + WHEN = { CLRBAR!='0 } + WIDTH: + NODE = CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK HL = CLK1 + RELEASETIME_LH = 30NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK HL = CLK2 + RELEASETIME_LH = 50NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK HL = CLK1 + RELEASETIME_LH = 30NS + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK HL = CLK2 + RELEASETIME_LH = 50NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK HL = LOADBAR + SETUPTIME_HI = 10NS + SETUPTIME_LO = 15NS + HOLDTIME = 20NS + GENERAL: + WHEN = { LOADBAR=='0 & (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) + | CHANGED(D,0)) } + MESSAGE = "Invalid hold time of DATA with respect to LOADBAR." * .ENDS * *$ *--------- * 74LS197 4-Bit Presettable Binary Counter/Latch * * The LS Data Book, 1988, TI * JSW 8/4/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS197 LOADBAR_I CLRBAR_I CLK1_I CLK2_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS197LOG LOGICEXP(8,16) DPWR DGND + LOADBAR_I CLRBAR_I CLK1_I CLK2_I A_I B_I C_I D_I + LOADBAR CLRBAR CLK1 CLK2 A B C D SA SB SC SD RA RB RC RD + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + LOADBAR = { LOADBAR_I } + CLRBAR = { CLRBAR_I } + CLK1 = { CLK1_I } + CLK2 = { CLK2_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~CLRBAR | ~LOADBAR } + SA = { ~(A & LOAD & CLRBAR) } + SB = { ~(B & LOAD & CLRBAR) } + SC = { ~(C & LOAD & CLRBAR) } + SD = { ~(D & LOAD & CLRBAR) } + RA = { ~(SA & LOAD) } + RB = { ~(SB & LOAD) } + RC = { ~(SC & LOAD) } + RD = { ~(SD & LOAD) } * UJK1 JKFF(1) DPWR DGND SA RA CLK1 $D_HI $D_HI QA $D_NC D0_EFF IO_LS UJK2 JKFF(1) DPWR DGND SB RB CLK2 $D_HI $D_HI QB $D_NC D0_EFF IO_LS UJK3 JKFF(1) DPWR DGND SC RC QB $D_HI $D_HI QC $D_NC D0_EFF IO_LS UJK4 JKFF(1) DPWR DGND SD RD QC $D_HI $D_HI QD $D_NC D0_EFF IO_LS * ULS197DLY PINDLY (4,0,8) DPWR DGND + QA QB QC QD + CLK1 CLK2 A B C D LOADBAR CLRBAR + QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLEAR = { CHANGED(CLRBAR,0) } + LOAD = { CHANGED(LOADBAR,0) } + CLOCK1 = { CHANGED_HL(CLK1,0) } + CLOCK2 = { CHANGED_HL(CLK2,0) } + PINDLY: + QA_O = { + CASE( + CLOCK1 & TRN_LH, DELAY(-1,8NS,15NS), + CLOCK1 & TRN_HL, DELAY(-1,14NS,21NS), + CHANGED(A,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,18NS,27NS), + LOAD & TRN_LH, DELAY(-1,26NS,39NS), + CHANGED(A,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + QB_O = { + CASE( + CLOCK2 & TRN_LH, DELAY(-1,12NS,19NS), + CHANGED(B,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,18NS,27NS), + CLOCK2 & TRN_HL, DELAY(-1,23NS,35NS), + LOAD & TRN_LH, DELAY(-1,26NS,39NS), + CHANGED(B,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + DELAY(-1,34NS,51NS) + ) + } + QC_O = { + CASE( + CHANGED(C,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,18NS,27NS), + LOAD & TRN_LH, DELAY(-1,26NS,39NS), + CHANGED(C,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + CLOCK2 & TRN_LH, DELAY(-1,34NS,51NS), + CLOCK2 & TRN_HL, DELAY(-1,42NS,63NS), + DELAY(-1,42NS,63NS) + ) + } + QD_O = { + CASE( + CHANGED(D,0) & LOADBAR!='1 & TRN_LH, DELAY(-1,18NS,27NS), + LOAD & TRN_LH, DELAY(-1,26NS,39NS), + CHANGED(D,0) & LOADBAR!='1 & TRN_HL, DELAY(-1,29NS,44NS), + LOAD & TRN_HL, DELAY(-1,30NS,45NS), + CLEAR, DELAY(-1,34NS,51NS), + CLOCK2 & TRN_LH, DELAY(-1,55NS,78NS), + CLOCK2 & TRN_HL, DELAY(-1,63NS,95NS), + DELAY(-1,63NS,95NS) + ) + } + FREQ: + NODE = CLK1 + MAXFREQ = 30MEG + FREQ: + NODE = CLK2 + MAXFREQ = 15MEG + WIDTH: + NODE = CLK1 + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CLK2 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = LOADBAR + MIN_LO = 20NS + WHEN = { CLRBAR!='0 } + WIDTH: + NODE = CLRBAR + MIN_LO = 15NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK HL = CLK1 + RELEASETIME_LH = 30NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK HL = CLK2 + RELEASETIME_LH = 50NS + WHEN = { CLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK HL = CLK1 + RELEASETIME_LH = 30NS + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK HL = CLK2 + RELEASETIME_LH = 50NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK HL = LOADBAR + SETUPTIME_HI = 10NS + SETUPTIME_LO = 15NS + HOLDTIME = 20NS + WHEN = { CLRBAR!='0 } + GENERAL: + WHEN = { LOADBAR=='0 & (CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) + | CHANGED(D,0)) } + MESSAGE = "Invalid hold time of DATA with respect to LOADBAR." * .ENDS * *$ *---------- * 74LS240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/30/89 Update interface and model names * .subckt 74LS240 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS240 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_LS240 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS240 utgate ( + tplhty=9ns tplhmx=14ns + tphlty=12ns tphlmx=18ns + tpzhty=15ns tpzhmx=23ns + tpzlty=20ns tpzlmx=30ns + tphzty=15ns tphzmx=25ns + tplzty=10ns tplzmx=20ns + ) *$ *---------- * 74LS241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/30/89 Update interface and model names * jgt 09/08/92 Bug Fix: changed inverters to Buffers * .subckt 74LS241 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS241 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_LS241 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS241 utgate ( + tplhty=12ns tplhmx=18ns + tphlty=12ns tphlmx=18ns + tpzhty=15ns tpzhmx=23ns + tpzlty=20ns tpzlmx=30ns + tphzty=15ns tphzmx=25ns + tplzty=10ns tplzmx=20ns + ) * *$ *---------- * 74LS242 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/30/89 Update interface and model names * .subckt 74LS242 A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_LS242 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_LS242 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS242 utgate ( + tplhty=9ns tplhmx=14ns + tphlty=12ns tphlmx=18ns + tpzhty=15ns tpzhmx=23ns + tpzlty=20ns tpzlmx=30ns + tphzty=15ns tphzmx=25ns + tplzty=10ns tplzmx=20ns + ) *$ *---------- * 74LS243 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/30/89 Update interface and model names * .subckt 74LS243 A1 A2 A3 A4 GABBAR GBA B1 B2 B3 B4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + GABBAR GAB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + A1 A2 A3 A4 GAB B1 B2 B3 B4 + D_LS243 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + B1 B2 B3 B4 GBA A1 A2 A3 A4 + D_LS243 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS243 utgate ( + tplhty=12ns tplhmx=18ns + tphlty=12ns tphlmx=18ns + tpzhty=15ns tpzhmx=23ns + tpzlty=20ns tpzlmx=30ns + tphzty=15ns tphzmx=25ns + tplzty=10ns tplzmx=20ns + ) *$ *---------- * 74LS244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS * * The TTL Data Book, Vol 2, 1985, TI * tvh 06/30/89 Update interface and model names * .subckt 74LS244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS244 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_LS244 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS244 utgate ( + tplhty=12ns tplhmx=18ns + tphlty=12ns tphlmx=18ns + tpzhty=15ns tpzhmx=23ns + tpzlty=20ns tpzlmx=30ns + tphzty=15ns tphzmx=25ns + tplzty=10ns tplzmx=20ns + ) *$ *---------- * 74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-2-92 UPDATE TIMING * .SUBCKT 74LS245 DIR_I GBAR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + DIR_I GBAR_I + DIR GBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + DIR DIRBAR + D0_GATE IO_LS U3 NORA(2,2) DPWR DGND + DIRBAR GBAR DIR GBAR + ENABLEAB ENABLEBA + D0_GATE IO_LS * U4 BUF3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + ENABLEAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_LS245 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 BUF3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + ENABLEBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_LS245 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_LS245 UTGATE ( + TPLHTY= 8NS TPLHMX=12NS + TPHLTY= 8NS TPHLMX=12NS + TPZHTY=25NS TPZHMX=40NS + TPZLTY=27NS TPZLMX=40NS + TPHZTY=15NS TPHZMX=28NS + TPLZTY=15NS TPLZMX=25NS + ) * .ENDS * *$ *-------- * 74LS247 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS247 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} * ULS247LOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { (BBI & DBI) | (ALT & BLT & CBI) | (ABI & BLT & CLT & DLT) } + OUTB = { (BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI) } + OUTC = { (CBI & DBI) | (ALT & BBI & CLT) } + OUTD = { (ABI & BLT & CLT & DLT) | (ALT & BLT & CBI) | + (ABI & BBI & CBI) } + OUTE = { ABI | (BLT & CBI) } + OUTF = { (ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT) } + OUTG = { (ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR) } * ULS247DLY_OC PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } * .ENDS * *$ *-------- * 74LS248 DECODER/DRIVER BCD-7 SEGMENT WITH INTERNAL PULLUPS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS248 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} * ULS248LOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { ~((BBI & DBI) | (ALT & BLT & CBI) | (ABI & BLT & CLT & DLT)) } + OUTB = { ~((BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI)) } + OUTC = { ~((CBI & DBI) | (ALT & BBI & CLT)) } + OUTD = { ~((ABI & BLT & CLT & DLT) | (ALT & BLT & CBI) | + (ABI & BBI & CBI)) } + OUTE = { ~( ABI | (BLT & CBI)) } + OUTF = { ~((ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT)) } + OUTG = { ~((ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR)) } * ULS248DLY PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } * .ENDS * *$ *-------- * 74LS249 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * THE TTL DATA BOOK, VOLUME 2, STANDARD, S, LS, TTL; 1985, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS249 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 OR(6) DPWR DGND + LT RBIBAR INA INB INC IND + BIBAR/RBOBAR_B + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} * ULS249LOG LOGICEXP (7,13) DPWR DGND + INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + INA INB INC IND RBIBAR LT + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + INA = { INA_I } + INB = { INB_I } + INC = { INC_I } + IND = { IND_I } + RBIBAR = { RBIBAR_I } + LTBAR = { LTBAR_I } + BIBAR/RBOBAR = { BIBAR/RBOBAR_B } + + LT = { ~LTBAR } + ALT = { ~(INA & LTBAR) } + BLT = { ~(INB & LTBAR) } + CLT = { ~(INC & LTBAR) } + DLT = { ~IND } + ABI = { ~(ALT & BIBAR/RBOBAR) } + BBI = { ~(BLT & BIBAR/RBOBAR) } + CBI = { ~(CLT & BIBAR/RBOBAR) } + DBI = { ~(DLT & BIBAR/RBOBAR) } + + OUTA = { ~((BBI & DBI) | (ALT & BLT & CBI) | (ABI & BLT & CLT & DLT)) } + OUTB = { ~((BBI & DBI) | (ABI & BLT & CBI) | (ALT & BBI & CBI)) } + OUTC = { ~((CBI & DBI) | (ALT & BBI & CLT)) } + OUTD = { ~((ABI & BLT & CLT & DLT) | (ALT & BLT & CBI) | + (ABI & BBI & CBI)) } + OUTE = { ~( ABI | (BLT & CBI)) } + OUTF = { ~((ABI & BBI) | (BBI & CLT) | (ABI & CLT & DLT)) } + OUTG = { ~((ABI & BBI & CBI) | (BLT & CLT & DLT & LTBAR)) } * ULS249DLY_OC PINDLY (7,0,0) DPWR DGND + OUTA OUTB OUTC OUTD OUTE OUTF OUTG + + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + IO_LS_OC + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O = + { DELAY(-1,-1,100NS) } * .ENDS * *$ *--------- * 74LS251 MULTIPLEXER/DATA SELECTOR 8-1 LINE WITH 3-STATE OUTPUTS * * THE TTL DATA BOOK, 1988, TI * TC 08/24/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74LS251 GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS251LOG LOGICEXP(12,14) DPWR DGND + GBAR_I A_I B_I C_I D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + GBAR A B C D0 D1 D2 D3 D4 D5 D6 D7 W Y + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + IA = { ~A } + IB = { ~B } + IC = { ~C } + IG = { ~GBAR } + ID0 = { D0 & IA & IB & IC & IG } + ID1 = { D1 & A & IB & IC & IG } + ID2 = { D2 & IA & B & IC & IG } + ID3 = { D3 & A & B & IC & IG } + ID4 = { D4 & IA & IB & C & IG } + ID5 = { D5 & A & IB & C & IG } + ID6 = { D6 & IA & B & C & IG } + ID7 = { D7 & A & B & C & IG } + W = { ~(ID0 | ID1 | ID2 | ID3 | ID4 | ID5 | ID6 | ID7) } + Y = { ~W } * ULS251DLY PINDLY (2,1,11) DPWR DGND + W Y + GBAR + A B C D0 D1 D2 D3 D4 D5 D6 D7 + W_O Y_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | + CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0) } + TRISTATE: + ENABLE LO GBAR + Y_O = { + CASE( + TRN_HZ, DELAY(-1,30NS,45NS), + TRN_ZH, DELAY(-1,30NS,45NS), + SELECT & TRN_LH, DELAY(-1,29NS,45NS), + SELECT & TRN_HL, DELAY(-1,28NS,45NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DATA & TRN_HL, DELAY(-1,18NS,28NS), + DATA & TRN_LH, DELAY(-1,17NS,28NS), + TRN_LZ, DELAY(-1,15NS,25NS), + DELAY(-1,31NS,46NS) + ) + } + W_O = { + CASE( + TRN_HZ, DELAY(-1,37NS,55NS), + TRN_ZL, DELAY(-1,24NS,40NS), + SELECT & TRN_HL, DELAY(-1,21NS,33NS), + SELECT & TRN_LH, DELAY(-1,20NS,33NS), + TRN_ZH, DELAY(-1,17NS,27NS), + TRN_LZ, DELAY(-1,15NS,25NS), + DATA & TRN_LH, DELAY(-1,10NS,15NS), + DATA & TRN_HL, DELAY(-1,9NS,15NS), + DELAY(-1,38NS,56NS) + ) + } * .ENDS * *$ *--------- * 74LS253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * The TTL Data Book, 1988, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS253 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS253LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { I0 | I1 | I2 | I3 } + Y2 = { I4 | I5 | I6 | I7 } * ULS253DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(-1,15NS,28NS), + TRN_ZL, DELAY(-1,15NS,23NS), + TRN_HZ, DELAY(-1,27NS,41NS), + TRN_LZ, DELAY(-1,18NS,27NS), + SELECT & TRN_LH, DELAY(-1,30NS,45NS), + SELECT & TRN_HL, DELAY(-1,21NS,32NS), + DATA1 & TRN_LH, DELAY(-1,17NS,25NS), + DATA1 & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,28NS,46NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(-1,15NS,28NS), + TRN_ZL, DELAY(-1,15NS,23NS), + TRN_HZ, DELAY(-1,27NS,41NS), + TRN_LZ, DELAY(-1,18NS,27NS), + SELECT & TRN_LH, DELAY(-1,30NS,45NS), + SELECT & TRN_HL, DELAY(-1,21NS,32NS), + DATA2 & TRN_LH, DELAY(-1,17NS,25NS), + DATA2 & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,28NS,46NS) + ) + } * .ENDS * *$ *--------- * 74LS257B QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * The TTL Data Book, 1988, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS257B GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS257BLOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { (1A & SELBAR) | (1B & SEL) } + Y2 = { (2A & SELBAR) | (2B & SEL) } + Y3 = { (3A & SELBAR) | (3B & SEL) } + Y4 = { (4A & SELBAR) | (4B & SEL) } * ULS257BDLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(-1,15NS,30NS), + TRN_ZL, DELAY(-1,19NS,30NS), + TRN_HZ, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,16NS,25NS), + SELECT & TRN_LH, DELAY(-1,16NS,21NS), + SELECT & TRN_HL, DELAY(-1,17NS,24NS), + DATA & TRN_LH, DELAY(-1,8NS,13NS), + DATA & TRN_HL, DELAY(-1,10NS,15NS), + DELAY(-1,20NS,31NS) + ) + } * .ENDS * *$ *--------- * 74LS258B QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * WITH 3-STATE OUTPUTS * * The TTL Data Book, 1988, TI * JSW 8/25/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS258B GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + Y1_O Y2_O Y3_O Y4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS258BLOG LOGICEXP(10,14) DPWR DGND + GBAR_I 1A_I 1B_I 2A_I 2B_I 3A_I 3B_I 4A_I 4B_I SEL_I + GBAR 1A 1B 2A 2B 3A 3B 4A 4B SEL Y1 Y2 Y3 Y4 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + 1A = { 1A_I } + 1B = { 1B_I } + 2A = { 2A_I } + 2B = { 2B_I } + 3A = { 3A_I } + 3B = { 3B_I } + 4A = { 4A_I } + 4B = { 4B_I } + SEL = { SEL_I } + SELBAR = { ~SEL } + Y1 = { ~((1A & SELBAR) | (1B & SEL)) } + Y2 = { ~((2A & SELBAR) | (2B & SEL)) } + Y3 = { ~((3A & SELBAR) | (3B & SEL)) } + Y4 = { ~((4A & SELBAR) | (4B & SEL)) } * ULS258BDLY PINDLY (4,1,9) DPWR DGND + Y1 Y2 Y3 Y4 + GBAR + 1A 1B 2A 2B 3A 3B 4A 4B SEL + Y1_O Y2_O Y3_O Y4_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA = { CHANGED(1A,0) | CHANGED(1B,0) | CHANGED(2A,0) | CHANGED(2B,0) | + CHANGED(3A,0) | CHANGED(3B,0) | CHANGED(4A,0) | CHANGED(4B,0) } + SELECT = { CHANGED(SEL,0) } + TRISTATE: + ENABLE LO = GBAR + Y1_O Y2_O Y3_O Y4_O = { + CASE( + TRN_ZH, DELAY(-1,15NS,30NS), + TRN_ZL, DELAY(-1,20NS,30NS), + TRN_HZ, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,16NS,25NS), + SELECT & TRN_LH, DELAY(-1,14NS,21NS), + SELECT & TRN_HL, DELAY(-1,19NS,24NS), + DATA & TRN_LH, DELAY(-1,7NS,12NS), + DATA & TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,31NS) + ) + } * .ENDS * *$ *---------- * 74LS259B 8-BIT ADDRESSABLE LATCHES * * The TTL Data Book, Vol 2, 1985, TI * tvh 09/11/89 Update interface and model names * .subckt 74LS259B CLRBAR GBAR D S0 S1 S2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(3) DPWR DGND + CLRBAR GBAR D RB GB DATA + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 bufa(3) DPWR DGND + S0 S1 S2 SA SB SC + D_LS259B_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U3 inva(3) DPWR DGND + SA SB SC AB BB CB + D0_GATE IO_LS U4 nanda(3,8) DPWR DGND + AB BB CB + SA BB CB + AB SB CB + SA SB CB + AB BB SC + SA BB SC + AB SB SC + SA SB SC + T0 T1 T2 T3 T4 T5 T6 T7 + D0_GATE IO_LS U5 nora(2,8) DPWR DGND + GB T0 + GB T1 + GB T2 + GB T3 + GB T4 + GB T5 + GB T6 + GB T7 + G0 G1 G2 G3 G4 G5 G6 G7 + D0_GATE IO_LS U6 ora(2,8) DPWR DGND + G0 RB + G1 RB + G2 RB + G3 RB + G4 RB + G5 RB + G6 RB + G7 RB + R0 R1 R2 R3 R4 R5 R6 R7 + D0_GATE IO_LS U7 dltch(1) DPWR DGND + $D_HI R0 G0 DATA Q0 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 dltch(1) DPWR DGND + $D_HI R1 G1 DATA Q1 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 dltch(1) DPWR DGND + $D_HI R2 G2 DATA Q2 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 dltch(1) DPWR DGND + $D_HI R3 G3 DATA Q3 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U11 dltch(1) DPWR DGND + $D_HI R4 G4 DATA Q4 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U12 dltch(1) DPWR DGND + $D_HI R5 G5 DATA Q5 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U13 dltch(1) DPWR DGND + $D_HI R6 G6 DATA Q6 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U14 dltch(1) DPWR DGND + $D_HI R7 G7 DATA Q7 $D_NC + D_LS259B_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS259B_1 ugate ( + TPLHTY=2NS TPLHMX=3NS + TPHLTY=2NS TPHLMX=3NS + ) .model D_LS259B_2 ugff ( + TWGHMN=17NS TWPCLMN=10NS + TSUDGMN=20NS TPPCQHLTY=12NS + TPPCQHLMX=18NS TPDQLHTY=19NS + TPDQLHMX=30NS TPDQHLTY=13NS + TPDQHLMX=20NS TPGQLHTY=15NS + TPGQLHMX=24NS TPGQHLTY=15NS + TPGQHLMX=24NS + ) *$ *------------------------------------------------------------------------- * 74LS261 2-BIT BY 4-BIT BINARY MULTIPLIERS * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 08/11/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * jgt 10/16/93 Changed to use integral constraint clauses in pindly * .SUBCKT 74LS261 C_I M2_I M1_I M0_I B0_I B1_I B2_I B3_I B4_I + Q0_O Q1_O Q2_O Q3_O Q4BAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS261LOG LOGICEXP(14,14) DPWR DGND + C_I M2_I M1_I M0_I B0_I B1_I B2_I B3_I B4_I Q0 Q1 Q2 Q3 Q4BAR + C M2 M1 M0 B0 B1 B2 B3 B4 Q0 Q1 Q2 Q3 Q4BAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + C = { C_I } + M2 = { M2_I } + M1 = { M1_I } + M0 = { M0_I } + B0 = { B0_I } + B1 = { B1_I } + B2 = { B2_I } + B3 = { B3_I } + B4 = { B4_I } + IB1 = { ~B1 } + IB2 = { ~B2 } + IB3 = { ~B3 } + IB4 = { ~B4 } + IM1 = { M0 & M1 } + IM2 = { ~(M0 | M1) } + IM3 = { ~(IM1 | IM2) } + IC1 = { ~C } + IC2 = { ~(M2 | IC1) } + IC3 = { ~(IC1 | IC2) } + Q0 = { (B0 & IM1 & IC2) | (~B0 & IM2 & IC3) | (B1 & IM3 & IC2) | + (IB1 & IM3 & IC3) | (IC1 & Q0) } + Q1 = { (B1 & IM1 & IC2) | (IB1 & IM2 & IC3) | (B2 & IM3 & IC2) | + (IB2 & IM3 & IC3) | (IC1 & Q1) } + Q2 = { (B2 & IM1 & IC2) | (IB2 & IM2 & IC3) | (B3 & IM3 & IC2) | + (IB3 & IM3 & IC3) | (IC1 & Q2) } + Q3 = { (B3 & IM1 & IC2) | (IB3 & IM2 & IC3) | (B4 & IM3 & IC2) | + (IB4 & IM3 & IC3) | (IC1 & Q3) } + Q4BAR = { ~((B4 & IM1 & IC2) | (IB4 & IM2 & IC3) | (B4 & IM3 & IC2) | + (IB4 & IM3 & IC3) | (IC1 & ~Q4BAR)) } * ULS261DLY PINDLY (5,0,9) DPWR DGND + Q0 Q1 Q2 Q3 Q4BAR + C M0 M1 M2 B0 B1 B2 B3 B4 + Q0_O Q1_O Q2_O Q3_O Q4BAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + MULTIPLIER = { CHANGED(M0,0) | CHANGED(M1,0) | CHANGED(M2,0) } + MULTIPLICAND = { CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | + CHANGED(B3,0) | CHANGED(B4,0) } + PINDLY: + Q0_O Q1_O Q2_O Q3_O Q4BAR_O = { + CASE( + MULTIPLICAND & TRN_LH, DELAY(-1,27NS,42NS), + MULTIPLIER & TRN_LH, DELAY(-1,25NS,40NS), + MULTIPLICAND & TRN_HL, DELAY(-1,24NS,37NS), + CHANGED_LH(C,0) & TRN_LH, DELAY(-1,22NS,35NS), + MULTIPLIER & TRN_HL, DELAY(-1,22NS,35NS), + CHANGED_LH(C,0) & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(-1,27NS,42NS) + ) + } + + WIDTH: + NODE = C + MIN_HI = 25NS + SETUP_HOLD: + DATA(3) = M0 M1 M2 + CLOCK HL = C + SETUPTIME = 17NS + AFFECTS_ALL + SETUP_HOLD: + DATA(1) = B0 + CLOCK HL = C + SETUPTIME = 15NS + AFFECTS (1) Q0_O + SETUP_HOLD: + DATA(4) = B1 B2 B3 B4 + CLOCK HL = C + SETUPTIME = 15NS + AFFECTS (4) Q1_O Q2_O Q3_O Q4BAR_O * .ENDS * *$ *---------- * 74LS266 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES WITH OPEN-COLLECTOR OUTPUTS. * * The TTL Data Book, Vol 2, 1985, TI * tvh 07/5/89 Update interface and model names * .subckt 74LS266 A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 nxor DPWR DGND + A B Y + D_LS266 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS266 ugate ( + TPLHTY=18NS TPLHMX=30NS + TPHLTY=18NS TPHLMX=30NS + ) *$ *---------- * 74LS273 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR * * The TTL Data Book, Vol 2, 1985, TI * tvh 07/5/89 Update interface and model names * .subckt 74LS273 CLRBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UD dff(8) DPWR DGND + $D_HI CLRBAR CLK + D1 D2 D3 D4 D5 D6 D7 D8 + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_LS273 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS273 ueff ( + TWCLKLMN=20NS TWCLKHMN=20NS + TWPCLMN=20NS TSUDCLKMN=20NS + TSUPCCLKHMN=25NS THDCLKMN=5NS + TPPCQHLTY=18NS TPPCQHLMX=27NS + TPCLKQLHTY=17NS TPCLKQLHMX=27NS + TPCLKQHLTY=18NS TPCLKQHLMX=27NS + ) *$ *---------- * 74LS279A QUADRUPLE SBAR-RBAR LATCHES * * The TTL Data Book, Vol 2, 1985, TI * tvh 09/07/89 Update interface and model names * .subckt 74LS279A 1RBAR 1S1BAR 1S2BAR 2RBAR 2SBAR 1Q 2Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1 bufa(2) DPWR DGND + 1RBAR 2RBAR 1RB 2RB + D_LS279A_1 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 nanda(3,2) DPWR DGND + 1RB Q1 $D_HI 1S1BAR 1S2BAR Q1B Q1B Q1 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U3 nanda(2,2) DPWR DGND + 2RB Q2 2SBAR Q2B Q2B Q2 + D0_GATE IO_STD IO_LEVEL={IO_LEVEL} U4 wdthck(5) DPWR DGND + 1RBAR 1S1BAR 1S2BAR 2RBAR 2SBAR + $D_NC $D_NC $D_NC $D_NC $D_NC + 1RLO 1S1LO 1S2LO 2RLO 2SLO + D_LS279A_2 IO_STD MNTYMXDLY={MNTYMXDLY} U5 ora(3,2) DPWR DGND + 1RLO 1S1LO 1S2LO 2RLO 2SLO $D_LO X1 X2 + D0_GATE IO_STD U6 inva(2) DPWR DGND + X1 X2 T1 T2 + D0_GATE IO_STD U7 buf3 DPWR DGND + $D_X X1 1Q + D_LS279A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U8 buf3 DPWR DGND + $D_X X2 2Q + D_LS279A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U9 buf3 DPWR DGND + Q1 T1 1Q + D_LS279A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U10 buf3 DPWR DGND + Q2 T2 2Q + D_LS279A_3 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS279A_1 ugate ( + TPHLTY=2NS TPHLMX=6NS + ) .model D_LS279A_2 uwdth ( + TWLMN=20NS + ) .model D_LS279A_3 utgate ( + TPLHTY=12NS TPHLTY=13NS + TPLHMX=22NS TPHLMX=21NS + TPZHTY=12NS TPZLTY=13NS + TPZHMX=22NS TPZLMX=21NS + TPLZTY=12NS TPHZTY=13NS + TPLZMX=22NS TPHZMX=21NS + ) * *$ *--------- * 74LS280 PARITY GENERATOR/CHECKER ODD/EVEN 9-BIT * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS280 A_I B_I C_I D_I E_I F_I G_I H_I I_I + EOUT_O OOUT_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS280LOG LOGICEXP (9,2) DPWR DGND + A_I B_I C_I D_I E_I F_I G_I H_I I_I + EOUT OOUT + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + I = { I_I } + + ABC = { (A & ~B & ~C) | (~A & B & ~C) | (~A & ~B & C) | (A & B & C) } + DEF = { (D & ~E & ~F) | (~D & E & ~F) | (~D & ~E & F) | (D & E & F) } + GHI = { (G & ~H & ~I) | (~G & H & ~I) | (~G & ~H & I) | (G & H & I) } + EOUT = { (~ABC & DEF & GHI) | (ABC & ~DEF & GHI) | (ABC & DEF & ~GHI) | + (~ABC & ~DEF & ~GHI) } + OOUT = { ~EOUT } * ULS280DLY PINDLY (2,0,0) DPWR DGND + EOUT OOUT + + EOUT_O OOUT_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + EOUT_O = { + CASE ( + TRN_HL, DELAY(-1,29NS,45NS), + DELAY(-1,33NS,50NS) + ) + } + OOUT_O = { + CASE ( + TRN_LH, DELAY(-1,23NS,35NS), + DELAY(-1,31NS,50NS) + ) + } * .ENDS * *$ *--------- * 74LS283 4-BIT BINARY FULL ADDERS WITH FAST CARRY * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/26/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS283 C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I C4_O + SUM1_O SUM2_O SUM3_O SUM4_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS283LOG LOGICEXP(9,14) DPWR DGND + C0_I A1_I A2_I A3_I A4_I B1_I B2_I B3_I B4_I + C0 A1 A2 A3 A4 B1 B2 B3 B4 C4 SUM1 SUM2 SUM3 SUM4 + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + C0 = { C0_I } + A1 = { A1_I } + A2 = { A2_I } + A3 = { A3_I } + A4 = { A4_I } + B1 = { B1_I } + B2 = { B2_I } + B3 = { B3_I } + B4 = { B4_I } + + NAND4 = { ~(A4 & B4) } + NAND3 = { ~(A3 & B3) } + NAND2 = { ~(A2 & B2) } + NAND1 = { ~(A1 & B1) } + NOR4 = { ~(A4 | B4) } + NOR3 = { ~(A3 | B3) } + NOR2 = { ~(A2 | B2) } + NOR1 = { ~(A1 | B1) } + C0BAR = { ~C0 } + + SUM1 = { (NAND1 & ~NOR1) ^ C0 } + SUM2 = { (NAND2 & ~NOR2) ^ (~(NOR1 | (NAND1 & C0BAR))) } + SUM3 = { (NAND3 & ~NOR3) ^ (~(NOR2 | (NOR1 & NAND2) | + (NAND2 & NAND1 & C0BAR))) } + SUM4 = { (NAND4 & ~NOR4) ^ (~(NOR3 | (NOR2 & NAND3) | + (NOR1 & NAND3 & NAND2) | (NAND3 & NAND2 & NAND1 & C0BAR))) } + C4 = { ~( NOR4 | (NOR3 & NAND4) | (NOR2 & NAND4 & NAND3) | + (NOR1 & NAND4 & NAND3 & NAND2) | + (NAND4 & NAND3 & NAND2 & NAND1 & C0BAR) ) } * ULS283DLY PINDLY (5,0,9) DPWR DGND + SUM1 SUM2 SUM3 SUM4 C4 + C0 A1 A2 A3 A4 B1 B2 B3 B4 + SUM1_O SUM2_O SUM3_O SUM4_O C4_O + IO_LS MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_AB = { CHANGED(A1,0) | CHANGED(B1,0) | CHANGED(A2,0) | + CHANGED(B2,0) | CHANGED(A3,0) | CHANGED(B3,0) | + CHANGED(A4,0) | CHANGED(B4,0) } + + PINDLY: + SUM1_O SUM2_O SUM3_O SUM4_O = { + CASE( + ANY_CH_AB, DELAY(-1,15NS,24NS), + CHANGED(C0,0) & TRN_LH, DELAY(-1,16NS,24NS), + CHANGED(C0,0) & TRN_HL, DELAY(-1,15NS,24NS), + DELAY(-1,17NS,25NS) ;DEFAULT + ) + } + C4_O = { + CASE( + CHANGED(C0,0) & TRN_HL, DELAY(-1,11NS,22NS), + ANY_CH_AB & TRN_HL, DELAY(-1,12NS,17NS), + (ANY_CH_AB | CHANGED(C0,0)) & TRN_LH, DELAY(-1,11NS,17NS), + DELAY(-1,16NS,23NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS290 COUNTER DECADE 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-3-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE -- EXCEPT FOR THE PIN ARRANGEMENT, THE 'LS290 IS ELECTRICALLY AND * FUNCTIONALLY IDENTICAL TO THE 'LS90 * NOTICE -- THE CKA TO QD PIN DELAY IS NOT INCLUDED IN THIS MODEL SINCE * THE DIV2 AND DIV5 SECTIONS OF THE COUNTER ACT INDEPENDENTLY. * .SUBCKT 74LS290 R91 R92 CKA CKB R01 R02 QA QB QC QD + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * X1 R91 R92 CKA CKB R01 R02 QA QB QC QD DPWR DGND 74LS90 + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .ENDS * *$ *-------- * 74LS293 COUNTER BINARY 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 6-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE -- EXCEPT FOR THE PIN ARRANGEMENT, THE 'LS293 IS ELECTRICALLY AND * FUNCTIONALLY IDENTICAL TO THE 'LS93 * NOTICE -- THE CKA TO QD PIN DELAY IS NOT INCLUDED IN THIS MODEL SINCE * THE DIV2 AND DIV8 SECTIONS OF THE COUNTER ACT INDEPENDENTLY. * .SUBCKT 74LS293 CKA CKB R01 R02 QA QB QC QD + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * X1 CKA CKB R01 R02 QA QB QC QD DPWR DGND 74LS93 + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .ENDS * *$ *------------------------------------------------------------------------- * 74LS295B 4-BIT RIGHT-SHIFT LEFT-SHIFT REGISTERS WITH 3-STATE OUTPUTS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 7/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS295B CLK_I LD/SHBAR_I OC_I SER_I A_I B_I C_I D_I QA_O QB_O QC_O + QD_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * U295BLOG LOGICEXP(11,16) DPWR DGND + CLK_I LD/SHBAR_I OC_I SER_I A_I B_I C_I D_I QA QB QC + CLK LD/SHBAR OC SER A B C D JA JB JC JD KA KB KC KD + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + CLK = { CLK_I } + LD/SHBAR = { LD/SHBAR_I } + OC = { OC_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERM + SHIFT = { ~LD/SHBAR } + + KA = { ~((SER & SHIFT) | (LD/SHBAR & A)) } + KB = { ~((QA & SHIFT) | (LD/SHBAR & B)) } + KC = { ~((QB & SHIFT) | (LD/SHBAR & C)) } + KD = { ~((QC & SHIFT) | (LD/SHBAR & D)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } * U1 JKFF(4) DPWR DGND $D_HI $D_HI CLK JA JB JC JD KA KB KC KD + QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U295BDLY PINDLY (4,1,8) DPWR DGND + QA QB QC QD + OC + CLK CLK LD/SHBAR SER A B C D + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ENABLE = { CHANGED_LH(OC,0) } + DISABLE = { CHANGED_HL(OC,0) } + + TRISTATE: + ENABLE HI OC + QA_O QB_O QC_O QD_O = { + CASE( + DISABLE, DELAY(-1,13NS,20NS), + CHANGED_HL(CLK,0) & TRN_LH, DELAY(-1,14NS,20NS), + ENABLE & TRN_ZH, DELAY(-1,18NS,26NS), + CHANGED_HL(CLK,0) & TRN_HL, DELAY(-1,19NS,30NS), + ENABLE & TRN_ZL, DELAY(-1,20NS,30NS), + DELAY(-1,21NS,31NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 30MEG + + WIDTH: + NODE = CLK + MIN_LO = 16NS + MIN_HI = 16NS + + SETUP_HOLD: + DATA(1) LD/SHBAR + CLOCK HL = CLK + SETUPTIME_HI = 25NS + SETUPTIME_LO = 30NS + + SETUP_HOLD: + DATA(1) SER + CLOCK HL = CLK + SETUPTIME = 20NS + HOLDTIME = 20NS + WHEN = { (LD/SHBAR!='1 ^ CHANGED(LD/SHBAR,0)) } + + SETUP_HOLD: + DATA(4) A B C D + CLOCK HL = CLK + SETUPTIME = 20NS + HOLDTIME = 20NS + WHEN = { (LD/SHBAR!='0 ^ CHANGED(LD/SHBAR,0)) } * .ENDS * *$ *--------- * 74LS298 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * THE TTL DATA BOOK, 1988, TI * TC 08/25/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74LS298 WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(4) DPWR DGND $D_HI $D_HI CLK + JA JB JC JD KA KB KC KD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS298LOG LOGICEXP(10,18) DPWR DGND + WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + WS CLK A1 A2 B1 B2 C1 C2 D1 D2 JA JB JC JD KA KB KC KD + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + WS = { WS_I } + CLK = { CLK_I } + A1 = { A1_I } + A2 = { A2_I } + B1 = { B1_I } + B2 = { B2_I } + C1 = { C1_I } + C2 = { C2_I } + D1 = { D1_I } + D2 = { D2_I } + IWS = { ~WS } + KA = { ~((A1 & IWS) | (WS & A2)) } + KB = { ~((B1 & IWS) | (WS & B2)) } + KC = { ~((C1 & IWS) | (WS & C2)) } + KD = { ~((D1 & IWS) | (WS & D2)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } * ULS298DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + A1 A2 B1 B2 C1 C2 D1 D2 WS CLK + QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + TRN_LH, DELAY(-1,18NS,27NS), + DELAY(-1,21NS,32NS) + ) + } + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + SETUP_HOLD: + DATA(4) = A1 B1 C1 D1 + CLOCK HL = CLK + SETUPTIME = 15NS + HOLDTIME = 5NS + WHEN = { WS!='1 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(4) = A2 B2 C2 D2 + CLOCK HL = CLK + SETUPTIME = 15NS + HOLDTIME = 5NS + WHEN = { WS!='0 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(1) = WS + CLOCK HL = CLK + SETUPTIME = 25NS * .ENDS * *$ *--------- * 74LS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-20-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS299 CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS299LOG LOGICEXP(32,25) DPWR DGND + CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B ; BUFFERING + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + + CLK CLRBAR S1 S0 G1BAR G2BAR SL SR + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + D1A D1B D1C D1D D1E D1F D1G D1H OE + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: * BUFFERING: + + CLK = { CLK_I } + CLRBAR = { CLRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + SL = { SL_I } + SR = { SR_I } + A/QA = { A/QA_B } + B/QB = { B/QB_B } + C/QC = { C/QC_B } + D/QD = { D/QD_B } + E/QE = { E/QE_B } + F/QF = { F/QF_B } + G/QG = { G/QG_B } + H/QH = { H/QH_B } + * INTERMEDIATE TERMS: + S0S1 = { S0 & S1 } + S0/S1 = { S0 & ~S1 } + /S0S1 = { ~S0 & S1 } + /S0/S1 = { ~S0 & ~S1 } + * OUTPUTS: + D1A = { (S0/S1 & SR ) | (/S0S1 & LB/QB) | + (S0S1 & A/QA) | (/S0/S1 & LA/QA) } + D1B = { (S0/S1 & LA/QA) | (/S0S1 & LC/QC) | + (S0S1 & B/QB) | (/S0/S1 & LB/QB) } + D1C = { (S0/S1 & LB/QB) | (/S0S1 & LD/QD) | + (S0S1 & C/QC) | (/S0/S1 & LC/QC) } + D1D = { (S0/S1 & LC/QC) | (/S0S1 & LE/QE) | + (S0S1 & D/QD) | (/S0/S1 & LD/QD) } + D1E = { (S0/S1 & LD/QD) | (/S0S1 & LF/QF) | + (S0S1 & E/QE) | (/S0/S1 & LE/QE) } + D1F = { (S0/S1 & LE/QE) | (/S0S1 & LG/QG) | + (S0S1 & F/QF) | (/S0/S1 & LF/QF) } + D1G = { (S0/S1 & LF/QF) | (/S0S1 & LH/QH) | + (S0S1 & G/QG) | (/S0/S1 & LG/QG) } + D1H = { (S0/S1 & LG/QG) | (/S0S1 & SL ) | + (S0S1 & H/QH) | (/S0/S1 & LH/QH) } + OE = { G1BAR | G2BAR | (S1 & S0) } * U1 DFF(8) DPWR DGND $D_HI CLRBAR CLK + D1A D1B D1C D1D D1E D1F D1G D1H + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS299DLY PINDLY (10,1,17) DPWR DGND + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH LA/QA LH/QH + OE + G1BAR G2BAR CLK CLRBAR CLRBAR S0 S1 A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH SR SL + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QAP_O QHP_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,22NS,33NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,26NS,39NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,27NS,40NS), + DELAY(-1,28NS,41NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OE + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B = { + CASE( + TRN_ZH, DELAY(-1,13NS,21NS), + TRN_ZL, DELAY(-1,19NS,30NS), + TRN_HZ, DELAY(-1,10NS,20NS), + TRN_LZ, DELAY(-1,10NS,15NS), + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,17NS,25NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,26NS,39NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,26NS,40NS), + DELAY(-1,27NS,41NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 20MEG + + WIDTH: + NODE = CLK + MIN_HI = 30NS + MIN_LO = 10NS + + WIDTH: + NODE = CLRBAR + MIN_LO = 20NS + + SETUP_HOLD: + DATA(2) = S1 S0 + CLOCK LH = CLK + SETUPTIME = 35NS + HOLDTIME = 10NS + WHEN = { CLRBAR!='0 } + + SETUP_HOLD: + DATA(8) = A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) + & (S0!='0 ^ CHANGED(S0,0)) } + + + SETUP_HOLD: + DATA(1) = SL + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) + & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 + & (S1!='1 ^ CHANGED(S1,0)) + & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 20NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS322A 8-BIT SHIFT REGISTERS WITH SIGN EXTEND * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-20-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS322A OEBAR_I GBAR_I CLK_I S/PBAR_I SEBAR_I CLRBAR_I DS_I D0_I D1_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U322LOG LOGICEXP(33,26) DPWR DGND + OEBAR_I GBAR_I CLK_I S/PBAR_I SEBAR_I CLRBAR_I DS_I D0_I D1_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B ; BUFFERING + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + + OEBAR GBAR CLK S/PBAR SEBAR CLRBAR DS D0 D1 + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + D1A D1B D1C D1D D1E D1F D1G D1H OE + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: * BUFFERING: + OEBAR = { OEBAR_I } + CLRBAR = { CLRBAR_I } + CLK = { CLK_I } + GBAR = { GBAR_I } + S/PBAR = { S/PBAR_I } + SEBAR = { SEBAR_I } + DS = { DS_I } + D1 = { D1_I } + D0 = { D0_I } + A/QA = { A/QA_B } + B/QB = { B/QB_B } + C/QC = { C/QC_B } + D/QD = { D/QD_B } + E/QE = { E/QE_B } + F/QF = { F/QF_B } + G/QG = { G/QG_B } + H/QH = { H/QH_B } + * INTERMEDIATE TERMS: + GP = { ~(GBAR | S/PBAR) } + GS = { ~(GBAR | ~(GBAR | S/PBAR)) } + * OUTPUTS: + OE = { OEBAR | GP } + D1A = { (~DS & GS & SEBAR & D0) | (DS & GS & SEBAR & D1) | + (GP & A/QA) | (~SEBAR & GS & LA/QA) | (LA/QA & GBAR) } + D1B = { (GS & LA/QA) | (GP & B/QB) | (GBAR & LB/QB) } + D1C = { (GS & LB/QB) | (GP & C/QC) | (GBAR & LC/QC) } + D1D = { (GS & LC/QC) | (GP & D/QD) | (GBAR & LD/QD) } + D1E = { (GS & LD/QD) | (GP & E/QE) | (GBAR & LE/QE) } + D1F = { (GS & LE/QE) | (GP & F/QF) | (GBAR & LF/QF) } + D1G = { (GS & LF/QF) | (GP & G/QG) | (GBAR & LG/QG) } + D1H = { (GS & LG/QG) | (GP & H/QH) | (GBAR & LH/QH) } + * U1 DFF(8) DPWR DGND $D_HI CLRBAR CLK + D1A D1B D1C D1D D1E D1F D1G D1H + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U322DLY PINDLY (9,1,17) DPWR DGND + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH LH/QH + OEBAR + OEBAR CLRBAR CLK CLK DS D0 D1 GBAR S/PBAR A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QHP_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QHP_O = { + CASE( + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,22NS,33NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,26NS,35NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,27NS,35NS), + DELAY(-1,28NS,36NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OEBAR + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B = { + CASE( + TRN_ZH, DELAY(-1,15NS,35NS), + TRN_ZL, DELAY(-1,15NS,35NS), + TRN_HZ, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,15NS,25NS), + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,16NS,25NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,22NS,35NS), + DELAY(-1,23NS,36NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 20MEG + + WIDTH: + NODE = CLK + MIN_HIGH = 30NS + MIN_LOW = 10NS + + WIDTH: + NODE = CLRBAR + MIN_LOW = 20NS + + SETUP_HOLD: + DATA(10) A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH D0 D1 + CLOCK LH = CLK + SETUPTIME = 20NS + HOLDTIME = 2NS + WHEN = { CLRBAR != '0 & GBAR != '1 & S/PBAR != '1 } + + SETUP_HOLD: + DATA(1) DS + CLOCK LH = CLK + SETUPTIME = 10NS + HOLDTIME = 10NS + WHEN = { CLRBAR != '0 & GBAR != '1 & S/PBAR != '0 } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK LH = CLK + RELEASETIME_LH = 20NS + + SETUP_HOLD: + DATA(1) GBAR + CLOCK LH = CLK + RELEASETIME_LH = 35NS + RELEASETIME_HL = 50NS + WHEN = { CLRBAR != '0 } * .ENDS * *$ *--------- * 74LS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS * * THE TTL DATABOOK, 1988, TI * KN 7-22-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS323 CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS323LOG LOGICEXP(32,25) DPWR DGND + CLK_I CLRBAR_I S1_I S0_I G1BAR_I G2BAR_I SL_I SR_I + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B ; BUFFERING + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + + CLK CLRBAR S1 S0 G1BAR G2BAR SL SR + A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + D1A D1B D1C D1D D1E D1F D1G D1H OE + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: + * BUFFERING: + CLK = { CLK_I } + CLRBAR = { CLRBAR_I } + S1 = { S1_I } + S0 = { S0_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + SL = { SL_I } + SR = { SR_I } + A/QA = { A/QA_B } + B/QB = { B/QB_B } + C/QC = { C/QC_B } + D/QD = { D/QD_B } + E/QE = { E/QE_B } + F/QF = { F/QF_B } + G/QG = { G/QG_B } + H/QH = { H/QH_B } + * INTERMEDIATE TERMS: + SA = { ~(S0 | ~CLRBAR) } + SB = { ~(SA | ~CLRBAR) } + + S0S1 = { SB & S1 } + S0/S1 = { SB & ~S1 } + /S0S1 = { SA & S1 } + /S0/S1 = { SA & ~S1 } + * OUTPUTS: + D1A = { (S0/S1 & SR ) | (/S0S1 & LB/QB) | (S0S1 & A/QA) | (/S0/S1 & LA/QA) } + D1B = { (S0/S1 & LA/QA) | (/S0S1 & LC/QC) | (S0S1 & B/QB) + | (/S0/S1 & LB/QB) } + D1C = { (S0/S1 & LB/QB) | (/S0S1 & LD/QD) | (S0S1 & C/QC) + | (/S0/S1 & LC/QC) } + D1D = { (S0/S1 & LC/QC) | (/S0S1 & LE/QE) | (S0S1 & D/QD) + | (/S0/S1 & LD/QD) } + D1E = { (S0/S1 & LD/QD) | (/S0S1 & LF/QF) | (S0S1 & E/QE) + | (/S0/S1 & LE/QE) } + D1F = { (S0/S1 & LE/QE) | (/S0S1 & LG/QG) | (S0S1 & F/QF) + | (/S0/S1 & LF/QF) } + D1G = { (S0/S1 & LF/QF) | (/S0S1 & LH/QH) | (S0S1 & G/QG) + | (/S0/S1 & LG/QG) } + D1H = { (S0/S1 & LG/QG) | (/S0S1 & SL ) | (S0S1 & H/QH) + | (/S0/S1 & LH/QH) } + OE = { G1BAR | G2BAR | (S1 & S0) } * U1 DFF(8) DPWR DGND $D_HI CLRBAR CLK + D1A D1B D1C D1D D1E D1F D1G D1H + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS323DLY PINDLY (10,1,15) DPWR DGND + LA/QA LB/QB LC/QC LD/QD LE/QE LF/QF LG/QG LH/QH LA/QA LH/QH + OE + CLK CLK CLRBAR S0 S1 A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH SR SL + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B QAP_O QHP_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QAP_O QHP_O = { + CASE( + CHANGED(CLK,0) & TRN_LH, DELAY(-1,22NS,33NS), + CHANGED(CLK,0) & TRN_HL, DELAY(-1,26NS,39NS), + DELAY(-1,27NS,40NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO OE + A/QA_B B/QB_B C/QC_B D/QD_B E/QE_B F/QF_B G/QG_B H/QH_B = { + CASE( + TRN_ZH, DELAY(-1,14NS,21NS), + TRN_ZL, DELAY(-1,20NS,30NS), + TRN_HZ, DELAY(-1,10NS,20NS), + TRN_LZ, DELAY(-1,10NS,15NS), + CHANGED(CLK,0) & TRN_LH, DELAY(-1,17NS,25NS), + CHANGED(CLK,0) & TRN_HL, DELAY(-1,25NS,39NS), + DELAY(-1,26NS,40NS) ;DEFAULT + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 20MEG + + WIDTH: + NODE = CLK + MIN_HI = 30NS + MIN_LO = 10NS + + SETUP_HOLD: + DATA(1) = CLRBAR + CLOCK LH = CLK + SETUPTIME = 20NS + + SETUP_HOLD: + DATA(2) = S1 S0 + CLOCK LH = CLK + SETUPTIME = 35NS + HOLDTIME = 10NS + WHEN = { CLRBAR!='0 } + + SETUP_HOLD: + DATA(8) = A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SL + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 + & (S1!='0 ^ CHANGED(S1,0)) & (S0!='1 ^ CHANGED(S0,0)) } + + SETUP_HOLD: + DATA(1) = SR + CLOCK LH = CLK + SETUPTIME = 20NS + WHEN = { CLRBAR!='0 + & (S1!='1 ^ CHANGED(S1,0)) & (S0!='0 ^ CHANGED(S0,0)) } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS347 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS347 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * X1 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O DPWR DGND 74LS47 + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .ENDS * *$ *------------------------------------------------------------------------- * 74LS348 PRIORITY ENCODER 8-3 LINE WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-28-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS348 EI_I IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I + A0_O A1_O A2_O EO_O GS_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS348LOG LOGICEXP (9,15) DPWR DGND + EI_I IN0_I IN1_I IN2_I IN3_I IN4_I IN5_I IN6_I IN7_I + EI IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 + A0 A1 A2 EO GS EIEO + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + EI = { EI_I } + IN0 = { IN0_I } + IN1 = { IN1_I } + IN2 = { IN2_I } + IN3 = { IN3_I } + IN4 = { IN4_I } + IN5 = { IN5_I } + IN6 = { IN6_I } + IN7 = { IN7_I } + EIBAR = { ~EI } + IN0BAR = { ~IN0 } + IN1BAR = { ~IN1 } + IN2BAR = { ~IN2 } + IN3BAR = { ~IN3 } + IN4BAR = { ~IN4 } + IN5BAR = { ~IN5 } + IN6BAR = { ~IN6 } + IN7BAR = { ~IN7 } + + EO = { ~(IN0 & IN1 & IN2 & IN3 & IN4 & IN5 & IN6 & IN7 & EIBAR) } + EIEO = { EO & EIBAR } + GS = { ~EIEO } + A0 = { ~(EIEO & ((IN1BAR & IN2 & IN4 & IN6) | + (IN3BAR & IN4 & IN6) | (IN5BAR & IN6) | IN7BAR)) } + A1 = { ~(EIEO & ((IN2BAR & IN4 & IN5) | + (IN3BAR & IN4 & IN5) | IN6BAR | IN7BAR)) } + A2 = { ~(EIEO & (IN4BAR | IN5BAR | IN6BAR | IN7BAR)) } * ULS348DLY PINDLY (5,1,9) DPWR DGND + A0 A1 A2 GS EO + EIEO + IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 EI + A0_O A1_O A2_O GS_O EO_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + DATAHI = { IN7=='1 & IN6=='1 & IN5=='1 & IN4=='1 & + IN3=='1 & IN2=='1 & IN1=='1 & IN0=='1 } + ENABLE = { CHANGED(EI,0) } + + TRISTATE: + ENABLE HI EIEO + A2_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,25NS,39NS), + ENABLE & TRN_HL, DELAY(-1,24NS,41NS), + DATAHI , DELAY(-1,11NS,17NS), + TRN_HL, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,23NS,35NS), + DELAY(-1,25NS,41NS) + ) + } + A1_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,25NS,39NS), + ENABLE & TRN_HL, DELAY(-1,24NS,41NS), + DATAHI , DELAY(-1,11NS,17NS), + TRN_HL, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,23NS,35NS), + DELAY(-1,25NS,41NS) + ) + } + A0_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,25NS,39NS), + ENABLE & TRN_HL, DELAY(-1,24NS,41NS), + DATAHI , DELAY(-1,11NS,17NS), + TRN_HL, DELAY(-1,20NS,30NS), + TRN_LH, DELAY(-1,23NS,35NS), + DELAY(-1,25NS,41NS) + ) + } + GS_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,11NS,17NS), + ENABLE & TRN_HL, DELAY(-1,14NS,36NS), + TRN_LH, DELAY(-1,38NS,55NS), + TRN_HL, DELAY(-1, 9NS,21NS), + DELAY(-1,38NS,55NS) + ) + } + EO_O = { + CASE ( + ENABLE & TRN_LH, DELAY(-1,17NS,26NS), + ENABLE & TRN_HL, DELAY(-1,25NS,40NS), + TRN_LH, DELAY(-1,11NS,18NS), + TRN_HL, DELAY(-1,26NS,40NS), + DELAY(-1,26NS,40NS) + ) + } * .ENDS * *$ *--------- * 74LS352 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS * * The TTL Data Book, 1988, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS352 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS352LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * ULS352DLY PINDLY (2,0,12) DPWR DGND + Y1 Y2 + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + PINDLY: + Y1_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,25NS,38NS), + CHANGED(G1BAR,0) & TRN_HL, DELAY(-1,21NS,32NS), + SELECT & TRN_LH, DELAY(-1,19NS,29NS), + DATA1 & TRN_HL, DELAY(-1,17NS,26NS), + CHANGED(G1BAR,0) & TRN_LH, DELAY(-1,16NS,24NS), + DATA1 & TRN_LH, DELAY(-1,13NS,20NS), + DELAY(-1,26NS,39NS) + ) + } + Y2_O = { + CASE( + SELECT & TRN_HL, DELAY(-1,25NS,38NS), + CHANGED(G2BAR,0) & TRN_HL, DELAY(-1,21NS,32NS), + SELECT & TRN_LH, DELAY(-1,19NS,29NS), + DATA2 & TRN_HL, DELAY(-1,17NS,26NS), + CHANGED(G2BAR,0) & TRN_LH, DELAY(-1,16NS,24NS), + DATA2 & TRN_LH, DELAY(-1,13NS,20NS), + DELAY(-1,26NS,39NS) + ) + } * .ENDS * *$ *--------- * 74LS353 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS * * The TTL Data Book, 1988, TI * JSW 8/24/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS353 G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I + 2C0_I 2C1_I 2C2_I 2C3_I Y1_O Y2_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS353LOG LOGICEXP(12,14) DPWR DGND + G1BAR_I G2BAR_I A_I B_I 1C0_I 1C1_I 1C2_I 1C3_I 2C0_I 2C1_I 2C2_I 2C3_I + G1BAR G2BAR A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 Y1 Y2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + A = { A_I } + B = { B_I } + 1C0 = { 1C0_I } + 1C1 = { 1C1_I } + 1C2 = { 1C2_I } + 1C3 = { 1C3_I } + 2C0 = { 2C0_I } + 2C1 = { 2C1_I } + 2C2 = { 2C2_I } + 2C3 = { 2C3_I } + G1 = { ~G1BAR } + G2 = { ~G2BAR } + ABAR = { ~A } + BBAR = { ~B } + I0 = { G1 & BBAR & ABAR & 1C0 } + I1 = { G1 & BBAR & A & 1C1 } + I2 = { G1 & B & ABAR & 1C2 } + I3 = { G1 & B & A & 1C3 } + I4 = { G2 & BBAR & ABAR & 2C0 } + I5 = { G2 & BBAR & A & 2C1 } + I6 = { G2 & B & ABAR & 2C2 } + I7 = { G2 & B & A & 2C3 } + Y1 = { ~(I0 | I1 | I2 | I3) } + Y2 = { ~(I4 | I5 | I6 | I7) } * ULS353DLY PINDLY (2,2,10) DPWR DGND + Y1 Y2 + G1BAR G2BAR + A B 1C0 1C1 1C2 1C3 2C0 2C1 2C2 2C3 + Y1_O Y2_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + BOOLEAN: + DATA1 = { (CHANGED(1C0,0) | CHANGED(1C1,0) | CHANGED(1C2,0) | + CHANGED(1C3,0)) } + DATA2 = { (CHANGED(2C0,0) | CHANGED(2C1,0) | CHANGED(2C2,0) | + CHANGED(2C3,0)) } + SELECT = { CHANGED(A,0) | CHANGED(B,0) } + TRISTATE: + ENABLE LO G1BAR + Y1_O = { + CASE( + TRN_ZH, DELAY(-1,11NS,23NS), + TRN_ZL, DELAY(-1,15NS,23NS), + TRN_HZ, DELAY(-1,27NS,41NS), + TRN_LZ, DELAY(-1,12NS,27NS), + SELECT & TRN_LH, DELAY(-1,20NS,45NS), + SELECT & TRN_HL, DELAY(-1,21NS,32NS), + DATA1 & TRN_LH, DELAY(-1,11NS,25NS), + DATA1 & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,28NS,46NS) + ) + } + TRISTATE: + ENABLE LO G2BAR + Y2_O = { + CASE( + TRN_ZH, DELAY(-1,11NS,23NS), + TRN_ZL, DELAY(-1,15NS,23NS), + TRN_HZ, DELAY(-1,27NS,41NS), + TRN_LZ, DELAY(-1,12NS,27NS), + SELECT & TRN_LH, DELAY(-1,20NS,45NS), + SELECT & TRN_HL, DELAY(-1,21NS,32NS), + DATA2 & TRN_LH, DELAY(-1,11NS,25NS), + DATA2 & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,28NS,46NS) + ) + } * .ENDS * *$ *--------- * 74LS354 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/REGISTERS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-26-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS354 G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I DCBAR_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS354LOG LOGICEXP(30,21) DPWR DGND + G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I DCBAR_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + QS2 QS2BAR QS1 QS1BAR QS0 QS0BAR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + G1BAR G2BAR G3 SCBAR S0 S1 S2 DCBAR + D0 D1 D2 D3 D4 D5 D6 D7 Y W ENABLE13 DC SC + D0_GATE + IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3 = { G3_I } + SCBAR = { SCBAR_I } + SC = { ~SCBAR } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + DCBAR = { DCBAR_I } + DC = { ~DCBAR } + * OUTPUT ASSIGNMENTS: + ENABLE13 = { ~G1BAR & ~G2BAR & G3 } + Y = { (QS2BAR & QS1BAR & QS0BAR & Q0) | + (QS2BAR & QS1BAR & QS0 & Q1) | + (QS2BAR & QS1 & QS0BAR & Q2) | + (QS2BAR & QS1 & QS0 & Q3) | + (QS2 & QS1BAR & QS0BAR & Q4) | + (QS2 & QS1BAR & QS0 & Q5) | + (QS2 & QS1 & QS0BAR & Q6) | + (QS2 & QS1 & QS0 & Q7) } + W = { ~Y } * U1 DLTCH(8) DPWR DGND $D_HI $D_HI DC + D0 D1 D2 D3 D4 D5 D6 D7 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS * U2 DLTCH(3) DPWR DGND $D_HI $D_HI SC + S0 S1 S2 + QS0 QS1 QS2 QS0BAR QS1BAR QS2BAR + D0_GFF IO_LS * ULS354DLY PINDLY (2,1,16) DPWR DGND + Y W + ENABLE13 + D0 D1 D2 D3 D4 D5 D6 D7 DCBAR S0 S1 S2 SCBAR G1BAR G2BAR G3 + Y_O W_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + D_CHANGE = { (CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) + | CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0)) + & DCBAR!='1 } + DCBAR_CHANGE = { CHANGED(DCBAR,0) } + SCBAR_CHANGE = { CHANGED(SCBAR,0) } + S_CHANGE = { (CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0)) & SCBAR!='1 } + G12_CHANGE = { CHANGED(G1BAR,0) | CHANGED(G2BAR,0) } + G3_CHANGE = { CHANGED(G3,0) } + + TRISTATE: + ENABLE HI ENABLE13 + Y_O = { + CASE( + SCBAR_CHANGE & TRN_LH, DELAY(-1,34NS,51NS), + SCBAR_CHANGE & TRN_HL, DELAY(-1,31NS,47NS), + S_CHANGE & TRN_LH, DELAY(-1,29NS,44NS), + S_CHANGE & TRN_HL, DELAY(-1,24NS,45NS), + DCBAR_CHANGE & TRN_LH, DELAY(-1,28NS,42NS), + DCBAR_CHANGE & TRN_HL, DELAY(-1,26NS,39NS), + D_CHANGE & TRN_LH, DELAY(-1,24NS,36NS), + D_CHANGE & TRN_HL, DELAY(-1,23NS,35NS), + G3_CHANGE & TRN_ZH, DELAY(-1,15NS,29NS), + G3_CHANGE & TRN_ZL, DELAY(-1,19NS,29NS), + G12_CHANGE & TRN_ZH, DELAY(-1,14NS,27NS), + G12_CHANGE & TRN_ZL, DELAY(-1,18NS,27NS), + TRN_$Z, DELAY(-1,15NS,25NS), + DELAY(-1,35NS,52NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE HI ENABLE13 + W_O = { + CASE( + SCBAR_CHANGE & TRN_HL, DELAY(-1,40NS,60NS), + S_CHANGE & TRN_HL, DELAY(-1,34NS,51NS), + DCBAR_CHANGE & TRN_HL, DELAY(-1,33NS,50NS), + D_CHANGE & TRN_HL, DELAY(-1,29NS,44NS), + S_CHANGE & TRN_LH, DELAY(-1,28NS,42NS), + SCBAR_CHANGE & TRN_LH, DELAY(-1,27NS,41NS), + DCBAR_CHANGE & TRN_LH, DELAY(-1,22NS,33NS), + D_CHANGE & TRN_LH, DELAY(-1,18NS,27NS), + TRN_$Z, DELAY(-1,15NS,25NS), + G3_CHANGE & TRN_ZH, DELAY(-1,13NS,25NS), + G3_CHANGE & TRN_ZL, DELAY(-1,17NS,25NS), + G12_CHANGE & TRN_ZH, DELAY(-1,12NS,24NS), + G12_CHANGE & TRN_ZL, DELAY(-1,16NS,24NS), + DELAY(-1,41NS,61NS) ;DEFAULT + ) + } + + SETUP_HOLD: + DATA(8) = D0 D1 D2 D3 D4 D5 D6 D7 + CLOCK LH = DCBAR + SETUPTIME = 15NS + HOLDTIME = 15NS * .ENDS * *$ *-------------------------------------------------------------------------- * 74LS355 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/REGISTERS WITH * OPEN-COLLECTOR OUPUTS. * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-26-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS355 G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I DCBAR_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS355LOG LOGICEXP(30,20) DPWR DGND + G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I DCBAR_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + QS2 QS2BAR QS1 QS1BAR QS0 QS0BAR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + G1BAR G2BAR G3 SCBAR S0 S1 S2 DCBAR + D0 D1 D2 D3 D4 D5 D6 D7 Y W DC SC + D0_GATE + IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3 = { G3_I } + SCBAR = { SCBAR_I } + SC = { ~SCBAR } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + DCBAR = { DCBAR_I } + DC = { ~DCBAR } + Y_INTERNAL = { (QS2BAR & QS1BAR & QS0BAR & Q0) | + (QS2BAR & QS1BAR & QS0 & Q1) | + (QS2BAR & QS1 & QS0BAR & Q2) | + (QS2BAR & QS1 & QS0 & Q3) | + (QS2 & QS1BAR & QS0BAR & Q4) | + (QS2 & QS1BAR & QS0 & Q5) | + (QS2 & QS1 & QS0BAR & Q6) | + (QS2 & QS1 & QS0 & Q7) } + W_INTERNAL = { ~Y_INTERNAL } + * OUTPUT ASSIGNMENTS: + ENABLEBAR = { G1BAR | G2BAR | ~G3 } + Y = { Y_INTERNAL | ENABLEBAR } + W = { W_INTERNAL | ENABLEBAR } * U1 DLTCH(8) DPWR DGND $D_HI $D_HI DC + D0 D1 D2 D3 D4 D5 D6 D7 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS * U2 DLTCH(3) DPWR DGND $D_HI $D_HI SC + S0 S1 S2 + QS0 QS1 QS2 + QS0BAR QS1BAR QS2BAR + D0_GFF IO_LS * ULS355DLY PINDLY (2,0,16) DPWR DGND + Y W + D0 D1 D2 D3 D4 D5 D6 D7 DCBAR S0 S1 S2 SCBAR G1BAR G2BAR G3 + Y_O W_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + EN = { G1BAR!='1 & G2BAR!='1 & G3!='0 } + G12_CHANGE = { CHANGED(G1BAR,0) | CHANGED(G2BAR,0) } + G3_CHANGE = { CHANGED(G3,0) } + D_CHANGE = { (CHANGED(D0,0) | CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) + | CHANGED(D4,0) | CHANGED(D5,0) | CHANGED(D6,0) | CHANGED(D7,0)) + & EN & DCBAR!='1 } + DCBAR_CHANGE = { CHANGED(DCBAR,0) & EN } + SCBAR_CHANGE = { CHANGED(SCBAR,0) & EN } + S_CHANGE ={ (CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0)) & EN & SCBAR!='1} + PINDLY: + Y_O = { + CASE( + SCBAR_CHANGE & TRN_LH, DELAY(-1,45NS,68NS), + SCBAR_CHANGE & TRN_HL, DELAY(-1,42NS,63NS), + S_CHANGE & TRN_LH, DELAY(-1,39NS,59NS), + DCBAR_CHANGE & TRN_LH, DELAY(-1,38NS,57NS), + S_CHANGE & TRN_HL, DELAY(-1,36NS,49NS), + DCBAR_CHANGE & TRN_HL, DELAY(-1,31NS,47NS), + D_CHANGE & TRN_LH, DELAY(-1,34NS,41NS), + G3_CHANGE & TRN_HL, DELAY(-1,25NS,40NS), + D_CHANGE & TRN_HL, DELAY(-1,26NS,39NS), + G3_CHANGE & TRN_LH, DELAY(-1,24NS,36NS), + G12_CHANGE & TRN_HL, DELAY(-1,22NS,33NS), + G12_CHANGE & TRN_LH, DELAY(-1,21NS,32NS), + DELAY(-1,46NS,69NS) ;DEFAULT + ) + } + + W_O = { + CASE( + SCBAR_CHANGE & TRN_HL, DELAY(-1,45NS,68NS), + SCBAR_CHANGE & TRN_LH, DELAY(-1,44NS,66NS), + DCBAR_CHANGE & TRN_HL, DELAY(-1,39NS,59NS), + S_CHANGE & TRN_HL, DELAY(-1,39NS,58NS), + DCBAR_CHANGE & TRN_LH, DELAY(-1,33NS,50NS), + D_CHANGE & TRN_HL, DELAY(-1,33NS,50NS), + S_CHANGE & TRN_LH, DELAY(-1,32NS,48NS), + D_CHANGE & TRN_LH, DELAY(-1,30NS,45NS), + G3_CHANGE & TRN_LH, DELAY(-1,19NS,31NS), + (G3_CHANGE | G12_CHANGE) & TRN_HL, DELAY(-1,19NS,29NS), + G12_CHANGE & TRN_LH, DELAY(-1,18NS,27NS), + DELAY(-1,46NS,69NS) ;DEFAULT + ) + } + + SETUP_HOLD: + DATA(8) = D0 D1 D2 D3 D4 D5 D6 D7 + CLOCK LH = DCBAR + SETUPTIME = 15NS + HOLDTIME = 15NS * .ENDS * *$ *--------- * 74LS356 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/REGISTERS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-26-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS356 G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I CLK_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS356LOG LOGICEXP(30,20) DPWR DGND + G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I CLK_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + QS2 QS2BAR QS1 QS1BAR QS0 QS0BAR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + G1BAR G2BAR G3 SCBAR S0 S1 S2 CLK + D0 D1 D2 D3 D4 D5 D6 D7 Y W ENABLE13 SC + D0_GATE + IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3 = { G3_I } + SCBAR = { SCBAR_I } + SC = { ~SCBAR } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + CLK = { CLK_I } + * OUTPUT ASSIGNMENTS: + ENABLE13 = { ~G1BAR & ~G2BAR & G3 } + Y = { (QS2BAR & QS1BAR & QS0BAR & Q0) | + (QS2BAR & QS1BAR & QS0 & Q1) | + (QS2BAR & QS1 & QS0BAR & Q2) | + (QS2BAR & QS1 & QS0 & Q3) | + (QS2 & QS1BAR & QS0BAR & Q4) | + (QS2 & QS1BAR & QS0 & Q5) | + (QS2 & QS1 & QS0BAR & Q6) | + (QS2 & QS1 & QS0 & Q7) } + W = { ~Y } * U1 DFF(8) DPWR DGND $D_HI $D_HI CLK + D0 D1 D2 D3 D4 D5 D6 D7 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U2 DLTCH(3) DPWR DGND $D_HI $D_HI SC + S0 S1 S2 + QS0 QS1 QS2 QS0BAR QS1BAR QS2BAR + D0_GFF IO_LS * ULS356DLY PINDLY (2,1,16) DPWR DGND + Y W + ENABLE13 + D0 D1 D2 D3 D4 D5 D6 D7 CLK S0 S1 S2 SCBAR G1BAR G2BAR G3 + Y_O W_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLK_CHANGE = { CHANGED(CLK,0) } + SCBAR_CHANGE = { CHANGED(SCBAR,0) } + S_CHANGE = { (CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0)) & SCBAR!='1 } + G12_CHANGE = { CHANGED(G1BAR,0) | CHANGED(G2BAR,0) } + G3_CHANGE = { CHANGED(G3,0) } + + TRISTATE: + ENABLE HI ENABLE13 + Y_O = { + CASE( + SCBAR_CHANGE & TRN_HL, DELAY(-1,40NS,60NS), + SCBAR_CHANGE & TRN_LH, DELAY(-1,36NS,54NS), + CLK_CHANGE & TRN_HL, DELAY(-1,33NS,50NS), + S_CHANGE & TRN_HL, DELAY(-1,28NS,48NS), + S_CHANGE & TRN_LH, DELAY(-1,30NS,45NS), + CLK_CHANGE & TRN_LH, DELAY(-1,18NS,27NS), + G3_CHANGE & TRN_ZH, DELAY(-1,15NS,27NS), + G3_CHANGE & TRN_ZL, DELAY(-1,18NS,27NS), + G3_CHANGE & TRN_$Z, DELAY(-1,16NS,25NS), + G12_CHANGE & TRN_ZH, DELAY(-1,14NS,25NS), + G12_CHANGE & TRN_ZL, DELAY(-1,17NS,25NS), + G12_CHANGE & TRN_$Z, DELAY(-1,16NS,24NS), + DELAY(-1,41NS,61NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE HI ENABLE13 + W_O = { + CASE( + SCBAR_CHANGE & TRN_HL, DELAY(-1,36NS,54NS), + S_CHANGE & TRN_LH, DELAY(-1,36NS,54NS), + SCBAR_CHANGE & TRN_LH, DELAY(-1,32NS,48NS), + S_CHANGE & TRN_HL, DELAY(-1,30NS,45NS), + CLK_CHANGE & TRN_LH, DELAY(-1,24NS,36NS), + CLK_CHANGE & TRN_HL, DELAY(-1,18NS,27NS), + G3_CHANGE & TRN_ZH, DELAY(-1,14NS,25NS), + G3_CHANGE & TRN_ZL, DELAY(-1,16NS,25NS), + G3_CHANGE & TRN_$Z, DELAY(-1,16NS,25NS), + G12_CHANGE & TRN_ZH, DELAY(-1,14NS,23NS), + G12_CHANGE & TRN_ZL, DELAY(-1,16NS,23NS), + G12_CHANGE & TRN_$Z, DELAY(-1,16NS,23NS), + DELAY(-1,37NS,55NS) ;DEFAULT + ) + } + + SETUP_HOLD: + DATA(8) = D0 D1 D2 D3 D4 D5 D6 D7 + CLOCK LH = CLK + SETUPTIME = 15NS * .ENDS * *$ *-------------------------------------------------------------------------- * 74LS357 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS/REGISTERS * WITH OPEN-COLLECTOR OUTPUTS * THE TTL DATABOOK, 1985, TI , DISCONTINUED * KN 8-26-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS357 G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I CLK_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I Y_O W_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS357LOG LOGICEXP(30,19) DPWR DGND + G1BAR_I G2BAR_I G3_I SCBAR_I S0_I S1_I S2_I CLK_I + D0_I D1_I D2_I D3_I D4_I D5_I D6_I D7_I + QS2 QS2BAR QS1 QS1BAR QS0 QS0BAR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 + G1BAR G2BAR G3 SCBAR S0 S1 S2 CLK + D0 D1 D2 D3 D4 D5 D6 D7 Y W SC + D0_GATE + IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + D0 = { D0_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + D5 = { D5_I } + D6 = { D6_I } + D7 = { D7_I } + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + G3 = { G3_I } + SCBAR = { SCBAR_I } + SC = { ~SCBAR } + S0 = { S0_I } + S1 = { S1_I } + S2 = { S2_I } + CLK = { CLK_I } + Y_INTERNAL = { (QS2BAR & QS1BAR & QS0BAR & Q0) | + (QS2BAR & QS1BAR & QS0 & Q1) | + (QS2BAR & QS1 & QS0BAR & Q2) | + (QS2BAR & QS1 & QS0 & Q3) | + (QS2 & QS1BAR & QS0BAR & Q4) | + (QS2 & QS1BAR & QS0 & Q5) | + (QS2 & QS1 & QS0BAR & Q6) | + (QS2 & QS1 & QS0 & Q7) } + W_INTERNAL = { ~Y_INTERNAL } + ENABLEBAR = { G1BAR | G2BAR | ~G3 } + * OUTPUT ASSIGNMENTS: + Y = { Y_INTERNAL | ENABLEBAR } + W = { W_INTERNAL | ENABLEBAR } + * U1 DFF(8) DPWR DGND $D_HI $D_HI CLK + D0 D1 D2 D3 D4 D5 D6 D7 + Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U2 DLTCH(3) DPWR DGND $D_HI $D_HI SC + S0 S1 S2 + QS0 QS1 QS2 QS0BAR QS1BAR QS2BAR + D0_GFF IO_LS * ULS357DLY PINDLY (2,0,16) DPWR DGND + Y W + D0 D1 D2 D3 D4 D5 D6 D7 CLK S0 S1 S2 SCBAR G1BAR G2BAR G3 + Y_O W_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLK_CHANGE = { CHANGED(CLK,0) } + SCBAR_CHANGE = { CHANGED(SCBAR,0) } + S_CHANGE = { (CHANGED(S0,0) | CHANGED(S1,0) | CHANGED(S2,0)) & SCBAR!='1 } + G12_CHANGE = { CHANGED(G1BAR,0) | CHANGED(G2BAR,0) } + G3_CHANGE = { CHANGED(G3,0) } + + PINDLY: + Y_O = { + CASE( + SCBAR_CHANGE & TRN_LH, DELAY(-1,44NS,66NS), + SCBAR_CHANGE & TRN_HL, DELAY(-1,41NS,62NS), + S_CHANGE & TRN_HL, DELAY(-1,40NS,60NS), + S_CHANGE & TRN_LH, DELAY(-1,38NS,57NS), + CLK_CHANGE & TRN_HL, DELAY(-1,34NS,51NS), + CLK_CHANGE & TRN_LH, DELAY(-1,27NS,41NS), + G3_CHANGE, DELAY(-1,24NS,36NS), + G12_CHANGE, DELAY(-1,18NS,27NS), + DELAY(-1,42NS,67NS) ;DEFAULT + ) + } + + W_O = { + CASE( + SCBAR_CHANGE, DELAY(-1,41NS,62NS), + S_CHANGE & TRN_LH, DELAY(-1,38NS,57NS), + S_CHANGE & TRN_HL, DELAY(-1,35NS,53NS), + CLK_CHANGE & TRN_LH, DELAY(-1,32NS,48NS), + CLK_CHANGE & TRN_HL, DELAY(-1,23NS,35NS), + G12_CHANGE & TRN_HL, DELAY(-1,21NS,32NS), + G12_CHANGE & TRN_LH, DELAY(-1,20NS,30NS), + G3_CHANGE & TRN_LH, DELAY(-1,19NS,31NS), + G3_CHANGE & TRN_HL, DELAY(-1,19NS,29NS), + DELAY(-1,42NS,58NS) ;DEFAULT + ) + } + + SETUP_HOLD: + DATA(8) = D0 D1 D2 D3 D4 D5 D6 D7 + CLOCK LH = CLK + SETUPTIME = 15NS * .ENDS * *$ *--------- * 74LS365A Hex Bus Drivers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS365A A1 A2 A3 A4 A5 A6 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf3a(6) DPWR DGND + A1 A2 A3 A4 A5 A6 + E + Y1 Y2 Y3 Y4 Y5 Y6 + D_LS365 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS365 utgate ( + tplhty=10ns tplhmx=16ns + tphlty=9ns tphlmx=22ns + tpzhty=19ns tpzhmx=35ns + tpzlty=24ns tpzlmx=40ns + tphzmx=30ns tplzmx=35ns + ) *$ *--------- * 74LS366A Hex Bus Drivers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 06/27/89 Update interface and model names * .subckt 74LS366A A1 A2 A3 A4 A5 A6 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv3a(6) DPWR DGND + A1 A2 A3 A4 A5 A6 + E + Y1 Y2 Y3 Y4 Y5 Y6 + D_LS366 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS366 utgate ( + tplhty=7ns tplhmx=15ns + tphlty=12ns tphlmx=18ns + tpzhty=18ns tpzhmx=35ns + tpzlty=28ns tpzlmx=45ns + tphzmx=32ns tplzmx=35ns + ) *$ *--------- * 74LS367A Hex Bus Drivers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS367A 1A1 1A2 1A3 1A4 2A1 2A2 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS367 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(2) DPWR DGND + 2A1 2A2 G2 2Y1 2Y2 + D_LS367 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS367 utgate ( + tplhty=10ns tplhmx=16ns + tphlty=9ns tphlmx=22ns + tpzhty=19ns tpzhmx=35ns + tpzlty=24ns tpzlmx=40ns + tphzmx=30ns tplzmx=35ns + ) *$ *--------- * 74LS368A Hex Bus Drivers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS368A 1A1 1A2 1A3 1A4 2A1 2A2 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS368A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(2) DPWR DGND + 2A1 2A2 G2 2Y1 2Y2 + D_LS368A IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS368A utgate ( + tplhty=7ns tplhmx=15ns + tphlty=12ns tphlmx=18ns + tpzhty=18ns tpzhmx=35ns + tpzlty=28ns tpzlmx=45ns + tphzmx=32ns tplzmx=35ns + ) *$ *--------- * 74LS373 Octal D-Type Transparent Latches with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS373 OCBAR C 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + OCBAR OC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 dltch(8) DPWR DGND + $D_HI $D_HI C + 1D 2D 3D 4D 5D 6D 7D 8D + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_LS373_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 buf3a(8) DPWR DGND + 1QI 2QI 3QI 4QI 5QI 6QI 7QI 8QI + OC + 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + D_LS373_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS373_1 ugff ( + tpgqlhty=8ns tpgqlhmx=12ns + tpgqhlty=6ns tpgqhlmx=12ns + twghmn=15ns tsudgmn=5ns + thdgmn=20ns + ) .model D_LS373_2 utgate ( + tplhty=12ns tplhmx=18ns + tphlty=12ns tphlmx=18ns + tpzhty=15ns tpzhmx=28ns + tpzlty=25ns tpzlmx=36ns + tphzty=15ns tphzmx=25ns + tplzty=12ns tplzmx=20ns + ) *$ *--------- * 74LS374 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS374 OCBAR CLK D1 D2 D3 D4 D5 D6 D7 D8 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UOC inv DPWR DGND + OCBAR OC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UD dff(8) DPWR DGND + $D_HI $D_HI CLK + D1 D2 D3 D4 D5 D6 D7 D8 + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D_LS374_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UQS buf3a(8) DPWR DGND + SQ1 SQ2 SQ3 SQ4 SQ5 SQ6 SQ7 SQ8 + OC + Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 + D_LS374_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS374_1 ueff ( + twclklmn=15ns twclkhmn=15ns + tsudclkmn=20ns + ) .model D_LS374_2 utgate ( + tplhty=15ns tplhmx=28ns + tphlty=19ns tphlmx=28ns + tpzhty=20ns tpzhmx=26ns + tpzlty=21ns tpzlmx=28ns + tphzty=15ns tphzmx=28ns + tplzty=12ns tplzmx=20ns + ) *$ *--------- * 74LS375 4-bit Bistable Latches * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS375 1D 2D C 1Q 1QBAR 2Q 2QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 * Note: The 74LS375 bistable latches are electrically and functionally * identical to the 74LS75. * X1 1D 2D C 1Q 1QBAR 2Q 2QBAR DPWR DGND 74LS75 + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * *$ *--------- * 74LS377 Octal D-TYPE Flip-Flops with Clock Enable * * The TTL Data Book, Vol 2, 1985, TI * atl 8/7/89 Update interface and model names * .subckt 74LS377 GBAR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + GBAR CLK GBBUF CLKBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1Q GBBUF CLKBUF 1D 1Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2Q GBBUF CLKBUF 2D 2Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3Q GBBUF CLKBUF 3D 3Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4Q GBBUF CLKBUF 4D 4Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X5Q GBBUF CLKBUF 5D 5Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X6Q GBBUF CLKBUF 6D 6Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X7Q GBBUF CLKBUF 7D 7Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X8Q GBBUF CLKBUF 8D 8Q DPWR DGND LS377DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS377DAT GB CLK D Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + D DBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} USET inv DPWR DGND + GB G2 + D_LS377_1 IO_LS MNTYMXDLY={MNTYMXDLY} UNXOR nxor DPWR DGND + GB G2 EN + D0_GATE IO_LS UIN buf3 DPWR DGND + $D_X EN IN + D0_TGATE IO_LS UD1 buf DPWR DGND + DBUF DX + D0_GATE IO_LS UD2 buf DPWR DGND + DBUF DX + D_LS377_2 IO_LS MNTYMXDLY={MNTYMXDLY} UINV inv DPWR DGND + GB G + D0_GATE IO_LS UAO ao(2,2) DPWR DGND + G DX GB QBUF IN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UDFF dff(1) DPWR DGND + $D_HI $D_HI CLK IN QBUF $D_NC + D_LS377_3 IO_LS MNTYMXDLY={MNTYMXDLY} UQOUT buf DPWR DGND + QBUF Q + D_LS377_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS377_1 ugate ( + tphlmn=15ns + ) .model D_LS377_2 ugate ( + tplhmn=10ns tphlmn=10ns + ) .model D_LS377_3 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=10ns thdclkmn=5ns + ) .model D_LS377_4 ugate ( + tplhty=17ns tplhmx=27ns + tphlty=18ns tphlmx=27ns + ) *$ *--------- * 74LS378 Octal D-TYPE Flip-Flops with Clock Enable * * The TTL Data Book, Vol 2, 1985, TI * atl 8/7/89 Update interface and model names * .subckt 74LS378 CLK GBAR 1D 2D 3D 4D 5D 6D 1Q 2Q 3Q 4Q 5Q 6Q + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + GBAR CLK GBBUF CLKBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1Q GBBUF CLKBUF 1D 1Q DPWR DGND LS378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2Q GBBUF CLKBUF 2D 2Q DPWR DGND LS378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3Q GBBUF CLKBUF 3D 3Q DPWR DGND LS378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4Q GBBUF CLKBUF 4D 4Q DPWR DGND LS378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X5Q GBBUF CLKBUF 5D 5Q DPWR DGND LS378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X6Q GBBUF CLKBUF 6D 6Q DPWR DGND LS378DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS378DAT GB CLK D Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + D DBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} USET inv DPWR DGND + GB G2 + D_LS378_1 IO_LS MNTYMXDLY={MNTYMXDLY} UNXOR nxor DPWR DGND + GB G2 EN + D0_GATE IO_LS UIN buf3 DPWR DGND + $D_X EN IN + D0_TGATE IO_LS UD1 buf DPWR DGND + DBUF DX + D0_GATE IO_LS UD2 buf DPWR DGND + DBUF DX + D_LS378_2 IO_LS MNTYMXDLY={MNTYMXDLY} UINV inv DPWR DGND + GB G + D0_GATE IO_LS UAO ao(2,2) DPWR DGND + G DX GB QBUF IN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UDFF dff(1) DPWR DGND + $D_HI $D_HI CLK IN QBUF $D_NC + D_LS378_3 IO_LS MNTYMXDLY={MNTYMXDLY} UQOUT buf DPWR DGND + QBUF Q + D_LS378_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS378_1 ugate ( + tphlmn=15ns + ) .model D_LS378_2 ugate ( + tplhmn=10ns tphlmn=10ns + ) .model D_LS378_3 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=10ns thdclkmn=5ns + ) .model D_LS378_4 ugate ( + tplhty=17ns tplhmx=27ns + tphlty=18ns tphlmx=27ns + ) *$ *--------- * 74LS379 Octal D-TYPE Flip-Flops with Clock Enable * * The TTL Data Book, Vol 2, 1985, TI * atl 8/7/89 Update interface and model names * .subckt 74LS379 CLK GBAR 1D 2D 3D 4D 1Q 1QBAR 2Q 2QBAR 3Q 3QBAR 4Q 4QBAR + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + GBAR CLK GBBUF CLKBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} X1Q GBBUF CLKBUF 1D 1Q 1QBAR DPWR DGND LS379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2Q GBBUF CLKBUF 2D 2Q 2QBAR DPWR DGND LS379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3Q GBBUF CLKBUF 3D 3Q 3QBAR DPWR DGND LS379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4Q GBBUF CLKBUF 4D 4Q 4QBAR DPWR DGND LS379DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS379DAT GB CLK D Q QB DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + D DBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} USET inv DPWR DGND + GB G2 + D_LS379_1 IO_LS MNTYMXDLY={MNTYMXDLY} UNXOR nxor DPWR DGND + GB G2 EN + D0_GATE IO_LS UIN buf3 DPWR DGND + $D_X EN IN + D0_TGATE IO_LS UD1 buf DPWR DGND + DBUF DX + D0_GATE IO_LS UD2 buf DPWR DGND + DBUF DX + D_LS379_2 IO_LS MNTYMXDLY={MNTYMXDLY} UINV inv DPWR DGND + GB G + D0_GATE IO_LS UAO ao(2,2) DPWR DGND + G DX GB QBUF IN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UDFF dff(1) DPWR DGND + $D_HI $D_HI CLK IN QBUF QBBUF + D_LS379_3 IO_LS MNTYMXDLY={MNTYMXDLY} UQOUT bufa(2) DPWR DGND + QBUF QBBUF Q QB + D_LS379_4 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS379_1 ugate ( + tphlmn=15ns + ) .model D_LS379_2 ugate ( + tplhmn=10ns tphlmn=10ns + ) .model D_LS379_3 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=10ns thdclkmn=5ns + ) .model D_LS379_4 ugate ( + tplhty=17ns tplhmx=27ns + tphlty=18ns tphlmx=27ns + ) * *$ *--------- * 74LS381A ALU / FUNCTION GENERATOR * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-8-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE: THE GBAR AND PBAR OUTPUTS OF THE 74LS381A ARE FUNCTIONALLY * DIFFERENT THAN THE AC,ACT,F,S FAMILIES. * .SUBCKT 74LS381A S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + F3_O F2_O F1_O F0_O PBAR_O GBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS381LOG LOGICEXP (12,18) DPWR DGND + S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3 F2 F1 F0 PBAR GBAR + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + S2 = { S2_I } + S1 = { S1_I } + S0 = { S0_I } + CN = { CN_I } + A3 = { A3_I } + A2 = { A2_I } + A1 = { A1_I } + A0 = { A0_I } + B3 = { B3_I } + B2 = { B2_I } + B1 = { B1_I } + B0 = { B0_I } + S2BAR = { ~S2 } + S1BAR = { ~S1 } + S0BAR = { ~S0 } + A3BAR = { ~A3 } + A2BAR = { ~A2 } + A1BAR = { ~A1 } + A0BAR = { ~A0 } + B3BAR = { ~B3 } + B2BAR = { ~B2 } + B1BAR = { ~B1 } + B0BAR = { ~B0 } + + L6 = { ~( (S0 & S1BAR & S2BAR) | (S0BAR & S1 & S2BAR) | (S0 & S1 & S2) ) } + L5 = { ~( (S0 & S1BAR ) | (S0BAR & S1 ) | (S0 & S2) ) } + L4 = { ~( ( S1BAR & S2 ) | (S0 & S1 ) ) } + L3 = { S0BAR | S1 | S2 } + L2 = { S0BAR | S1BAR | S2 } + L1 = { S0 | S1BAR | S2 } + L0 = { (S0 & S2BAR) | ( S1 & S2BAR) } + TOP0 = { ~( (A0BAR & B0BAR & L6) | (A0 & B0BAR & L4) | + (A0BAR & B0 & L4) | (A0 & B0 & L5) ) } + BOT0 = { ~( (A0BAR & B0BAR ) | (A0 & B0BAR & L1) | + (A0BAR & B0 & L3) | (A0 & B0 & L2) ) } + TOP1 = { ~( (A1BAR & B1BAR & L6) | (A1 & B1BAR & L4) | + (A1BAR & B1 & L4) | (A1 & B1 & L5) ) } + BOT1 = { ~( (A1BAR & B1BAR ) | (A1 & B1BAR & L1) | + (A1BAR & B1 & L3) | (A1 & B1 & L2) ) } + TOP2 = { ~( (A2BAR & B2BAR & L6) | (A2 & B2BAR & L4) | + (A2BAR & B2 & L4) | (A2 & B2 & L5) ) } + BOT2 = { ~( (A2BAR & B2BAR ) | (A2 & B2BAR & L1) | + (A2BAR & B2 & L3) | (A2 & B2 & L2) ) } + TOP3 = { ~( (A3BAR & B3BAR & L6) | (A3 & B3BAR & L4) | + (A3BAR & B3 & L4) | (A3 & B3 & L5) ) } + BOT3 = { ~( (A3BAR & B3BAR ) | (A3 & B3BAR & L1) | + (A3BAR & B3 & L3) | (A3 & B3 & L2) ) } + + F0 = { ~(TOP0 ^ ~( CN & L0) ) } + F1 = { ~(TOP1 ^ ~( ( CN & L0 & TOP0) | + (BOT0 & L0 ) ) ) } + F2 = { ~(TOP2 ^ ~( ( CN & L0 & TOP0 & TOP1) | + (BOT0 & L0 & TOP1) | + (BOT1 & L0 ) ) ) } + F3 = { ~(TOP3 ^ ~( ( CN & L0 & TOP0 & TOP1 & TOP2) | + (BOT0 & L0 & TOP1 & TOP2) | + (BOT1 & L0 & TOP2) | + (BOT2 & L0 ) ) ) } + PBAR = { ~(TOP0 & TOP1 & TOP2 & TOP3) } + GBAR = { ~( (TOP1 & TOP2 & TOP3 & BOT0) | + (TOP2 & TOP3 & BOT1) | + (TOP3 & BOT2) | + (BOT3) ) } * ULS381DLY PINDLY (6,0,12) DPWR DGND + F3 F2 F1 F0 PBAR GBAR + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3_O F2_O F1_O F0_O PBAR_O GBAR_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3,0) | CHANGED(A2,0) | CHANGED(A1,0) | CHANGED(A0,0) | + CHANGED(B3,0) | CHANGED(B2,0) | CHANGED(B1,0) | CHANGED(B0,0) } + MODE = { CHANGED(S2,0) | CHANGED(S1,0) | CHANGED(S0,0) } + + PINDLY: + F3_O F2_O F1_O F0_O = { + CASE ( + CARRY & TRN_LH, DELAY(-1,18NS,27NS), + CARRY & TRN_HL, DELAY(-1,14NS,21NS), + OPER & TRN_LH, DELAY(-1,20NS,30NS), + OPER & TRN_HL, DELAY(-1,15NS,23NS), + MODE & TRN_LH, DELAY(-1,35NS,53NS), + MODE & TRN_HL, DELAY(-1,34NS,51NS), + DELAY(-1,35NS,53NS) + ) + } + GBAR_O = { + CASE ( + OPER & TRN_LH, DELAY(-1,20NS,30NS), + OPER & TRN_HL, DELAY(-1,21NS,33NS), + MODE & TRN_LH, DELAY(-1,31NS,47NS), + MODE & TRN_HL, DELAY(-1,32NS,48NS), + DELAY(-1,32NS,48NS) + ) + } + PBAR_O = { + CASE ( + OPER & TRN_LH, DELAY(-1,21NS,33NS), + OPER & TRN_HL, DELAY(-1,23NS,33NS), + MODE & TRN_LH, DELAY(-1,31NS,47NS), + MODE & TRN_HL, DELAY(-1,32NS,48NS), + DELAY(-1,32NS,48NS) + ) + } * .ENDS * *$ *--------- * 74LS382 ALU / FUNCTION GENERATOR * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-8-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS382 S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + F3_O F2_O F1_O F0_O OVR_O CN+4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS382ALOG LOGICEXP (12,18) DPWR DGND + S2_I S1_I S0_I CN_I A3_I A2_I A1_I A0_I B3_I B2_I B1_I B0_I + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3 F2 F1 F0 OVR CN+4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + S2 = { S2_I } + S1 = { S1_I } + S0 = { S0_I } + CN = { CN_I } + A3 = { A3_I } + A2 = { A2_I } + A1 = { A1_I } + A0 = { A0_I } + B3 = { B3_I } + B2 = { B2_I } + B1 = { B1_I } + B0 = { B0_I } + S2BAR = { ~S2 } + S1BAR = { ~S1 } + S0BAR = { ~S0 } + A3BAR = { ~A3 } + A2BAR = { ~A2 } + A1BAR = { ~A1 } + A0BAR = { ~A0 } + B3BAR = { ~B3 } + B2BAR = { ~B2 } + B1BAR = { ~B1 } + B0BAR = { ~B0 } + + L6 = { ~( (S0 & S1BAR & S2BAR) | (S0 & S1 & S2) | + (S0BAR & S1 & S2BAR) ) } + L5 = { ~( (S0 & S1BAR ) | (S0 & S2) | + (S0BAR & S1 ) ) } + L4 = { ~( ( S1BAR & S2 ) | (S0 & S1 ) ) } + L3 = { S0BAR | S1 | S2 } + L2 = { S0BAR | S1BAR | S2 } + L1 = { S0 | S1BAR | S2 } + L0 = { (S0 & S2BAR) | ( S1 & S2BAR) } + TOP0 = { ~( (A0BAR & B0BAR & L6) | (A0 & B0BAR & L4) | + (A0BAR & B0 & L4) | (A0 & B0 & L5) ) } + BOT0 = { ~( (A0BAR & B0BAR ) | (A0 & B0BAR & L1) | + (A0BAR & B0 & L3) | (A0 & B0 & L2) ) } + TOP1 = { ~( (A1BAR & B1BAR & L6) | (A1 & B1BAR & L4) | + (A1BAR & B1 & L4) | (A1 & B1 & L5) ) } + BOT1 = { ~( (A1BAR & B1BAR ) | (A1 & B1BAR & L1) | + (A1BAR & B1 & L3) | (A1 & B1 & L2) ) } + TOP2 = { ~( (A2BAR & B2BAR & L6) | (A2 & B2BAR & L4) | + (A2BAR & B2 & L4) | (A2 & B2 & L5) ) } + BOT2 = { ~( (A2BAR & B2BAR ) | (A2 & B2BAR & L1) | + (A2BAR & B2 & L3) | (A2 & B2 & L2) ) } + TOP3 = { ~( (A3BAR & B3BAR & L6) | (A3 & B3BAR & L4) | + (A3BAR & B3 & L4) | (A3 & B3 & L5) ) } + BOT3 = { ~( (A3BAR & B3BAR ) | (A3 & B3BAR & L1) | + (A3BAR & B3 & L3) | (A3 & B3 & L2) ) } + + F0 = { ~(TOP0 ^ ~( CN & L0) ) } + F1 = { ~(TOP1 ^ ~( ( CN & L0 & TOP0) | + (BOT0 & L0 ) ) ) } + F2 = { ~(TOP2 ^ ~( ( CN & L0 & TOP0 & TOP1) | + (BOT0 & L0 & TOP1) | + (BOT1 & L0 ) ) ) } + PRE3 = { ~( ( CN & L0 & TOP0 & TOP1 & TOP2) | + (BOT0 & L0 & TOP1 & TOP2) | + (BOT1 & L0 & TOP2) | + (BOT2 & L0 ) ) } + F3 = { ~(TOP3 ^ PRE3) } + CN+4 = { (TOP0 & TOP1 & TOP2 & TOP3 & CN) | + (TOP1 & TOP2 & TOP3 & BOT0) | + (TOP2 & TOP3 & BOT1) | + (TOP3 & BOT2) | + (BOT3) } + OVR = { ~CN+4 ^ PRE3 } * ULS382ADLY PINDLY (6,0,12) DPWR DGND + F3 F2 F1 F0 OVR CN+4 + S2 S1 S0 CN A3 A2 A1 A0 B3 B2 B1 B0 + F3_O F2_O F1_O F0_O OVR_O CN+4_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CARRY = { CHANGED(CN,0) } + OPER = { CHANGED(A3,0) | CHANGED(A2,0) | CHANGED(A1,0) | CHANGED(A0,0) | + CHANGED(B3,0) | CHANGED(B2,0) | CHANGED(B1,0) | CHANGED(B0,0) } + MODE = { CHANGED(S2,0) | CHANGED(S1,0) | CHANGED(S0,0) } + + PINDLY: + F3_O F2_O F1_O F0_O = { + CASE ( + CARRY & TRN_LH, DELAY(-1,18NS,27NS), + CARRY & TRN_HL, DELAY(-1,14NS,21NS), + OPER & TRN_LH, DELAY(-1,20NS,30NS), + OPER & TRN_HL, DELAY(-1,15NS,23NS), + MODE & TRN_LH, DELAY(-1,35NS,53NS), + MODE & TRN_HL, DELAY(-1,34NS,51NS), + DELAY(-1,35NS,53NS) + ) + } + OVR_O = { + CASE ( + CARRY & TRN_LH, DELAY(-1,10NS,15NS), + CARRY & TRN_HL, DELAY(-1,13NS,23NS), + OPER & TRN_LH, DELAY(-1,23NS,35NS), + OPER & TRN_HL, DELAY(-1,27NS,41NS), + MODE & TRN_LH, DELAY(-1,38NS,57NS), + MODE & TRN_HL, DELAY(-1,36NS,54NS), + DELAY(-1,38NS,57NS) + ) + } + CN+4_O = { + CASE ( + CARRY & TRN_LH, DELAY(-1,13NS,21NS), + CARRY & TRN_HL, DELAY(-1,11NS,20NS), + OPER & TRN_LH, DELAY(-1,28NS,42NS), + OPER & TRN_HL, DELAY(-1,26NS,39NS), + MODE & TRN_LH, DELAY(-1,38NS,57NS), + MODE & TRN_HL, DELAY(-1,36NS,54NS), + DELAY(-1,38NS,57NS) + ) + } * .ENDS * *$ *--------- * 74LS386A Quadruple 2-Input Exclusive-OR-Gates * * The TTL Data Book, Vol 2, 1985, TI * atl 9/26/89 Update interface and model names * .subckt 74LS386A A B Y + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A B AF BF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UINV inva(2) DPWR DGND + AF BF AB BB + D_LS386A_1 IO_LS MNTYMXDLY={MNTYMXDLY} UY ao(2,2) DPWR DGND + BF AB AF BB Y + D_LS386A_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS386A_1 ugate ( + tplhty=8ns tplhmx=7ns + tphlty=3ns tphlmx=5ns + ) .model D_LS386A_2 ugate ( + tplhty=12ns tplhmx=23ns + tphlty=10ns tphlmx=17ns + ) * *$ *--------- * 74LS390 COUNTER DECADE 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-1-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS390 CKA_I CKB_I CLR_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI CLRBAR CKA $D_HI $D_HI QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI CLRBAR CLOCK2 $D_HI $D_HI QB QBBAR + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI CLRBAR QB $D_HI $D_HI QC QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + $D_HI CLRBAR CLOCK4 $D_HI $D_HI QD QDBAR + D0_EFF IO_LS ULS390LOG LOGICEXP (6,6) DPWR DGND + CKA_I CKB_I CLR_I QBBAR QCBAR QDBAR + CKA CKB CLR CLRBAR CLOCK2 CLOCK4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + CKA = { CKA_I } + CKB = { CKB_I } + CLR = { CLR_I } + CLRBAR = { ~CLR } + CLOCK2 = { CKB & QDBAR } + CLOCK4 = { ~((QBBAR & QDBAR) | (QCBAR & QDBAR)) & CKB } * ULS390DLY PINDLY (4,0,3) DPWR DGND + QA QB QC QD + CKA CKB CLR + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKEDA = { CHANGED_HL(CKA,0) } + CLOCKEDB = { CHANGED_HL(CKB,0) } + CLEARED = { CHANGED_LH(CLR,0) } + + PINDLY: + QA_O = { + CASE ( + CLOCKEDA & TRN_LH, DELAY(-1,12NS,20NS), + CLOCKEDA & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,24NS,39NS) + ) + } + QB_O QD_O = { + CASE ( + CLOCKEDB & TRN_LH, DELAY(-1,13NS,21NS), + CLOCKEDB & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,24NS,39NS) + ) + } + QC_O = { + CASE ( + CLEARED, DELAY(-1,24NS,39NS), + TRN_LH, DELAY(-1,24NS,39NS), + DELAY(-1,26NS,39NS) + ) + } + + FREQ: + NODE = CKA + MAXFREQ = 25MEGHZ + FREQ: + NODE = CKB + MAXFREQ = 12.5MEGHZ + WIDTH: + NODE = CKA + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CKB + MIN_LO = 40NS + MIN_HI = 40NS + WIDTH: + NODE = CLR + MIN_HI = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK HL = CKA + RELEASETIME_HL = 25NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK HL = CKB + RELEASETIME_HL = 25NS * .ENDS * *$ *--------- * 74LS393 COUNTER BINARY 4-BIT, ASYNCHRONOUS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 6-30-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * NOTICE: PROPAGATION DELAYS FOR A-TO-QB AND A-TO-QC WERE NOT SPECIFIED * IN THE DATA BOOK, SO THEY WERE INTERPOLATED FROM THE A-TO-QA AND * A-TO-QD PROPAGATION DELAYS * .SUBCKT 74LS393 A_I CLR_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + $D_HI CLRBAR A $D_HI $D_HI QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI CLRBAR QA $D_HI $D_HI QB $D_NC + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI CLRBAR QB $D_HI $D_HI QC $D_NC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + $D_HI CLRBAR QC $D_HI $D_HI QD $D_NC + D0_EFF IO_LS U5 BUFA(2) DPWR DGND + A_I CLR_I + A CLR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U6 INV DPWR DGND + CLR CLRBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * ULS393DLY PINDLY (4,0,2) DPWR DGND + QA QB QC QD + CLR A + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED = { CHANGED_HL(A,0) } + CLEARED = { CHANGED_LH(CLR,0) } + + PINDLY: + QA_O = { + CASE ( + CLOCKED & TRN_LH, DELAY(-1,12NS,20NS), + CLOCKED & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,24NS,39NS) + ) + } + QB_O = { + CASE ( + CLOCKED, DELAY(-1,23NS,35NS), ;GUESSED PROP DELAY--NOT IN DATA BOOK + DELAY(-1,24NS,39NS) + ) + } + QC_O = { + CASE ( + CLEARED, DELAY(-1,24NS,39NS), + DELAY(-1,33NS,50NS) ;GUESSED PROP DELAY--NOT IN DATA BOOK + ) + } + QD_O = { + CASE ( + CLEARED, DELAY(-1,24NS,39NS), + DELAY(-1,40NS,60NS) + ) + } + + FREQ: + NODE = A + MAXFREQ = 25MEGHZ + WIDTH: + NODE = A + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CLR + MIN_HI = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK HL = A + RELEASETIME_HL = 25NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3 STATE OUTPUTS * * THE TTL DATA BOOK, VOL 2, 1988, TI * NH 7/9/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS395A CLK_I LD/SHBAR_I CLRBAR_I SER_I OCBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O QD_P_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * U395ALOG LOGICEXP(16,21) DPWR DGND + CLK_I LD/SHBAR_I CLRBAR_I SER_I OCBAR_I A_I B_I C_I D_I QA0 QB0 QC0 + QABAR QBBAR QCBAR QDBAR + KA KB KC KD JA JB JC JD CLK LD/SHBAR CLRBAR SER OCBAR + A B C D QA QB QC QD + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: * * INTERMEDIATE TERMS: + SHBAR = { ~LD/SHBAR_I } * * OUTPUT ASSIGNMENT + CLK = { CLK_I } + LD/SHBAR = { LD/SHBAR_I } + CLRBAR = { CLRBAR_I } + SER = { SER_I } + OCBAR = { OCBAR_I } + A = { A_I} + B = { B_I } + C = { C_I } + D = { D_I } + + KA = { ~((SER & SHBAR) | (LD/SHBAR & A)) } + KB = { ~((QA0 & SHBAR) | (LD/SHBAR & B)) } + KC = { ~((QB0 & SHBAR) | (LD/SHBAR & C)) } + KD = { ~((QC0 & SHBAR) | (LD/SHBAR & D)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } + QA = { ~QABAR } + QB = { ~QBBAR } + QC = { ~QCBAR } + QD = { ~QDBAR } * U1 JKFF(4) DPWR DGND + $D_HI CLRBAR CLK JA JB JC JD KA KB KC KD + QA0 QB0 QC0 QD0 QABAR QBBAR QCBAR QDBAR + D0_EFF IO_LS * U395ADLY PINDLY (5,1,9) DPWR DGND + QA QB QC QD QD0 + OCBAR + CLRBAR CLK OCBAR LD/SHBAR SER A B C D + QA_O QB_O QC_O QD_O QD_P_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + PINDLY: + QD_P_O = { + CASE( + CHANGED_HL(CLK,0) & TRN_LH, DELAY(-1,15NS,30NS), + CHANGED_HL(CLK,0) & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,22NS,35NS), + DELAY(10NS,23NS,36NS) + ) + } + + TRISTATE: + ENABLE LO OCBAR + QA_O QB_O QC_O QD_O = { + CASE( + TRN_HZ, DELAY(-1,11NS,17NS), + TRN_LZ, DELAY(-1,12NS,20NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_ZL, DELAY(-1,17NS,25NS), + CHANGED_HL(CLK,0) & TRN_LH, DELAY(-1,15NS,30NS), + CHANGED_HL(CLK,0) & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,22NS,35NS), + DELAY(-1,23NS,36NS) + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 30MEG + + WIDTH: + NODE = CLK + MIN_LO = 16NS + MIN_HI = 16NS + + SETUP_HOLD: + DATA(1) LD/SHBAR + CLOCK HL = CLK + SETUPTIME = 40NS + HOLDTIME = 10NS + WHEN = { CLRBAR!='0 } + + SETUP_HOLD: + DATA(1) CLRBAR + CLOCK HL = CLK + RELEASETIME_LH = 20NS + + SETUP_HOLD: ;WHEN NOT CLEAR AND MODE = SHIFT + DATA(1) SER + CLOCK HL = CLK + SETUPTIME = 20NS + HOLDTIME = 10NS + WHEN = { CLRBAR!='0 & (LD/SHBAR!='1 ^ CHANGED(LD/SHBAR,0)) } + + SETUP_HOLD: ;WHEN NOT CLEAR AND MODE = LOAD + DATA(4) A B C D + CLOCK HL = CLK + SETUPTIME = 20NS + HOLDTIME = 10NS + WHEN = { CLRBAR!='0 & (LD/SHBAR!='0 ^ CHANGED(LD/SHBAR,0)) } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS396 Octal Storage Registers * * The TTL Data Book, Vol 2, 1985, TI * atl 8/2/89 Update interface and model names * .subckt 74LS396 GBAR CLK D1 D2 D3 D4 1Q1 2Q1 1Q2 2Q2 1Q3 2Q3 1Q4 2Q4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF buf DPWR DGND + CLK CLKBUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UGBD buf DPWR DGND + GBAR GBARBUF + D_LS396_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X1 GBARBUF CLKBUF D1 1Q1 2Q1 DPWR DGND LS396DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X2 GBARBUF CLKBUF D2 1Q2 2Q2 DPWR DGND LS396DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X3 GBARBUF CLKBUF D3 1Q3 2Q3 DPWR DGND LS396DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} X4 GBARBUF CLKBUF D4 1Q4 2Q4 DPWR DGND LS396DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS396DAT GBAR CLK D 1Q 2Q DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 U1Q dff(1) DPWR DGND + $D_HI $D_HI CLK D D2 1Y + D_LS396_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2Q dff(1) DPWR DGND + $D_HI $D_HI CLK D2 $D_NC 2Y + D_LS396_2 IO_LS MNTYMXDLY={MNTYMXDLY} UQOUT nora(2,2) DPWR DGND + GBAR 1Y GBAR 2Y 1Q 2Q + D_LS396_3 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS396_1 ugate ( + tplhty=14ns tplhmx=24ns + tphlty=14ns tphlmx=24ns + ) .model D_LS396_2 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=20ns thdclkmn=5ns + tpclkqlhty=14ns tpclkqlhmx=24ns + tpclkqhlty=14ns tpclkqhlmx=24ns + ) .model D_LS396_3 ugate ( + tplhty=6ns tphlty=6ns + ) * *$ *--------- * 74LS398 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * THE TTL DATA BOOK, VOL. 2, 1985, TI * TC 08/26/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74LS398 WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + QA_O QB_O QC_O QD_O QABAR_O QBBAR_O QCBAR_O QDBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(4) DPWR DGND $D_HI $D_HI MCLK + JA JB JC JD KA KB KC KD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_LS * ULS398LOG LOGICEXP(10,19) DPWR DGND + WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + WS CLK A1 A2 B1 B2 C1 C2 D1 D2 JA JB JC JD KA KB KC KD MCLK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + WS = { WS_I } + CLK = { CLK_I } + A1 = { A1_I } + A2 = { A2_I } + B1 = { B1_I } + B2 = { B2_I } + C1 = { C1_I } + C2 = { C2_I } + D1 = { D1_I } + D2 = { D2_I } + IWS = { ~WS } + MCLK = { ~CLK } + KA = { ~((A1 & IWS) | (WS & A2)) } + KB = { ~((B1 & IWS) | (WS & B2)) } + KC = { ~((C1 & IWS) | (WS & C2)) } + KD = { ~((D1 & IWS) | (WS & D2)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } * ULS398DLY PINDLY (8,0,10) DPWR DGND + QA QB QC QD QABAR QBBAR QCBAR QDBAR + A1 A2 B1 B2 C1 C2 D1 D2 WS CLK + QA_O QB_O QC_O QD_O QABAR_O QBBAR_O QCBAR_O QDBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O QABAR_O QBBAR_O QCBAR_O QDBAR_O = { + CASE( + TRN_LH, DELAY(-1,18NS,27NS), + DELAY(-1,21NS,32NS) + ) + } + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + SETUP_HOLD: + DATA(4) = A1 B1 C1 D1 + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { WS!='1 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(4) = A2 B2 C2 D2 + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { WS!='0 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(1) = WS + CLOCK LH = CLK + SETUPTIME = 45NS * .ENDS * *$ *--------- * 74LS399 MULTIPLEXERS QUAD 2-INPUT WITH STORAGE * * THE TTL DATA BOOK, VOL. 2, 1985, TI * TC 08/26/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * .SUBCKT 74LS399 WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(4) DPWR DGND $D_HI $D_HI MCLK + JA JB JC JD KA KB KC KD QA QB QC QD $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS399LOG LOGICEXP(10,19) DPWR DGND + WS_I CLK_I A1_I A2_I B1_I B2_I C1_I C2_I D1_I D2_I + WS CLK A1 A2 B1 B2 C1 C2 D1 D2 JA JB JC JD KA KB KC KD MCLK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + WS = { WS_I } + CLK = { CLK_I } + A1 = { A1_I } + A2 = { A2_I } + B1 = { B1_I } + B2 = { B2_I } + C1 = { C1_I } + C2 = { C2_I } + D1 = { D1_I } + D2 = { D2_I } + IWS = { ~WS } + MCLK = { ~CLK } + KA = { ~((A1 & IWS) | (WS & A2)) } + KB = { ~((B1 & IWS) | (WS & B2)) } + KC = { ~((C1 & IWS) | (WS & C2)) } + KD = { ~((D1 & IWS) | (WS & D2)) } + JA = { ~KA } + JB = { ~KB } + JC = { ~KC } + JD = { ~KD } * ULS399DLY PINDLY (4,0,10) DPWR DGND + QA QB QC QD + A1 A2 B1 B2 C1 C2 D1 D2 WS CLK + QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + PINDLY: + QA_O QB_O QC_O QD_O = { + CASE( + TRN_LH, DELAY(-1,18NS,27NS), + DELAY(-1,21NS,32NS) + ) + } + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + SETUP_HOLD: + DATA(4) = A1 B1 C1 D1 + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { WS!='1 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(4) = A2 B2 C2 D2 + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { WS!='0 ^ CHANGED(WS,0) } + SETUP_HOLD: + DATA(1) = WS + CLOCK LH = CLK + SETUPTIME = 45NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS440 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 9/2/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS440 CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1_T A2_T A3_T A4_T + B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS440BUF BUFA(12) DPWR DGND + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS440LOG LOGICEXP(18,21) DPWR DGND + CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + CSBAR GBARA GBARB GBARC S0 S1 A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + CSBAR = { CSBAR_I } + GBARA = { GBARA_I } + GBARB = { GBARB_I } + GBARC = { GBARC_I } + S0 = { S0_I } + S1 = { S1_I } * INTERMEDIATE TERMS + CS = { ~CSBAR } + S0BAR = { ~S0 } + S1BAR = { ~S1 } + /S1/S0 = { S0BAR & S1BAR } + /S1S0 = { S1BAR & S0 } + S1/S0 = { S1 & S0BAR } + ENA = { ((S0 ^ S1) & ~GBARA & CS) } + ENB = { (S0BAR & ~GBARB & CS) } + ENC = { (S1BAR & ~GBARC & CS) } + * OUTPUT ASSIGNMENTS + A1O = { ~((/S1S0 & ~B1 & ENA) | (S1/S0 & ~C1 & ENA )) } + A2O = { ~((/S1S0 & ~B2 & ENA) | (S1/S0 & ~C2 & ENA )) } + A3O = { ~((/S1S0 & ~B3 & ENA) | (S1/S0 & ~C3 & ENA )) } + A4O = { ~((/S1S0 & ~B4 & ENA) | (S1/S0 & ~C4 & ENA )) } + B1O = { ~((/S1/S0 & ~A1 & ENB) | (S1/S0 & ~C1 & ENB )) } + B2O = { ~((/S1/S0 & ~A2 & ENB) | (S1/S0 & ~C2 & ENB )) } + B3O = { ~((/S1/S0 & ~A3 & ENB) | (S1/S0 & ~C3 & ENB )) } + B4O = { ~((/S1/S0 & ~A4 & ENB) | (S1/S0 & ~C4 & ENB )) } + C1O = { ~((/S1/S0 & ~A1 & ENC) | (/S1S0 & ~B1 & ENC )) } + C2O = { ~((/S1/S0 & ~A2 & ENC) | (/S1S0 & ~B2 & ENC )) } + C3O = { ~((/S1/S0 & ~A3 & ENC) | (/S1S0 & ~B3 & ENC )) } + C4O = { ~((/S1/S0 & ~A4 & ENC) | (/S1S0 & ~B4 & ENC )) } * ULS440DLY PINDLY (12,0,9) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + CSBAR GBARA GBARB GBARC S0 S1 ENA ENB ENC + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CH_S = { CHANGED(S0,0) | CHANGED(S1,0) } + + PINDLY: + A1_T A2_T A3_T A4_T = { + CASE( + CH_S & TRN_LH, DELAY(-1,33NS,50NS), + CH_S & TRN_HL, DELAY(-1,32NS,50NS), + CHANGED_LH(CSBAR,0) & TRN_LH, DELAY(-1,31NS,45NS), + CHANGED_HL(CSBAR,0) & TRN_HL, DELAY(-1,28NS,45NS), + CHANGED_LH(GBARA,0) & TRN_LH, DELAY(-1,29NS,45NS), + CHANGED_HL(GBARA,0) & TRN_HL, DELAY(-1,27NS,40NS), + (ENA!='0) & TRN_LH, DELAY(-1,24NS,35NS), + (ENA!='0) & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(0NS,0NS,0NS) + ) + } + B1_T B2_T B3_T B4_T = { + CASE( + CH_S & TRN_LH, DELAY(-1,33NS,50NS), + CH_S & TRN_HL, DELAY(-1,32NS,50NS), + CHANGED_LH(CSBAR,0) & TRN_LH, DELAY(-1,31NS,45NS), + CHANGED_HL(CSBAR,0) & TRN_HL, DELAY(-1,28NS,45NS), + CHANGED_LH(GBARB,0) & TRN_LH, DELAY(-1,29NS,45NS), + CHANGED_HL(GBARB,0) & TRN_HL, DELAY(-1,27NS,40NS), + (ENB!='0) & TRN_LH, DELAY(-1,24NS,35NS), + (ENB!='0) & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(0NS,0NS,0NS) + ) + } + C1_T C2_T C3_T C4_T = { + CASE( + CH_S & TRN_LH, DELAY(-1,33NS,50NS), + CH_S & TRN_HL, DELAY(-1,32NS,50NS), + CHANGED_LH(CSBAR,0) & TRN_LH, DELAY(-1,31NS,45NS), + CHANGED_HL(CSBAR,0) & TRN_HL, DELAY(-1,28NS,45NS), + CHANGED_LH(GBARC,0) & TRN_LH, DELAY(-1,29NS,45NS), + CHANGED_HL(GBARC,0) & TRN_HL, DELAY(-1,27NS,40NS), + (ENC!='0) & TRN_LH, DELAY(-1,24NS,35NS), + (ENC!='0) & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(0NS,0NS,0NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS441 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 9/2/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS441 CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1_T A2_T A3_T A4_T + B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS441BUF BUFA(12) DPWR DGND + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS441LOG LOGICEXP(18,21) DPWR DGND + CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + CSBAR GBARA GBARB GBARC S0 S1 A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + CSBAR = { CSBAR_I } + GBARA = { GBARA_I } + GBARB = { GBARB_I } + GBARC = { GBARC_I } + S0 = { S0_I } + S1 = { S1_I } * INTERMEDIATE TERMS + CS = { ~CSBAR } + S0BAR = { ~S0 } + S1BAR = { ~S1 } + /S1/S0 = { S0BAR & S1BAR } + /S1S0 = { S1BAR & S0 } + S1/S0 = { S1 & S0BAR } + ENA = { ((S0 ^ S1) & ~GBARA & CS) } + ENB = { (S0BAR & ~GBARB & CS) } + ENC = { (S1BAR & ~GBARC & CS) } + * OUTPUT ASSIGNMENTS + A1O = { ~((/S1S0 & B1 & ENA) | (S1/S0 & C1 & ENA )) } + A2O = { ~((/S1S0 & B2 & ENA) | (S1/S0 & C2 & ENA )) } + A3O = { ~((/S1S0 & B3 & ENA) | (S1/S0 & C3 & ENA )) } + A4O = { ~((/S1S0 & B4 & ENA) | (S1/S0 & C4 & ENA )) } + B1O = { ~((/S1/S0 & A1 & ENB) | (S1/S0 & C1 & ENB )) } + B2O = { ~((/S1/S0 & A2 & ENB) | (S1/S0 & C2 & ENB )) } + B3O = { ~((/S1/S0 & A3 & ENB) | (S1/S0 & C3 & ENB )) } + B4O = { ~((/S1/S0 & A4 & ENB) | (S1/S0 & C4 & ENB )) } + C1O = { ~((/S1/S0 & A1 & ENC) | (/S1S0 & B1 & ENC )) } + C2O = { ~((/S1/S0 & A2 & ENC) | (/S1S0 & B2 & ENC )) } + C3O = { ~((/S1/S0 & A3 & ENC) | (/S1S0 & B3 & ENC )) } + C4O = { ~((/S1/S0 & A4 & ENC) | (/S1S0 & B4 & ENC )) } * ULS441DLY PINDLY (12,0,9) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + CSBAR GBARA GBARB GBARC S0 S1 ENA ENB ENC + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CH_S = { CHANGED(S1,0) | CHANGED(S0,0) } + A_INPUT = { S1!='0 | S0!='0 } + B_INPUT = { S1!='0 | S0!='1 } + C_INPUT = { S1!='1 | S0!='0 } + EN_A = { ENA!='0 } + EN_B = { ENB!='0 } + EN_C = { ENC!='0 } + + PINDLY: + A1_T A2_T A3_T A4_T = { + CASE( + A_INPUT & CH_S & TRN_LH, DELAY(-1,27NS,40NS), + A_INPUT & CH_S & TRN_HL, DELAY(-1,26NS,40NS), + CHANGED_LH(CSBAR,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED_HL(CSBAR,0) & TRN_HL, DELAY(-1,21NS,30NS), + A_INPUT & CHANGED(GBARA,0) & TRN_LH, DELAY(-1,23NS,35NS), + A_INPUT & CHANGED(GBARA,0) & TRN_HL, DELAY(-1,20NS,30NS), + EN_A & TRN_LH, DELAY(-1,21NS,30NS), + EN_A & TRN_HL, DELAY(-1,9NS,15NS), + DELAY(0NS,0NS,0NS) + ) + } + B1_T B2_T B3_T B4_T = { + CASE( + B_INPUT & CH_S & TRN_LH, DELAY(-1,27NS,40NS), + B_INPUT & CH_S & TRN_HL, DELAY(-1,26NS,40NS), + CHANGED_LH(CSBAR,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED_HL(CSBAR,0) & TRN_HL, DELAY(-1,21NS,30NS), + B_INPUT & CHANGED(GBARB,0) & TRN_LH, DELAY(-1,23NS,35NS), + B_INPUT & CHANGED(GBARB,0) & TRN_HL, DELAY(-1,20NS,30NS), + EN_B & TRN_LH, DELAY(-1,21NS,30NS), + EN_B & TRN_HL, DELAY(-1,9NS,15NS), + DELAY(0NS,0NS,0NS) + ) + } + C1_T C2_T C3_T C4_T = { + CASE( + C_INPUT & CH_S & TRN_LH, DELAY(-1,27NS,40NS), + C_INPUT & CH_S & TRN_HL, DELAY(-1,26NS,40NS), + CHANGED(CSBAR,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(CSBAR,0) & TRN_HL, DELAY(-1,21NS,30NS), + C_INPUT & CHANGED(GBARC,0) & TRN_LH, DELAY(-1,23NS,35NS), + C_INPUT & CHANGED(GBARC,0) & TRN_HL, DELAY(-1,20NS,30NS), + EN_C & TRN_LH, DELAY(-1,21NS,30NS), + EN_C & TRN_HL, DELAY(-1,9NS,15NS), + DELAY(0NS,0NS,0NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS442 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS WITH TRI-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 9/3/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS442 CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1_T A2_T A3_T A4_T + B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS442BUF BUFA(12) DPWR DGND + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS442LOG LOGICEXP(18,21) DPWR DGND + CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + CSBAR GBARA GBARB GBARC S0 S1 A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + CSBAR = { CSBAR_I } + GBARA = { GBARA_I } + GBARB = { GBARB_I } + GBARC = { GBARC_I } + S0 = { S0_I } + S1 = { S1_I } * INTERMEDIATE TERMS + CS = { ~CSBAR } + S0BAR = { ~S0 } + S1BAR = { ~S1 } + /S1/S0 = { S0BAR & S1BAR } + /S1S0 = { S1BAR & S0 } + S1/S0 = { S1 & S0BAR } + ENA = { ((S0 ^ S1) & ~GBARA & CS) } + ENB = { (S0BAR & ~GBARB & CS) } + ENC = { (S1BAR & ~GBARC & CS) } + * OUTPUT ASSIGNMENTS + A1O = { ~( (/S1S0 & ~B1) | (S1/S0 & ~C1) ) } + A2O = { ~( (/S1S0 & ~B2) | (S1/S0 & ~C2) ) } + A3O = { ~( (/S1S0 & ~B3) | (S1/S0 & ~C3) ) } + A4O = { ~( (/S1S0 & ~B4) | (S1/S0 & ~C4) ) } + B1O = { ~( (/S1/S0 & ~A1) | (S1/S0 & ~C1) ) } + B2O = { ~( (/S1/S0 & ~A2) | (S1/S0 & ~C2) ) } + B3O = { ~( (/S1/S0 & ~A3) | (S1/S0 & ~C3) ) } + B4O = { ~( (/S1/S0 & ~A4) | (S1/S0 & ~C4) ) } + C1O = { ~( (/S1/S0 & ~A1) | (/S1S0 & ~B1) ) } + C2O = { ~( (/S1/S0 & ~A2) | (/S1S0 & ~B2) ) } + C3O = { ~( (/S1/S0 & ~A3) | (/S1S0 & ~B3) ) } + C4O = { ~( (/S1/S0 & ~A4) | (/S1S0 & ~B4) ) } * ULS442DLY PINDLY (12,3,6) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + CSBAR GBARA GBARB GBARC S0 S1 + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CS_EN = { CHANGED_HL(CSBAR,0) } + CH_S = { CHANGED(S1,0) | CHANGED(S0,0) } + + TRISTATE: + ENABLE HI ENA + A1_T A2_T A3_T A4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,23NS,36NS), + CHANGED_HL(GBARA,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,21NS,32NS), + TRN_LZ, DELAY(-1,14NS,35NS), + TRN_HZ, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,14NS), + TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,21NS,32NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_T B2_T B3_T B4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,23NS,36NS), + CHANGED_HL(GBARB,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,21NS,32NS), + TRN_LZ, DELAY(-1,14NS,35NS), + TRN_HZ, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,14NS), + TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,21NS,32NS) + ) + } + TRISTATE: + ENABLE HI ENC + C1_T C2_T C3_T C4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,23NS,36NS), + CHANGED_HL(GBARC,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,21NS,32NS), + TRN_LZ, DELAY(-1,14NS,35NS), + TRN_HZ, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,10NS,14NS), + TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,21NS,32NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS443 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS WITH TRI-STATE OUTPUTS * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL, 1985, TI * NH 9/4/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS443 CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1_T A2_T A3_T A4_T + B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS443BUF BUFA(12) DPWR DGND + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS443LOG LOGICEXP(18,21) DPWR DGND + CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + CSBAR GBARA GBARB GBARC S0 S1 A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + CSBAR = { CSBAR_I } + GBARA = { GBARA_I } + GBARB = { GBARB_I } + GBARC = { GBARC_I } + S0 = { S0_I } + S1 = { S1_I } * INTERMEDIATE TERMS + CS = { ~CSBAR } + S0BAR = { ~S0 } + S1BAR = { ~S1 } + /S1/S0 = { S0BAR & S1BAR } + /S1S0 = { S1BAR & S0 } + S1/S0 = { S1 & S0BAR } + ENA = { ((S0 ^ S1) & ~GBARA & CS) } + ENB = { (S0BAR & ~GBARB & CS) } + ENC = { (S1BAR & ~GBARC & CS) } + * OUTPUT ASSIGNMENTS + A1O = { ~( (/S1S0 & B1) | (S1/S0 & C1) ) } + A2O = { ~( (/S1S0 & B2) | (S1/S0 & C2) ) } + A3O = { ~( (/S1S0 & B3) | (S1/S0 & C3) ) } + A4O = { ~( (/S1S0 & B4) | (S1/S0 & C4) ) } + B1O = { ~( (/S1/S0 & A1) | (S1/S0 & C1) ) } + B2O = { ~( (/S1/S0 & A2) | (S1/S0 & C2) ) } + B3O = { ~( (/S1/S0 & A3) | (S1/S0 & C3) ) } + B4O = { ~( (/S1/S0 & A4) | (S1/S0 & C4) ) } + C1O = { ~( (/S1/S0 & A1) | (/S1S0 & B1) ) } + C2O = { ~( (/S1/S0 & A2) | (/S1S0 & B2) ) } + C3O = { ~( (/S1/S0 & A3) | (/S1S0 & B3) ) } + C4O = { ~( (/S1/S0 & A4) | (/S1S0 & B4) ) } * ULS443DLY PINDLY (12,3,6) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + CSBAR GBARA GBARB GBARC S0 S1 + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CS_EN = { CHANGED_HL(CSBAR,0) } + CH_S = { CHANGED(S1,0) | CHANGED(S0,0) } + + TRISTATE: + ENABLE HI ENA + A1_T A2_T A3_T A4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,24NS,36NS), + CHANGED_HL(GBARA,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,20NS,32NS), + TRN_$Z, DELAY(-1,15NS,25NS), + TRN_LH, DELAY(-1,9NS,14NS), + TRN_HL, DELAY(-1,7NS,13NS), + DELAY(-1,28NS,42NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_T B2_T B3_T B4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,24NS,36NS), + CHANGED_HL(GBARB,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,20NS,32NS), + TRN_$Z, DELAY(-1,15NS,25NS), + TRN_LH, DELAY(-1,9NS,14NS), + TRN_HL, DELAY(-1,7NS,13NS), + DELAY(-1,28NS,42NS) + ) + } + TRISTATE: + ENABLE HI ENC + C1_T C2_T C3_T C4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,24NS,36NS), + CHANGED_HL(GBARC,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,20NS,32NS), + TRN_$Z, DELAY(-1,15NS,25NS), + TRN_LH, DELAY(-1,9NS,14NS), + TRN_HL, DELAY(-1,7NS,13NS), + DELAY(-1,28NS,42NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS444 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS WITH TRI-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 9/4/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS444 CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1_T A2_T A3_T A4_T + B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS444BUF BUFA(12) DPWR DGND + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS444LOG LOGICEXP(18,21) DPWR DGND + CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + CSBAR GBARA GBARB GBARC S0 S1 A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + CSBAR = { CSBAR_I } + GBARA = { GBARA_I } + GBARB = { GBARB_I } + GBARC = { GBARC_I } + S0 = { S0_I } + S1 = { S1_I } * INTERMEDIATE TERMS + CS = { ~CSBAR } + S0BAR = { ~S0 } + S1BAR = { ~S1 } + /S1/S0 = { S0BAR & S1BAR } + /S1S0 = { S1BAR & S0 } + S1/S0 = { S1 & S0BAR } + ENA = { ((S0 ^ S1) & ~GBARA & CS) } + ENB = { (S0BAR & ~GBARB & CS) } + ENC = { (S1BAR & ~GBARC & CS) } + * OUTPUT ASSIGNMENTS + A1O = { ~( (/S1S0 & B1) | (S1/S0 & C1) ) } + A2O = { ~( (/S1S0 & B2) | (S1/S0 & C2) ) } + A3O = { ~( (/S1S0 & B3) | (S1/S0 & C3) ) } + A4O = { ~( (/S1S0 & B4) | (S1/S0 & C4) ) } + B1O = { ~( (/S1/S0 & A1) | (S1/S0 & ~C1) ) } + B2O = { ~( (/S1/S0 & A2) | (S1/S0 & ~C2) ) } + B3O = { ~( (/S1/S0 & A3) | (S1/S0 & ~C3) ) } + B4O = { ~( (/S1/S0 & A4) | (S1/S0 & ~C4) ) } + C1O = { ~( (/S1/S0 & A1) | (/S1S0 & ~B1) ) } + C2O = { ~( (/S1/S0 & A2) | (/S1S0 & ~B2) ) } + C3O = { ~( (/S1/S0 & A3) | (/S1S0 & ~B3) ) } + C4O = { ~( (/S1/S0 & A4) | (/S1S0 & ~B4) ) } * ULS444DLY PINDLY (12,3,18) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + CSBAR GBARA GBARB GBARC S0 S1 A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CS_EN = { CHANGED_HL(CSBAR,0) } + CH_S = { CHANGED(S1,0) | CHANGED(S0,0) } + CH_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) } + CH_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) } + CH_C = { CHANGED(C1,0) | CHANGED(C2,0) | CHANGED(C3,0) | CHANGED(C4,0) } + + TRISTATE: + ENABLE HI ENA + A1_T A2_T A3_T A4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,23NS,36NS), + CHANGED_HL(GBARA,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,24NS,32NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,14NS,25NS), + TRN_LH, DELAY(-1,9NS,14NS), + TRN_HL, DELAY(-1,7NS,13NS), + DELAY(-1,28NS,42NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_T B2_T B3_T B4_T = { + CASE( + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CS_EN & TRN_ZL, DELAY(-1,23NS,36NS), + CHANGED_HL(GBARB,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,24NS,32NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,14NS,25NS), + CH_C & TRN_LH, DELAY(-1,10NS,14NS), + CH_C & TRN_HL, DELAY(-1,13NS,20NS), + CH_A & TRN_LH, DELAY(-1,9NS,14NS), + CH_A & TRN_HL, DELAY(-1,7NS,13NS), + DELAY(-1,28NS,42NS) + ) + } + TRISTATE: + ENABLE HI ENC + C1_T C2_T C3_T C4_T = { + CASE( + CS_EN & TRN_ZL, DELAY(-1,23NS,36NS), + CH_S & TRN_ZL, DELAY(-1,28NS,42NS), + CHANGED_HL(GBARC,0) & TRN_ZL, DELAY(-1,22NS,33NS), + TRN_ZH, DELAY(-1,24NS,32NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,14NS,25NS), + CH_B & TRN_LH, DELAY(-1,10NS,14NS), + CH_B & TRN_HL, DELAY(-1,13NS,20NS), + CH_A & TRN_LH, DELAY(-1,9NS,14NS), + CH_A & TRN_HL, DELAY(-1,7NS,13NS), + DELAY(-1,28NS,42NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS445 DECODER/DRIVER BCD-DECIMAL WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-25-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS445 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * X1 A_I B_I C_I D_I + Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O DPWR DGND 74LS145 + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .ENDS * *$ *------------------------------------------------------------------------- * 74LS446 QUADRUPLE BUS TRANSCEIVERS WITH INDIVIDUAL DIRECTION CONTROLS, * 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT * .SUBCKT 74LS446 GABBAR_I GBABAR_I DIR1_I DIR2_I DIR3_I DIR4_I + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(8) DPWR DGND + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + A1 A2 A3 A4 B1 B2 B3 B4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS446LOG LOGICEXP(14,16) DPWR DGND + A1 A2 A3 A4 B1 B2 B3 B4 GABBAR_I GBABAR_I DIR1_I DIR2_I DIR3_I DIR4_I + ATOB_1 ATOB_2 ATOB_3 ATOB_4 BTOA_1 BTOA_2 BTOA_3 BTOA_4 + A1O A2O A3O A4O B1O B2O B3O B4O + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFERS: + GABBAR = { GABBAR_I } + GBABAR = { GBABAR_I } + GAB = { ~GABBAR } + GBA = { ~GBABAR } * * OUTPUT ASSIGNMENT: + ATOB_1 = { DIR1_I & GAB } + BTOA_1 = { ~DIR1_I & GBA } + ATOB_2 = { DIR2_I & GAB } + BTOA_2 = { ~DIR2_I & GBA } + ATOB_3 = { DIR3_I & GAB } + BTOA_3 = { ~DIR3_I & GBA } + ATOB_4 = { DIR4_I & GAB } + BTOA_4 = { ~DIR4_I & GBA } * + A1O = { ~B1 } + A2O = { ~B2 } + A3O = { ~B3 } + A4O = { ~B4 } + B1O = { ~A1 } + B2O = { ~A2 } + B3O = { ~A3 } + B4O = { ~A4 } * ULS446DLY PINDLY (8,8,0) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O + ATOB_1 ATOB_2 ATOB_3 ATOB_4 BTOA_1 BTOA_2 BTOA_3 BTOA_4 + + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + TRISTATE: + ENABLE HI ATOB_1 + B1_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI ATOB_2 + B2_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI ATOB_3 + B3_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI ATOB_4 + B4_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI BTOA_1 + A1_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI BTOA_2 + A2_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI BTOA_3 + A3_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } + TRISTATE: + ENABLE HI BTOA_4 + A4_B = { + CASE( + TRN_ZL, DELAY(-1,24NS,40NS), + TRN_ZH, DELAY(-1,15NS,25NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1, 8NS,13NS), + TRN_HL, DELAY(-1, 7NS,12NS), + DELAY(-1,24NS,40NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS447 DECODER/DRIVER BCD-7 SEGMENT WITH OPEN COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 8-26-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS447 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * X1 INA_I INB_I INC_I IND_I RBIBAR_I LTBAR_I BIBAR/RBOBAR_B + OUTA_O OUTB_O OUTC_O OUTD_O OUTE_O OUTF_O OUTG_O DPWR DGND 74LS247 + PARAMS: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .ENDS * *$ *------------------------------------------------------------------------- * 74LS448 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL, 1985, TI * NH 9/4/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS448 CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1_T A2_T A3_T A4_T + B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS448BUF BUFA(12) DPWR DGND + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS448LOG LOGICEXP(18,21) DPWR DGND + CSBAR_I GBARA_I GBARB_I GBARC_I S0_I S1_I A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + CSBAR GBARA GBARB GBARC S0 S1 A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + ENA ENB ENC + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS + CSBAR = { CSBAR_I } + GBARA = { GBARA_I } + GBARB = { GBARB_I } + GBARC = { GBARC_I } + S0 = { S0_I } + S1 = { S1_I } * INTERMEDIATE TERMS + CS = { ~CSBAR } + S0BAR = { ~S0 } + S1BAR = { ~S1 } + /S1/S0 = { S0BAR & S1BAR } + /S1S0 = { S1BAR & S0 } + S1/S0 = { S1 & S0BAR } + ENA = { ((S0 ^ S1) & ~GBARA & CS) } + ENB = { (S0BAR & ~GBARB & CS) } + ENC = { (S1BAR & ~GBARC & CS) } + * OUTPUT ASSIGNMENTS + A1O = { ~((/S1S0 & B1 & ENA) | (S1/S0 & C1 & ENA )) } + A2O = { ~((/S1S0 & B2 & ENA) | (S1/S0 & C2 & ENA )) } + A3O = { ~((/S1S0 & B3 & ENA) | (S1/S0 & C3 & ENA )) } + A4O = { ~((/S1S0 & B4 & ENA) | (S1/S0 & C4 & ENA )) } + B1O = { ~((/S1/S0 & A1 & ENB) | (S1/S0 & ~C1 & ENB )) } + B2O = { ~((/S1/S0 & A2 & ENB) | (S1/S0 & ~C2 & ENB )) } + B3O = { ~((/S1/S0 & A3 & ENB) | (S1/S0 & ~C3 & ENB )) } + B4O = { ~((/S1/S0 & A4 & ENB) | (S1/S0 & ~C4 & ENB )) } + C1O = { ~((/S1/S0 & A1 & ENC) | (/S1S0 & ~B1 & ENC )) } + C2O = { ~((/S1/S0 & A2 & ENC) | (/S1S0 & ~B2 & ENC )) } + C3O = { ~((/S1/S0 & A3 & ENC) | (/S1S0 & ~B3 & ENC )) } + C4O = { ~((/S1/S0 & A4 & ENC) | (/S1S0 & ~B4 & ENC )) } * ULS448DLY PINDLY (12,0,18) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O C1O C2O C3O C4O + CSBAR GBARA GBARB GBARC S0 S1 A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 + A1_T A2_T A3_T A4_T B1_T B2_T B3_T B4_T C1_T C2_T C3_T C4_T + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CH_S = { CHANGED(S1,0) | CHANGED(S0,0) } + CH_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) } + CH_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) } + CH_C = { CHANGED(C1,0) | CHANGED(C2,0) | CHANGED(C3,0) | CHANGED(C4,0) } + + PINDLY: + A1_T A2_T A3_T A4_T = { + CASE( + CH_S & TRN_LH, DELAY(-1,26NS,40NS), + CH_S & TRN_HL, DELAY(-1,27NS,40NS), + CHANGED(CSBAR,0) & TRN_LH, DELAY(-1,25NS,40NS), + CHANGED(CSBAR,0) & TRN_HL, DELAY(-1,22NS,35NS), + CHANGED_LH(GBARA,0) & TRN_LH, DELAY(-1,25NS,40NS), + CHANGED_HL(GBARA,0) & TRN_HL, DELAY(-1,22NS,35NS), + (CH_B | CH_C) & TRN_LH, DELAY(-1,21NS,30NS), + (CH_B | CH_C) & TRN_HL, DELAY(-1,9NS,15NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } + B1_T B2_T B3_T B4_T = { + CASE( + CH_S & TRN_LH, DELAY(-1,26NS,40NS), + CH_S & TRN_HL, DELAY(-1,27NS,40NS), + CHANGED(CSBAR,0) & TRN_LH, DELAY(-1,25NS,40NS), + CHANGED(CSBAR,0) & TRN_HL, DELAY(-1,22NS,35NS), + CHANGED_LH(GBARB,0) & TRN_LH, DELAY(-1,25NS,40NS), + CHANGED_HL(GBARB,0) & TRN_HL, DELAY(-1,22NS,35NS), + CH_A & TRN_LH, DELAY(-1,21NS,30NS), + CH_A & TRN_HL, DELAY(-1,9NS,15NS), + CH_C & TRN_LH, DELAY(-1,24NS,35NS), + CH_C & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } + C1_T C2_T C3_T C4_T = { + CASE( + CH_S & TRN_LH, DELAY(-1,26NS,40NS), + CH_S & TRN_HL, DELAY(-1,27NS,40NS), + CHANGED(CSBAR,0) & TRN_LH, DELAY(-1,25NS,40NS), + CHANGED(CSBAR,0) & TRN_HL, DELAY(-1,22NS,35NS), + CHANGED_LH(GBARC,0) & TRN_LH, DELAY(-1,25NS,40NS), + CHANGED_HL(GBARC,0) & TRN_HL, DELAY(-1,22NS,35NS), + CH_A & TRN_LH, DELAY(-1,21NS,30NS), + CH_A & TRN_HL, DELAY(-1,9NS,15NS), + CH_B & TRN_LH, DELAY(-1,24NS,35NS), + CH_B & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(0NS,0NS,0NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS449 QUADRUPLE BUS TRANSCEIVERS WITH INDIVIDUAL DIRECTION CONTROLS, * 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 9/1/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT * .SUBCKT 74LS449 GABBAR_I GBABAR_I DIR1_I DIR2_I DIR3_I DIR4_I + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(8) DPWR DGND + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + A1 A2 A3 A4 B1 B2 B3 B4 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS449LOG LOGICEXP(14,16) DPWR DGND + A1 A2 A3 A4 B1 B2 B3 B4 GABBAR_I GBABAR_I DIR1_I DIR2_I DIR3_I DIR4_I + ATOB_1 ATOB_2 ATOB_3 ATOB_4 BTOA_1 BTOA_2 BTOA_3 BTOA_4 + A1O A2O A3O A4O B1O B2O B3O B4O + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFERS: + GABBAR = { GABBAR_I } + GBABAR = { GBABAR_I } + GAB = { ~GABBAR } + GBA = { ~GBABAR } * * OUTPUT ASSIGNMENT: + ATOB_1 = { DIR1_I & GAB } + BTOA_1 = { ~DIR1_I & GBA } + ATOB_2 = { DIR2_I & GAB } + BTOA_2 = { ~DIR2_I & GBA } + ATOB_3 = { DIR3_I & GAB } + BTOA_3 = { ~DIR3_I & GBA } + ATOB_4 = { DIR4_I & GAB } + BTOA_4 = { ~DIR4_I & GBA } * + A1O = { B1 } + A2O = { B2 } + A3O = { B3 } + A4O = { B4 } + B1O = { A1 } + B2O = { A2 } + B3O = { A3 } + B4O = { A4 } * ULS449DLY PINDLY (8,8,0) DPWR DGND + A1O A2O A3O A4O B1O B2O B3O B4O + ATOB_1 ATOB_2 ATOB_3 ATOB_4 BTOA_1 BTOA_2 BTOA_3 BTOA_4 + + A1_B A2_B A3_B A4_B B1_B B2_B B3_B B4_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + TRISTATE: + ENABLE HI ATOB_1 + B1_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI ATOB_2 + B2_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI ATOB_3 + B3_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI ATOB_4 + B4_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI BTOA_1 + A1_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI BTOA_2 + A2_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI BTOA_3 + A3_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } + TRISTATE: + ENABLE HI BTOA_4 + A4_B = { + CASE( + TRN_ZL, DELAY(-1,21NS,35NS), + TRN_ZH, DELAY(-1,18NS,30NS), + TRN_LZ, DELAY(-1,14NS,25NS), + TRN_HZ, DELAY(-1,10NS,15NS), + TRN_LH, DELAY(-1,10NS,15NS), + TRN_HL, DELAY(-1,11NS,17NS), + DELAY(-1,21NS,35NS) + ) + } * .ENDS * *$ *--------- * 74LS465 Octal Buffers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS465 A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UB buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_LS465 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS465 utgate ( + tplhty=9ns tplhmx=15ns + tphlty=12ns tphlmx=18ns + tpzhty=25ns tpzhmx=40ns + tpzlty=29ns tpzlmx=45ns + tphzty=25ns tphzmx=40ns + tplzty=30ns tplzmx=45ns + ) *$ *--------- * 74LS466 Octal Buffers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS466 A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UB inv3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_LS466 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS466 utgate ( + tplhty=7ns tplhmx=12ns + tphlty=9ns tphlmx=15ns + tpzhty=25ns tpzhmx=40ns + tpzlty=29ns tpzlmx=45ns + tphzty=25ns tphzmx=40ns + tplzty=30ns tplzmx=45ns + ) *$ *--------- * 74LS467 Octal Buffers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 06/27/89 Update interface and model names * .subckt 74LS467 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2 1Y1 1Y2 1Y3 1Y4 2Y1 + 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA inv DPWR DGND + G1BAR G1 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UB buf3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS467 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UC buf3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_LS467 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS467 utgate ( + tplhty=9ns tplhmx=15ns + tphlty=12ns tphlmx=18ns + tpzhty=25ns tpzhmx=40ns + tpzlty=29ns tpzlmx=45ns + tphzty=25ns tphzmx=40ns + tplzty=30ns tplzmx=45ns + ) *$ *--------- * 74LS468 Octal Buffers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/18/89 Update interface and model names * .subckt 74LS468 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G1BAR G2BAR 1Y1 1Y2 1Y3 1Y4 + 2Y1 2Y2 2Y3 2Y4 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UINV inva(2) DPWR DGND + G1BAR G2BAR G1 G2 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv3a(4) DPWR DGND + 1A1 1A2 1A3 1A4 G1 1Y1 1Y2 1Y3 1Y4 + D_LS468 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 inv3a(4) DPWR DGND + 2A1 2A2 2A3 2A4 G2 2Y1 2Y2 2Y3 2Y4 + D_LS468 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS468 utgate ( + tplhty=7ns tplhmx=12ns + tphlty=9ns tphlmx=15ns + tpzhty=25ns tpzhmx=40ns + tpzlty=29ns tpzlmx=45ns + tphzty=25ns tphzmx=40ns + tplzty=30ns tplzmx=45ns + ) * *$ *--------- * 74LS490 COUNTER DECADE 4-BIT, ASYNCHRONOUS * * THE TTL DATA BOOK, VOLUME 2, STANDARD, S, LS, TTL; 1985, TI * JLS 7-2-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS490 CLR_I SET9_I CLK_I QA_O QB_O QC_O QD_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND + SET9BAR CLRBAR CLK $D_HI $D_HI QA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND + $D_HI CLRBAR23 CLOCK2 $D_HI $D_HI QB QBBAR + D0_EFF IO_LS U3 JKFF(1) DPWR DGND + $D_HI CLRBAR23 QB $D_HI $D_HI QC QCBAR + D0_EFF IO_LS U4 JKFF(1) DPWR DGND + SET9BAR CLRBAR CLOCK4 $D_HI $D_HI QD QDBAR + D0_EFF IO_LS * ULS490LOG LOGICEXP (7,8) DPWR DGND + CLR_I SET9_I CLK_I QA QBBAR QCBAR QDBAR + CLR SET9 CLK CLRBAR23 CLOCK2 CLOCK4 CLRBAR SET9BAR + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + CLR = { CLR_I } + CLRBAR = { ~CLR } + SET9 = { SET9_I } + SET9BAR = { ~SET9 } + CLK = { CLK_I } + CLRBAR23 = { CLRBAR & SET9BAR } + CLOCK2 = { QA & QDBAR } + CLOCK4 = { ~( (QBBAR & QDBAR) | (QCBAR & QDBAR) ) & QA } * ULS490DLY PINDLY (4,0,3) DPWR DGND + QA QB QC QD + CLR SET9 CLK + QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + CLOCKED = { CHANGED_HL(CLK,0) } + CLEARED = { CHANGED_LH(CLR,0) } + SETNINE = { CHANGED_LH(SET9,0) } + + PINDLY: + QA_O = { + CASE ( + CLOCKED & TRN_LH, DELAY(-1,12NS,20NS), + CLOCKED & TRN_HL, DELAY(-1,13NS,20NS), + DELAY(-1,24NS,39NS) + ) + } + QB_O = { + CASE ( + SETNINE, DELAY(-1,20NS,36NS), + CLEARED, DELAY(-1,24NS,39NS), + TRN_LH, DELAY(-1,24NS,39NS), + DELAY(-1,26NS,39NS) + ) + } + QC_O = { + CASE ( + SETNINE, DELAY(-1,20NS,36NS), + CLEARED, DELAY(-1,24NS,39NS), + TRN_LH, DELAY(-1,32NS,54NS), + DELAY(-1,36NS,54NS) + ) + } + QD_O = { + CASE ( + TRN_LH, DELAY(-1,24NS,39NS), + CLEARED, DELAY(-1,24NS,39NS), + DELAY(-1,26NS,39NS) + ) + } + + FREQ: + NODE = CLK + MAXFREQ = 25MEGHZ + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CLR + MIN_HI = 20NS + WHEN = { SET9!='1 } + WIDTH: + NODE = SET9 + MIN_HI = 20NS + SETUP_HOLD: + DATA(1) = CLR + CLOCK HL = CLK + RELEASETIME_HL = 25NS + WHEN = { SET9!='1 } + SETUP_HOLD: + DATA(1) = SET9 + CLOCK HL = CLK + RELEASETIME_HL = 25NS * .ENDS * *$ *--------- * 74LS540 Octal Buffers and Line Drivers with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/19/89 Update interface and model names * .subckt 74LS540 A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 inv3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_LS540 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS540 utgate ( + tplhty=9ns tplhmx=15ns + tphlty=9ns tphlmx=15ns + tpzhty=15ns tpzhmx=25ns + tpzlty=25ns tpzlmx=38ns + tphzty=15ns tphzmx=25ns + tplzty=10ns tplzmx=18ns + ) *$ *--------- * 74LS541 Octal Buffers and Line Driver with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 7/19/89 Update interface and model names * .subckt 74LS541 A1 A2 A3 A4 A5 A6 A7 A8 G1BAR G2BAR Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UA nor(2) DPWR DGND + G1BAR G2BAR E + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U1 buf3a(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + E + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + D_LS541 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .model D_LS541 utgate ( + tplhty=9ns tplhmx=15ns + tphlty=10ns tphlmx=18ns + tpzhty=20ns tpzhmx=32ns + tpzlty=25ns tpzlmx=38ns + tphzty=18ns tphzmx=29ns + tplzty=10ns tplzmx=18ns + ) * *$ *------------------------------------------------------------------------- * 74LS589 8-BIT SHIFT REGISTERS WITH INPUT LATCHES AND 3-STATE OUTPUT * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-10-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS589 OCBAR_I SRCK_I SRLOADBAR_I RCK_I SER_I + A_I B_I C_I D_I E_I F_I G_I H_I QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * USTIM1 STIM(1,1) $G_DPWR $G_DGND PWR_CLRBAR + IO_STM + 0NS 0 + 1NS 1 * U589LOG LOGICEXP(30,29) DPWR DGND + OCBAR_I PWR_CLRBAR SRCK_I SRLOADBAR_I RCK_I SER_I A_I B_I C_I D_I E_I F_I G_I + H_I QA QB QC QD QE QF QG QH QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR QHBAR + OCBAR SRCK SRLOADBAR RCK SER A B C D E F G H SA SB SC SD SE SF SG SH + RA RB RC RD RE RF RG RH + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + OCBAR = { OCBAR_I } + SRCK = { SRCK_I } + SRLOADBAR = { SRLOADBAR_I } + RCK = { RCK_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + * INTERMEDIATE TERMS: + SRLOAD = { ~SRLOADBAR } + PWR_CLR = { ~PWR_CLRBAR } + + SA = { ~(SRLOAD & QA) } + SB = { ~(SRLOAD & QB) } + SC = { ~(SRLOAD & QC) } + SD = { ~(SRLOAD & QD) } + SE = { ~(SRLOAD & QE) } + SF = { ~(SRLOAD & QF) } + SG = { ~(SRLOAD & QG) } + SH = { ~(SRLOAD & QH) } + RA = { ~(PWR_CLR | (SRLOAD & QABAR)) } + RB = { ~(PWR_CLR | (SRLOAD & QBBAR)) } + RC = { ~(PWR_CLR | (SRLOAD & QCBAR)) } + RD = { ~(PWR_CLR | (SRLOAD & QDBAR)) } + RE = { ~(PWR_CLR | (SRLOAD & QEBAR)) } + RF = { ~(PWR_CLR | (SRLOAD & QFBAR)) } + RG = { ~(PWR_CLR | (SRLOAD & QGBAR)) } + RH = { ~(PWR_CLR | (SRLOAD & QHBAR)) } * U1 DFF(8) DPWR DGND $D_HI $D_HI RCK + A B C D E F G H + QA QB QC QD QE QF QG QH + QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR QHBAR + D0_EFF IO_LS * U2 DFF(1) DPWR DGND + SA RA SRCK SER Q2A $D_NC + D0_EFF IO_LS * U3 DFF(1) DPWR DGND + SB RB SRCK Q2A Q2B $D_NC + D0_EFF IO_LS * U4 DFF(1) DPWR DGND + SC RC SRCK Q2B Q2C $D_NC + D0_EFF IO_LS * U5 DFF(1) DPWR DGND + SD RD SRCK Q2C Q2D $D_NC + D0_EFF IO_LS * U6 DFF(1) DPWR DGND + SE RE SRCK Q2D Q2E $D_NC + D0_EFF IO_LS * U7 DFF(1) DPWR DGND + SF RF SRCK Q2E Q2F $D_NC + D0_EFF IO_LS * U8 DFF(1) DPWR DGND + SG RG SRCK Q2F Q2G $D_NC + D0_EFF IO_LS * U9 DFF(1) DPWR DGND + SH RH SRCK Q2G QHP $D_NC + D0_EFF IO_LS * U589DLY PINDLY (1,1,22) DPWR DGND + QHP + OCBAR + OCBAR SRCK SRLOADBAR RCK RCK SER A B C D E F G H QA QB QC QD QE QF QG QH + QHP_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + LOAD = { SRLOADBAR!='1 } + NOT_LOAD = { SRLOADBAR!='0 } + + TRISTATE: + ENABLE LO OCBAR + QHP_O = { + CASE( + TRN_ZH, DELAY(-1,10NS,15NS), + TRN_ZL, DELAY(-1,18NS,27NS), + TRN_HZ, DELAY(-1,20NS,30NS), + TRN_LZ, DELAY(-1,20NS,30NS), + + CHANGED_LH(SRCK,0) & NOT_LOAD & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED_LH(SRCK,0) & NOT_LOAD & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_HL(SRLOADBAR,0) & TRN_HL, DELAY(-1,29NS,44NS), + CHANGED_LH(RCK,0) & LOAD & TRN_HL, DELAY(-1,32NS,48NS), + CHANGED_HL(SRLOADBAR,0) & TRN_LH, DELAY(-1,38NS,57NS), + CHANGED_LH(RCK,0) & LOAD & TRN_LH, DELAY(-1,41NS,60NS), + DELAY(-1,42NS,61NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 20MEG + + WIDTH: + NODE = SRCK + MIN_HI = 15NS + MIN_LO = 35NS + + WIDTH: + NODE = RCK + MIN_HI = 20NS + + WIDTH: + NODE = SRLOADBAR + MIN_LO = 40NS + + SETUP_HOLD: + DATA(8) A B C D E F G H + CLOCK LH = RCK + SETUPTIME = 20NS + + SETUP_HOLD: + DATA(1) SRLOADBAR + CLOCK LH = SRCK + SETUPTIME_HI = 30NS + + SETUP_HOLD: + DATA(1) SER + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRLOADBAR!='0 ^ CHANGED(SRLOADBAR,0) } + + SETUP_HOLD: ; RCK RISE BEFORE LOAD RISE SETUP TIME + DATA(8) QA QB QC QD QE QF QG QH + CLOCK LH = SRLOADBAR + SETUPTIME = 40NS + MESSAGE = "RCK SETUP TIME BEFORE SRLOADBAR IS NOT MET" * .ENDS * *$ *--------- * 74LS590 8-Bit Binary Counter with Output Registers * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 07/20/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS590 GBAR_I CCK_I RCK_I CCKENBAR_I CCLRBAR_I + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTA $D_HI $D_HI JA KA + D0_EFF IO_LS U2 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTB $D_HI $D_HI JB KB + D0_EFF IO_LS U3 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTC $D_HI $D_HI JC KC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTD $D_HI $D_HI JD KD + D0_EFF IO_LS U5 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTE $D_HI $D_HI JE KE + D0_EFF IO_LS U6 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTF $D_HI $D_HI JF KF + D0_EFF IO_LS U7 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTG $D_HI $D_HI JG KG + D0_EFF IO_LS U8 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTH $D_HI $D_HI JH KH + D0_EFF IO_LS U9 JKFF(8) DPWR DGND $D_HI $D_HI MCLK + JA JB JC JD JE JF JG JH KA KB KC KD KE KF KG KH + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS590LOG LOGICEXP(14,15) DPWR DGND + GBAR_I RCK_I CCKENBAR_I CCK_I CCLRBAR_I JA JB JC JD JE JF JG JH CNTA + GBAR RCK CCKENBAR CCK CCLRBAR CNTA CNTB CNTC CNTD CNTE CNTF CNTG CNTH + MCLK RCOBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + RCK = { RCK_I } + CCKENBAR = { CCKENBAR_I } + CCK = { CCK_I } + CCLRBAR = { CCLRBAR_I } + CNTA = { ~((~(CNTA & CCKENBAR) & CCK) & CCK) } + CNTB = { JA & CNTA } + CNTC = { JB & CNTB } + CNTD = { JC & CNTC } + CNTE = { JD & CNTD } + CNTF = { JE & CNTE } + CNTG = { JF & CNTF } + CNTH = { JG & CNTG } + MCLK = { ~RCK } + RCOBAR = { ~(JH & JG & JF & JE & JD & JC & JB & JA) } * ULS590DLY PINDLY (9,1,14) DPWR DGND + QA QB QC QD QE QF QG QH RCOBAR + GBAR + GBAR RCK CCK CCK CCLRBAR CCKENBAR JA JB JC JD JE JF JG JH + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + RCOBAR_O = { + CASE( + CCLOCK & TRN_LH, DELAY(-1,14NS,22NS), + CCLOCK & TRN_HL, DELAY(-1,20NS,30NS), + DELAY(-1,30NS,45NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + RCLOCK & TRN_LH, DELAY(-1,12NS,18NS), + DISABLE & TRN_HZ, DELAY(-1,20NS,30NS), + RCLOCK & TRN_HL, DELAY(-1,22NS,33NS), + DISABLE & TRN_LZ, DELAY(-1,25NS,38NS), + ENABLE & TRN_ZH, DELAY(-1,25NS,38NS), + ENABLE & TRN_ZL, DELAY(-1,30NS,45NS), + DELAY(-1,30NS,45NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 25MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WHEN = { CCKENBAR!='1 } + WIDTH: + NODE = RCK + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(1) = CCKENBAR + CLOCK LH = CCK + SETUPTIME_LO = 20NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 20NS + SETUP_HOLD: + DATA(8) = JA JB JC JD JE JF JG JH + CLOCK LH = RCK + SETUPTIME = 40NS + WHEN = { CCKENBAR!='1 } + MESSAGE = "CCK BEFORE RCK SETUP TIME VIOLATION" * .ENDS * *$ *------------------------------------------------------------------------- * 74LS591 8-Bit Binary Counter with Output Registers * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 07/29/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices .SUBCKT 74LS591 GBAR_I CCK_I RCK_I CCKENBAR_I CCLRBAR_I + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTA $D_HI $D_HI JA KA + D0_EFF IO_LS U2 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTB $D_HI $D_HI JB KB + D0_EFF IO_LS U3 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTC $D_HI $D_HI JC KC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTD $D_HI $D_HI JD KD + D0_EFF IO_LS U5 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTE $D_HI $D_HI JE KE + D0_EFF IO_LS U6 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTF $D_HI $D_HI JF KF + D0_EFF IO_LS U7 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTG $D_HI $D_HI JG KG + D0_EFF IO_LS U8 JKFF(1) DPWR DGND $D_HI CCLRBAR CNTH $D_HI $D_HI JH KH + D0_EFF IO_LS U9 JKFF(8) DPWR DGND $D_HI $D_HI MCLK + JA JB JC JD JE JF JG JH KA KB KC KD KE KF KG KH + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS ULS591LOG LOGICEXP(22,23) DPWR DGND + GBAR_I RCK_I CCKENBAR_I CCK_I CCLRBAR_I JA JB JC JD JE JF JG JH CNTA + QA QB QC QD QE QF QG QH + GBAR RCK CCKENBAR CCK CCLRBAR CNTA CNTB CNTC CNTD CNTE CNTF CNTG CNTH + MCLK RCOBAR LQA LQB LQC LQD LQE LQF LQG LQH + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + RCK = { RCK_I } + CCKENBAR = { CCKENBAR_I } + CCK = { CCK_I } + CCLRBAR = { CCLRBAR_I } + IG = { ~GBAR } + CNTA = { ~((~(CNTA & CCKENBAR) & CCK) & CCK) } + CNTB = { JA & CNTA } + CNTC = { JB & CNTB } + CNTD = { JC & CNTC } + CNTE = { JD & CNTD } + CNTF = { JE & CNTE } + CNTG = { JF & CNTF } + CNTH = { JG & CNTG } + MCLK = { ~RCK } + RCOBAR = { ~(JH & JG & JF & JE & JD & JC & JB & JA) } + LQA = { IG & QA } + LQB = { IG & QB } + LQC = { IG & QC } + LQD = { IG & QD } + LQE = { IG & QE } + LQF = { IG & QF } + LQG = { IG & QG } + LQH = { IG & QH } ULS591DLY_1 PINDLY(8,0,3) DPWR DGND + LQA LQB LQC LQD LQE LQF LQG LQH + GBAR RCK CCK + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + RCLOCK = { CHANGED_LH(RCK,0) & GBAR!='1 } + PINDLY: + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + RCLOCK & TRN_LH, DELAY(-1,25NS,38NS), + RCLOCK & TRN_HL, DELAY(-1,28NS,42NS), + CHANGED_HL(GBAR,0) & TRN_LH, DELAY(-1,32NS,48NS), + CHANGED_LH(GBAR,0) & TRN_HL, DELAY(-1,34NS,50NS), + DELAY(-1,34NS,50NS) + ) + } ULS591DLY_2 PINDLY(1,0,2) DPWR DGND + RCOBAR + CCK CCLRBAR + RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + PINDLY: + RCOBAR_O = { + CASE( + CCLOCK & TRN_LH, DELAY(-1,16NS,24NS), + CCLOCK & TRN_HL, DELAY(-1,25NS,38NS), + CHANGED_HL(CCLRBAR,0), DELAY(-1,32NS,48NS), + DELAY(-1,32NS,48NS) + ) + } ULS591CON CONSTRAINT(12) DPWR DGND + CCK RCK CCLRBAR CCKENBAR JA JB JC JD JE JF JG JH + IO_LS + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 25MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WHEN = { CCKENBAR!='1 } + WIDTH: + NODE = RCK + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(1) = CCKENBAR + CLOCK LH = CCK + SETUPTIME_LO = 20NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 20NS + SETUP_HOLD: + DATA(8) = JA JB JC JD JE JF JG JH + CLOCK LH = RCK + SETUPTIME_HI = 40NS + WHEN = { CCKENBAR!='1 } + MESSAGE = "CCK BEFORE RCK SETUP TIME IS NOT MET" .ENDS *$ *------------------------------------------------------------------------- * 74LS592 8-Bit Binary Counter with Input Registers * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 07/15/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS592 CCK_I RCK_I CCKENBAR_I CLOADBAR_I CCLRBAR_I A_I B_I C_I + D_I E_I F_I G_I H_I RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 JKFF(1) DPWR DGND SA RA CNTA $D_HI $D_HI CQA $D_NC + D0_EFF IO_LS U2 JKFF(1) DPWR DGND SB RB CNTB $D_HI $D_HI CQB $D_NC + D0_EFF IO_LS U3 JKFF(1) DPWR DGND SC RC CNTC $D_HI $D_HI CQC $D_NC + D0_EFF IO_LS U4 JKFF(1) DPWR DGND SD RD CNTD $D_HI $D_HI CQD $D_NC + D0_EFF IO_LS U5 JKFF(1) DPWR DGND SE RE CNTE $D_HI $D_HI CQE $D_NC + D0_EFF IO_LS U6 JKFF(1) DPWR DGND SF RF CNTF $D_HI $D_HI CQF $D_NC + D0_EFF IO_LS U7 JKFF(1) DPWR DGND SG RG CNTG $D_HI $D_HI CQG $D_NC + D0_EFF IO_LS U8 JKFF(1) DPWR DGND SH RH CNTH $D_HI $D_HI CQH $D_NC + D0_EFF IO_LS U9 DFF(8) DPWR DGND $D_HI $D_HI RCK + A B C D E F G H + RQA RQB RQC RQD RQE RQF RQG RQH + RQABAR RQBBAR RQCBAR RQDBAR RQEBAR RQFBAR RQGBAR RQHBAR + D0_EFF IO_LS * ULS592LOG LOGICEXP(38,38) DPWR DGND + CCLRBAR_I CCKENBAR_I CCK_I CLOADBAR_I RCK_I A_I B_I C_I D_I E_I F_I G_I H_I + RQA RQB RQC RQD RQE RQF RQG RQH RQABAR RQBBAR RQCBAR RQDBAR RQEBAR RQFBAR + RQGBAR RQHBAR CQA CQB CQC CQD CQE CQF CQG CQH CNTA + CCLRBAR CCKENBAR CCK CLOADBAR RCK A B C D E F G H SA RA SB RB + SC RC SD RD SE RE SF RF SG RG SH RH CNTA CNTB CNTC CNTD CNTE CNTF CNTG CNTH + RCOBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CCLRBAR = { CCLRBAR_I } + CCKENBAR = { CCKENBAR_I } + CCK = { CCK_I } + CLOADBAR = { CLOADBAR_I } + RCK = { RCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + ILD = { ~CLOADBAR } + SA = { ~(RQA & ILD) } + SB = { ~(RQB & ILD) } + SC = { ~(RQC & ILD) } + SD = { ~(RQD & ILD) } + SE = { ~(RQE & ILD) } + SF = { ~(RQF & ILD) } + SG = { ~(RQG & ILD) } + SH = { ~(RQH & ILD) } + RA = { ~(ILD & RQABAR) & CCLRBAR } + RB = { ~(ILD & RQBBAR) & CCLRBAR } + RC = { ~(ILD & RQCBAR) & CCLRBAR } + RD = { ~(ILD & RQDBAR) & CCLRBAR } + RE = { ~(ILD & RQEBAR) & CCLRBAR } + RF = { ~(ILD & RQFBAR) & CCLRBAR } + RG = { ~(ILD & RQGBAR) & CCLRBAR } + RH = { ~(ILD & RQHBAR) & CCLRBAR } + CNTA = { ~((~(CNTA & CCKENBAR) & CCK) & CCK) } + CNTB = { CQA & CNTA } + CNTC = { CQB & CNTB } + CNTD = { CQC & CNTC } + CNTE = { CQD & CNTD } + CNTF = { CQE & CNTE } + CNTG = { CQF & CNTF } + CNTH = { CQG & CNTG } + RCOBAR = { ~(CQH & CQG & CQF & CQE & CQD & CQC & CQB & CQA) } * ULS592DLY PINDLY (1,0,21) DPWR DGND + RCOBAR + CCK CLOADBAR CCLRBAR RCK CCKENBAR A B C D E F G H RQA RQB RQC RQD RQE RQF RQG RQH + RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + CLOAD = { CHANGED_HL(CLOADBAR,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + PINDLY: + RCOBAR_O = { + CASE( + CCLOCK & TRN_LH, DELAY(-1,15NS,23NS), + CCLOCK & TRN_HL, DELAY(-1,20NS,30NS), + CLOAD & TRN_HL, DELAY(-1,27NS,41NS), + CHANGED_HL(CCLRBAR,0), DELAY(-1,30NS,45NS), + RCLOCK & TRN_HL, DELAY(-1,30NS,45NS), + CLOAD & TRN_LH, DELAY(-1,31NS,47NS), + RCLOCK & TRN_LH, DELAY(-1,35NS,53NS), + DELAY(-1,35NS,53NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 20NS + MIN_HI = 20NS + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + WHEN = { CLOADBAR!='0 } + WIDTH: + NODE = CLOADBAR + MIN_LO = 40NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCKENBAR + CLOCK LH = CCK + SETUPTIME_LO = 30NS + WHEN = { CLOADBAR!='0 & CCLRBAR!='0 } + SETUP_HOLD: + DATA(2) = CLOADBAR CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 20NS + WHEN = { CCKENBAR!='1 } + SETUP_HOLD: + DATA(8) = RQA RQB RQC RQD RQE RQF RQG RQH + CLOCK LH = CLOADBAR + SETUPTIME_HI = 30NS + MESSAGE = "RCK BEFORE CLOADBAR IS NOT MET" + SETUP_HOLD: + DATA(8) = A B C D E F G H + CLOCK LH = RCK + SETUPTIME = 20NS * .ENDS * *$ *--------- * 74LS594 8-BIT SHIFT REGISTERS WITH INPUT LATCHES * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-9-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS594 SRCK_I RCK_I SRCLRBAR_I RCLRBAR_I SER_I + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(5) DPWR DGND + SRCK_I RCK_I SRCLRBAR_I RCLRBAR_I SER_I + SRCK RCK SRCLRBAR RCLRBAR SER + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U2 DFF(8) DPWR DGND $D_HI SRCLRBAR SRCK + SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U3 DFF(8) DPWR DGND $D_HI RCLRBAR RCK + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS594DLY PINDLY (9,0,13) DPWR DGND + QA QB QC QD QE QF QG QH QHP + SRCK RCLRBAR SRCLRBAR RCK SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QHP_O = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,12NS,18NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,22NS,33NS), + DELAY(-1,23NS,34NS) ;DEFAULT + ) + } + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,12NS,18NS), + CHANGED_LH(RCK,0) & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_HL(RCLRBAR,0) & TRN_HL, DELAY(-1,38NS,57NS), + DELAY(-1,39NS,58NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 20MEG + + WIDTH: + NODE = SRCK + MIN_HIGH = 25NS + MIN_LOW = 25NS + + FREQ: + NODE = RCK + MAXFREQ = 25MEG + + WIDTH: + NODE = RCK + MIN_HIGH = 20NS + MIN_LOW = 20NS + + WIDTH: + NODE = SRCLRBAR + MIN_LOW = 20NS + + WIDTH: + NODE = RCLRBAR + MIN_LOW = 35NS + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 20NS + + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: ; SRCK RISE BEFORE RCK RISE SETUP TIME + DATA(8) Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + CLOCK LH = RCK + SETUPTIME_HI = 40NS + MESSAGE = "SETUPTIME VIOLATION OF SRCK BEFORE RCK" + + SETUP_HOLD: ; SRCLRBAR FALL BEFORE RCK RISE SETUP TIME + DATA(1) = SRCLRBAR + CLOCK LH = RCK + SETUPTIME_LO = 40NS + WHEN = { RCLRBAR!='0 } + + SETUP_HOLD: ; RCLRBAR RISE BEFORE RCK RISE SETUP TIME + DATA(1) = RCLRBAR + CLOCK LH = RCK + RELEASETIME_LH = 20NS * .ENDS * *$ *--------- * 74LS595 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-13-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS595 GBAR_I SRCK_I RCK_I SRCLRBAR_I SER_I + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(5) DPWR DGND + SRCK_I RCK_I SRCLRBAR_I GBAR_I SER_I + SRCK RCK SRCLRBAR GBAR SER + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U2 DFF(8) DPWR DGND $D_HI SRCLRBAR SRCK + SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U3 DFF(8) DPWR DGND $D_HI $D_HI RCK + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS595DLY PINDLY (9,1,15) DPWR DGND + QA QB QC QD QE QF QG QH QHP + GBAR + GBAR SRCK RCLRBAR SRCLRBAR RCK RCK SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QHP_O = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,12NS,18NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,24NS,35NS), + DELAY(-1,25NS,36NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED_LH(RCK,0) & TRN_HL, DELAY(-1,24NS,35NS), + TRN_LZ, DELAY(-1,25NS,38NS), + TRN_ZL, DELAY(-1,25NS,38NS), + DELAY(-1,26NS,39NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 20MEG + + WIDTH: + NODE = SRCK + MIN_HIGH = 25NS + MIN_LOW = 25NS + + WIDTH: + NODE = RCK + MIN_HIGH = 20NS + MIN_LOW = 20NS + + WIDTH: + NODE = SRCLRBAR + MIN_LOW = 20NS + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 20NS + + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRCLRBAR != '0 } + + SETUP_HOLD: ; SRCK RISE BEFORE RCK RISE SETUP TIME + DATA(8) = Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + CLOCK LH = RCK + SETUPTIME = 40NS + MESSAGE = "SETUPTIME VIOLATION OF SRCK BEFORE RCK" + + SETUP_HOLD: ; SRCLRBAR FALL BEFORE RCK RISE SETUP TIME + DATA(1) = SRCLRBAR + CLOCK LH = RCK + SETUPTIME_LO = 40NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS596 8-BIT SHIFT REGISTERS WITH OPEN-COLLECTOR OUTPUT REGISTERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-13-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS596 GBAR_I SRCK_I RCK_I SRCLRBAR_I SER_I + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(5) DPWR DGND + SRCK_I RCK_I SRCLRBAR_I GBAR_I SER_I + SRCK RCK SRCLRBAR GBAR SER + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U3 DFF(8) DPWR DGND $D_HI SRCLRBAR SRCK + SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U4 DFF(8) DPWR DGND $D_HI $D_HI RCK + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + LQA LQB LQC LQD LQE LQF LQG LQH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U5 ORA(2,8) DPWR DGND + LQA GBAR + LQB GBAR + LQC GBAR + LQD GBAR + LQE GBAR + LQF GBAR + LQG GBAR + LQH GBAR + QA QB QC QD QE QF QG QH + D0_GATE IO_LS * U596DLY PINDLY (9,0,13) DPWR DGND + QA QB QC QD QE QF QG QH QHP + GBAR SRCK SRCLRBAR RCK SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QHP_O = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,24NS,35NS), + DELAY(-1,25NS,36NS) ;DEFAULT + ) + } + + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + CHANGED_LH(RCK,0) & (GBAR != '1) & TRN_HL, DELAY(-1,24NS,35NS), + CHANGED_HL(GBAR,0) & TRN_LH, DELAY(-1,25NS,38NS), + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,28NS,42NS), + CHANGED_LH(GBAR,0) & TRN_HL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 25MEG + + WIDTH: + NODE = SRCK + MIN_HIGH = 20NS + MIN_LOW = 20NS + + WIDTH: + NODE = RCK + MIN_HIGH = 20NS + MIN_LOW = 20NS + + WIDTH: + NODE = SRCLRBAR + MIN_LOW = 20NS + + SETUP_HOLD: + DATA(1) SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 20NS + + SETUP_HOLD: + DATA(1) SER + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: ; SRCK RISE BEFORE RCK RISE SETUP TIME + CLOCK LH = RCK + DATA(8) Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + SETUPTIME = 40NS + MESSAGE = "SETUPTIME VIOLATION OF SRCK BEFORE RCK" + + SETUP_HOLD: ; SRCLRBAR FALL BEFORE RCK RISE SETUP TIME + DATA(1) SRCLRBAR + CLOCK LH = RCK + SETUPTIME_LO = 40NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS597 8-BIT SHIFT REGISTERS WITH INPUT LATCHES * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-8-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS597 SRCLRBAR_I SRCK_I SRLOADBAR_I RCK_I SER_I + A_I B_I C_I D_I E_I F_I G_I H_I QH_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS597LOG LOGICEXP(29,29) DPWR DGND + SRCLRBAR_I SRCK_I SRLOADBAR_I RCK_I SER_I A_I B_I C_I D_I E_I F_I G_I H_I + QA QB QC QD QE QF QG QHH + QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR QHHBAR + SRCLRBAR SRCK SRLOADBAR RCK SER + A B C D E F G H + SA SB SC SD SE SF SG SH RA RB RC RD RE RF RG RH + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: + + SRCLRBAR = { SRCLRBAR_I } + SRCK = { SRCK_I } + SRLOADBAR = { SRLOADBAR_I } + RCK = { RCK_I } + SER = { SER_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + E = { E_I } + F = { F_I } + G = { G_I } + H = { H_I } + + SA = { ~(~SRLOADBAR & QA) } + SB = { ~(~SRLOADBAR & QB) } + SC = { ~(~SRLOADBAR & QC) } + SD = { ~(~SRLOADBAR & QD) } + SE = { ~(~SRLOADBAR & QE) } + SF = { ~(~SRLOADBAR & QF) } + SG = { ~(~SRLOADBAR & QG) } + SH = { ~(~SRLOADBAR & QHH) } + RA = { ~(~SRCLRBAR | (~SRLOADBAR & QABAR)) } + RB = { ~(~SRCLRBAR | (~SRLOADBAR & QBBAR)) } + RC = { ~(~SRCLRBAR | (~SRLOADBAR & QCBAR)) } + RD = { ~(~SRCLRBAR | (~SRLOADBAR & QDBAR)) } + RE = { ~(~SRCLRBAR | (~SRLOADBAR & QEBAR)) } + RF = { ~(~SRCLRBAR | (~SRLOADBAR & QFBAR)) } + RG = { ~(~SRCLRBAR | (~SRLOADBAR & QGBAR)) } + RH = { ~(~SRCLRBAR | (~SRLOADBAR & QHHBAR)) } * U1 DFF(8) DPWR DGND $D_HI $D_HI RCK + A B C D E F G H + QA QB QC QD QE QF QG QHH + QABAR QBBAR QCBAR QDBAR QEBAR QFBAR QGBAR QHHBAR + D0_EFF IO_LS * U2 DFF(1) DPWR DGND + SA RA SRCK SER Q2A $D_NC + D0_EFF IO_LS * U3 DFF(1) DPWR DGND + SB RB SRCK Q2A Q2B $D_NC + D0_EFF IO_LS * U4 DFF(1) DPWR DGND + SC RC SRCK Q2B Q2C $D_NC + D0_EFF IO_LS * U5 DFF(1) DPWR DGND + SD RD SRCK Q2C Q2D $D_NC + D0_EFF IO_LS * U6 DFF(1) DPWR DGND + SE RE SRCK Q2D Q2E $D_NC + D0_EFF IO_LS * U7 DFF(1) DPWR DGND + SF RF SRCK Q2E Q2F $D_NC + D0_EFF IO_LS * U8 DFF(1) DPWR DGND + SG RG SRCK Q2F Q2G $D_NC + D0_EFF IO_LS * U9 DFF(1) DPWR DGND + SH RH SRCK Q2G QH $D_NC + D0_EFF IO_LS * ULS597DLY PINDLY (1,0,13) DPWR DGND + QH + SRCK SRLOADBAR SRCLRBAR RCK SER A B C D E F G H + QH_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + SRL = { SRLOADBAR == '0 } + + PINDLY: + QH_O = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,24NS,36NS), + CHANGED_HL(SRLOADBAR,0) & TRN_HL, DELAY(-1,29NS,44NS), + CHANGED_LH(RCK,0) & SRL & TRN_HL, DELAY(-1,32NS,48NS), + CHANGED_HL(SRLOADBAR,0) & TRN_LH, DELAY(-1,38NS,57NS), + CHANGED_LH(RCK,0) & SRL & TRN_LH, DELAY(-1,41NS,60NS), + DELAY(-1,42NS,61NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 20MEG + + WIDTH: + NODE = SRCK + MIN_HIGH = 15NS + + WIDTH: + NODE = SRCK + MIN_LOW = 35NS + + WIDTH: + NODE = RCK + MIN_HIGH = 20NS + + WIDTH: + NODE = SRCLRBAR + MIN_LOW = 20NS + + WIDTH: + NODE = SRLOADBAR + MIN_LOW = 40NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: + DATA(8) = A B C D E F G H + CLOCK LH = RCK + SETUPTIME = 20NS + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 25NS + + SETUP_HOLD: + DATA(1) = SRLOADBAR + CLOCK LH = SRCK + RELEASETIME_LH = 30NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRCLRBAR!='0 & SRLOADBAR!='0 } + + SETUP_HOLD: ; RCK RISE BEFORE LOAD RISE SETUP TIME + DATA(1) = RCK + CLOCK LH = SRLOADBAR + SETUPTIME_HI = 40NS + WHEN = { SRCLRBAR!='0 } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS598 8-BIT SHIFT REGISTERS WITH INPUT LATCHES * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-8-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS598 SRCLRBAR_I SRLOADBAR_I SRCKENBAR_I + SRCK_I RCK_I GBAR_I DS_I SER1_I SER0_I + AQA_B BQB_B CQC_B DQD_B EQE_B FQF_B GQG_B HQH_B QH_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS598LOG LOGICEXP(34,35) DPWR DGND + SRCLRBAR_I SRLOADBAR_I SRCKENBAR_I SRCK_I RCK_I GBAR_I DS_I SER1_I SER0_I + AQA_B BQB_B CQC_B DQD_B EQE_B FQF_B GQG_B HQH_B + Q1A Q1B Q1C Q1D Q1E Q1F Q1G Q1H + Q1ABAR Q1BBAR Q1CBAR Q1DBAR Q1EBAR Q1FBAR Q1GBAR Q1HBAR SRCK2 + SRCLRBAR SRLOADBAR SRCKENBAR SRCK RCK GBAR DS SER1 SER0 + AQA BQB CQC DQD EQE FQF GQG HQH + SA SB SC SD SE SF SG SH RA RB RC RD RE RF RG RH SRCK2 SER + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: + + SRCLRBAR = { SRCLRBAR_I } + SRLOADBAR = { SRLOADBAR_I } + SRCKENBAR = { SRCKENBAR_I } + SRCK = { SRCK_I } + RCK = { RCK_I } + GBAR = { GBAR_I } + DS = { DS_I } + SER1 = { SER1_I } + SER0 = { SER0_I } + AQA = { AQA_B } + BQB = { BQB_B } + CQC = { CQC_B } + DQD = { DQD_B } + EQE = { EQE_B } + FQF = { FQF_B } + GQG = { GQG_B } + HQH = { HQH_B } + + SRCK2 = { SRCK & ((SRCK2 | (~SRCKENBAR)) & (SRCK)) } + SER = {(DS & SER1) | (~DS & SER0) } + SA = { ~(~SRLOADBAR & Q1A) } + SB = { ~(~SRLOADBAR & Q1B) } + SC = { ~(~SRLOADBAR & Q1C) } + SD = { ~(~SRLOADBAR & Q1D) } + SE = { ~(~SRLOADBAR & Q1E) } + SF = { ~(~SRLOADBAR & Q1F) } + SG = { ~(~SRLOADBAR & Q1G) } + SH = { ~(~SRLOADBAR & Q1H) } + RA = { ~(~SRCLRBAR | (~SRLOADBAR & Q1ABAR)) } + RB = { ~(~SRCLRBAR | (~SRLOADBAR & Q1BBAR)) } + RC = { ~(~SRCLRBAR | (~SRLOADBAR & Q1CBAR)) } + RD = { ~(~SRCLRBAR | (~SRLOADBAR & Q1DBAR)) } + RE = { ~(~SRCLRBAR | (~SRLOADBAR & Q1EBAR)) } + RF = { ~(~SRCLRBAR | (~SRLOADBAR & Q1FBAR)) } + RG = { ~(~SRCLRBAR | (~SRLOADBAR & Q1GBAR)) } + RH = { ~(~SRCLRBAR | (~SRLOADBAR & Q1HBAR)) } * * U1 DFF(8) DPWR DGND $D_HI $D_HI RCK + AQA BQB CQC DQD EQE FQF GQG HQH + Q1A Q1B Q1C Q1D Q1E Q1F Q1G Q1H + Q1ABAR Q1BBAR Q1CBAR Q1DBAR Q1EBAR Q1FBAR Q1GBAR Q1HBAR + D0_EFF IO_LS * U2 DFF(1) DPWR DGND + SA RA SRCK2 SER LAQA $D_NC + D0_EFF IO_LS * U3 DFF(1) DPWR DGND + SB RB SRCK2 LAQA LBQB $D_NC + D0_EFF IO_LS * U4 DFF(1) DPWR DGND + SC RC SRCK2 LBQB LCQC $D_NC + D0_EFF IO_LS * U5 DFF(1) DPWR DGND + SD RD SRCK2 LCQC LDQD $D_NC + D0_EFF IO_LS * U6 DFF(1) DPWR DGND + SE RE SRCK2 LDQD LEQE $D_NC + D0_EFF IO_LS * U7 DFF(1) DPWR DGND + SF RF SRCK2 LEQE LFQF $D_NC + D0_EFF IO_LS * U8 DFF(1) DPWR DGND + SG RG SRCK2 LFQF LGQG $D_NC + D0_EFF IO_LS * U9 DFF(1) DPWR DGND + SH RH SRCK2 LGQG LHQH $D_NC + D0_EFF IO_LS * ULS598DLY PINDLY (9,1,17) DPWR DGND + LAQA LBQB LCQC LDQD LEQE LFQF LGQG LHQH LHQH + GBAR + SRCK SRLOADBAR SRCLRBAR RCK GBAR SRCKENBAR SER0 SER1 DS AQA BQB CQC DQD EQE FQF GQG HQH + AQA_B BQB_B CQC_B DQD_B EQE_B FQF_B GQG_B HQH_B QH_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QH_O = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,11NS,17NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,18NS,27NS), + CHANGED_LH(SRLOADBAR,0) & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED_LH(RCK,0) & TRN_HL, DELAY(-1,24NS,36NS), + CHANGED_LH(SRLOADBAR,0) & TRN_LH, DELAY(-1,28NS,42NS), + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,32NS,48NS), + DELAY(-1,33NS,49NS) ;DEFAULT + ) + } + + TRISTATE: + ENABLE LO GBAR + AQA_B BQB_B CQC_B DQD_B EQE_B FQF_B GQG_B HQH_B = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,12NS,18NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,19NS,28NS), + TRN_LZ, DELAY(-1,20NS,30NS), + TRN_ZH, DELAY(-1,26NS,31NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + CHANGED_HL(SRLOADBAR,0) & TRN_HL, DELAY(-1,27NS,40NS), + TRN_ZL, DELAY(-1,29NS,43NS), + CHANGED_HL(SRLOADBAR,0) & TRN_LH, DELAY(-1,32NS,48NS), + DELAY(-1,33NS,49NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 20MEG + + WIDTH: + NODE = SRCK + MIN_HIGH = 15NS + MIN_LOW = 35NS + + WIDTH: + NODE = RCK + MIN_HIGH = 20NS + + WIDTH: + NODE = SRCLRBAR + MIN_LOW = 20NS + + WIDTH: + NODE = SRLOADBAR + MIN_LOW = 40NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: + DATA(8) = AQA BQB CQC DQD EQE FQF GQG HQH + CLOCK LH = RCK + SETUPTIME = 20NS + + SETUP_HOLD: + DATA(1) = DS + CLOCK LH = SRCK + SETUPTIME = 30NS + WHEN = { SRCLRBAR!='0 & SRLOADBAR!='0 & SRCKENBAR!='1 } + + SETUP_HOLD: + DATA(2) = SER0 SER1 + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRCLRBAR!='0 & SRLOADBAR!='0 & SRCKENBAR!='1 } + + SETUP_HOLD: + DATA(1) = SRCKENBAR + CLOCK LH = SRCK + SETUPTIME_LO = 20NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 25NS + + SETUP_HOLD: + DATA(1) = SRLOADBAR + CLOCK LH = SRCK + SETUPTIME_HI = 30NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: ; RCK RISE BEFORE LOAD RISE SETUP TIME + DATA(1) = RCK + CLOCK LH = SRLOADBAR + SETUPTIME_HI = 40NS + WHEN = { SRCLRBAR!='0 } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS599 8-BIT SHIFT REGISTERS WITH INPUT LATCHES * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 7-23-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS599 SRCK_I RCK_I SRCLRBAR_I RCLRBAR_I SER_I + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(5) DPWR DGND + SRCK_I RCK_I SRCLRBAR_I RCLRBAR_I SER_I + SRCK RCK SRCLRBAR RCLRBAR SER + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U2 DFF(8) DPWR DGND $D_HI SRCLRBAR SRCK + SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U3 DFF(8) DPWR DGND $D_HI RCLRBAR RCK + Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA QB QC QD QE QF QG QH + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U599DLY PINDLY (9,0,13) DPWR DGND + QA QB QC QD QE QF QG QH QHP + SRCK RCLRBAR SRCLRBAR RCK SER Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O QHP_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + PINDLY: + QHP_O = { + CASE( + CHANGED_LH(SRCK,0) & TRN_LH, DELAY(-1,12NS,18NS), + CHANGED_LH(SRCK,0) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,24NS,35NS), + DELAY(-1,25NS,36NS) ;DEFAULT + ) + } + QA_O QB_O QC_O QD_O QE_O QF_O QG_O QH_O = { + CASE( + CHANGED_LH(RCK,0) & TRN_HL, DELAY(-1,24NS,35NS), + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,28NS,42NS), + CHANGED_HL(RCLRBAR,0) & TRN_HL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) ;DEFAULT + ) + } + + FREQ: + NODE = SRCK + MAXFREQ = 20MEG + + WIDTH: + NODE = SRCK + MIN_HIGH = 25NS + MIN_LOW = 25NS + + FREQ: + NODE = RCK + MAXFREQ = 25MEG + + WIDTH: + NODE = RCK + MIN_HIGH = 20NS + MIN_LOW = 20NS + + WIDTH: + NODE = SRCLRBAR + MIN_LOW = 20NS + + WIDTH: + NODE = RCLRBAR + MIN_LOW = 35NS + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 20NS + + SETUP_HOLD: + DATA(1) = SER + CLOCK LH = SRCK + SETUPTIME = 20NS + WHEN = { SRCLRBAR!='0 } + + SETUP_HOLD: ; SRCK RISE BEFORE RCK RISE SETUP TIME + DATA(8) = Q1A Q1B Q1C Q1D Q1E Q1F Q1G QHP + CLOCK LH = RCK + SETUPTIME_HI = 40NS + MESSAGE = "SETUPTIME VIOLATION SRCK BEFORE RCK" + + SETUP_HOLD: ; SRCLRBAR FALL BEFORE RCK RISE SETUP TIME + DATA(1) = SRCLRBAR + CLOCK LH = RCK + SETUPTIME_LO = 40NS + + SETUP_HOLD: ; RCLRBAR RISE BEFORE RCK RISE SETUP TIME + DATA(1) = RCLRBAR + CLOCK LH = RCK + RELEASETIME_LH = 20NS * .ENDS * *$ *--------- * 74LS604 Octal 2-Input Multiplexed Latches with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 8/24/89 Update interface and model names * .subckt 74LS604 A/BBAR CLK A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A/BBAR CLK A/BB CK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UAB/B inv DPWR DGND + A/BB AB/B + D0_GATE IO_LS XY1 A/BB AB/B CK A1 B1 Y1 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY2 A/BB AB/B CK A2 B2 Y2 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY3 A/BB AB/B CK A3 B3 Y3 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY4 A/BB AB/B CK A4 B4 Y4 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY5 A/BB AB/B CK A5 B5 Y5 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY6 A/BB AB/B CK A6 B6 Y6 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY7 A/BB AB/B CK A7 B7 Y7 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY8 A/BB AB/B CK A8 B8 Y8 DPWR DGND LS604DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS604DAT A/BB AB/B CK D1 D2 Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB dff(2) DPWR DGND + $D_HI $D_HI CK D1 D2 A B $D_NC $D_NC + D_LS604_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UAB/BD buf DPWR DGND + AB/B AB/BD + D_LS604_2 IO_LS MNTYMXDLY={MNTYMXDLY} UYI ao(2,2) DPWR DGND + A/BB A AB/BD B YI + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UY buf3 DPWR DGND + YI CK Y + D_LS604_3 IO_LS MNTYMXDLY={MNTYMXDLY} .ends * .model D_LS604_1 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=20ns + ) .model D_LS604_2 ugate ( + tplhty=16ns tplhmx=20ns + tphlty=4ns tphlmx=5ns + ) .model D_LS604_3 utgate ( + tplhty=15ns tplhmx=25ns + tphlty=19ns tphlmx=30ns + tpzhty=19ns tpzhmx=30ns + tpzlty=28ns tpzlmx=40ns + tphzty=20ns tphzmx=30ns + tplzty=15ns tplzmx=25ns + ) *$ *------------------------------------------------------------------------- * 74LS605 Octal 2-Input Multiplexed Latches with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 8/25/89 Update interface and model names * .subckt 74LS605 A/BBAR CLK A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A/BBAR CLK A/BB CK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UAB/B inv DPWR DGND + A/BB AB/B + D0_GATE IO_LS XY1 A/BB AB/B CK A1 B1 Y1 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY2 A/BB AB/B CK A2 B2 Y2 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY3 A/BB AB/B CK A3 B3 Y3 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY4 A/BB AB/B CK A4 B4 Y4 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY5 A/BB AB/B CK A5 B5 Y5 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY6 A/BB AB/B CK A6 B6 Y6 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY7 A/BB AB/B CK A7 B7 Y7 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY8 A/BB AB/B CK A8 B8 Y8 DPWR DGND LS605DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS605DAT A/BB AB/B CK D1 D2 Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB dff(2) DPWR DGND + $D_HI $D_HI CK D1 D2 A B $D_NC $D_NC + D_LS605_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCKB inv DPWR DGND + CK CKB + D0_GATE IO_LS UA/BBD buf DPWR DGND + A/BB A/BBD + D_LS605_2 IO_LS MNTYMXDLY={MNTYMXDLY} UAB/BD buf DPWR DGND + AB/B AB/BD + D_LS605_3 IO_LS MNTYMXDLY={MNTYMXDLY} UYI ao(2,2) DPWR DGND + A/BBD A AB/BD B YI + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UY or(2) DPWR DGND + YI CKB Y + D_LS605_4 IO_LS_OC MNTYMXDLY={MNTYMXDLY} .ends * .model D_LS605_1 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=20ns + ) .model D_LS605_2 ugate ( + tplhty=1ns tplhmx=1ps + ) .model D_LS605_3 ugate ( + tplhty=12ns tplhmx=20ns + tphlty=3ns tphlmx=1ps + ) .model D_LS605_4 ugate ( + tplhty=27ns tplhmx=40ns + tphlty=25ns tphlmx=40ns + ) *$ *------------------------------------------------------------------------- * 74LS606 Octal 2-Input Multiplexed Latches with 3-STATE Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 8/24/89 Update interface and model names * .subckt 74LS606 A/BBAR CLK A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A/BBAR CLK A/BB CK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UAB/B inv DPWR DGND + A/BB AB/B + D0_GATE IO_LS XY1 A/BB AB/B CK A1 B1 Y1 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY2 A/BB AB/B CK A2 B2 Y2 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY3 A/BB AB/B CK A3 B3 Y3 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY4 A/BB AB/B CK A4 B4 Y4 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY5 A/BB AB/B CK A5 B5 Y5 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY6 A/BB AB/B CK A6 B6 Y6 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY7 A/BB AB/B CK A7 B7 Y7 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY8 A/BB AB/B CK A8 B8 Y8 DPWR DGND LS606DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS606DAT A/BB AB/B CK D1 D2 Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB dff(2) DPWR DGND + $D_HI $D_HI CK D1 D2 A B $D_NC $D_NC + D_LS606_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UA/BBD buf DPWR DGND + A/BB A/BBD + D_LS606_2 IO_LS MNTYMXDLY={MNTYMXDLY} UYI ao(2,2) DPWR DGND + A/BBD A AB/B B YI + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UY buf3 DPWR DGND + YI CK Y + D_LS606_3 IO_LS MNTYMXDLY={MNTYMXDLY} .ends * .model D_LS606_1 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=20ns + ) .model D_LS606_2 ugate ( + tplhty=14ns tplhmx=15ns + tphlty=6ns tphlmx=5ns + ) .model D_LS606_3 utgate ( + tplhty=22ns tplhmx=35ns + tphlty=16ns tphlmx=30ns + tpzhty=27ns tpzhmx=40ns + tpzlty=35ns tpzlmx=50ns + tphzty=20ns tphzmx=30ns + tplzty=15ns tplzmx=25ns + ) *$ *------------------------------------------------------------------------- * 74LS607 Octal 2-Input Multiplexed Latches with Open-Collector Outputs * * The TTL Data Book, Vol 2, 1985, TI * atl 8/25/89 Update interface and model names * .subckt 74LS607 A/BBAR CLK A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 + Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 + optional: DPWR=$G_DPWR DGND=$G_DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UBUF bufa(2) DPWR DGND + A/BBAR CLK A/BB CK + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UAB/B inv DPWR DGND + A/BB AB/B + D0_GATE IO_LS XY1 A/BB AB/B CK A1 B1 Y1 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY2 A/BB AB/B CK A2 B2 Y2 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY3 A/BB AB/B CK A3 B3 Y3 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY4 A/BB AB/B CK A4 B4 Y4 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY5 A/BB AB/B CK A5 B5 Y5 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY6 A/BB AB/B CK A6 B6 Y6 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY7 A/BB AB/B CK A7 B7 Y7 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} XY8 A/BB AB/B CK A8 B8 Y8 DPWR DGND LS607DAT + params: MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ends * .subckt LS607DAT A/BB AB/B CK D1 D2 Y DPWR DGND + params: MNTYMXDLY=0 IO_LEVEL=0 UAB dff(2) DPWR DGND + $D_HI $D_HI CK D1 D2 A B $D_NC $D_NC + D_LS607_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UCKB inv DPWR DGND + CK CKB + D_LS607_2 IO_LS MNTYMXDLY={MNTYMXDLY} UA/BBD buf DPWR DGND + A/BB A/BBD + D_LS607_3 IO_LS MNTYMXDLY={MNTYMXDLY} UYI ao(2,2) DPWR DGND + A/BBD A AB/B B YI + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UY or(2) DPWR DGND + YI CKB Y + D_LS607_4 IO_LS_OC MNTYMXDLY={MNTYMXDLY} .ends * .model D_LS607_1 ueff ( + twclklmn=20ns twclkhmn=20ns + tsudclkmn=20ns + ) .model D_LS607_2 ugate ( + tplhty=2ns tplhmx=5ns + tphlty=11ns tphlmx=15ns + ) .model D_LS607_3 ugate ( + tplhty=23ns tplhmx=30ns + tphlty=7ns tphlmx=10ns + ) .model D_LS607_4 ugate ( + tplhty=28ns tplhmx=40ns + tphlty=21ns tphlmx=30ns + ) * *$ *---------- * 74LS620 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74LS620 GBABAR_I GAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + GAB_I GAB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + GBABAR_I GBA + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U3 INV3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_LS620 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 INV3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_LS620 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_LS620 UTGATE ( + TPLHTY= 6NS TPLHMX=10NS + TPHLTY= 8NS TPHLMX=15NS + TPZHTY=23NS TPZHMX=40NS + TPZLTY=31NS TPZLMX=40NS + TPHZTY=15NS TPHZMX=25NS + TPLZTY=15NS TPLZMX=25NS + ) * .ENDS * *$ *--------- * 74LS621 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS621 GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUF BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + A1_ST A2_ST A3_ST A4_ST A5_ST A6_ST A7_ST A8_ST + B1_ST B2_ST B3_ST B4_ST B5_ST B6_ST B7_ST B8_ST + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS621LOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_ST A2_ST A3_ST A4_ST A5_ST A6_ST A7_ST A8_ST + B1_ST B2_ST B3_ST B4_ST B5_ST B6_ST B7_ST B8_ST + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 + B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + GABBAR = { ~GAB_I } + * OUTPUT FSIGNMENTS + A1 = { B1_ST | GBABAR } + A2 = { B2_ST | GBABAR } + A3 = { B3_ST | GBABAR } + A4 = { B4_ST | GBABAR } + A5 = { B5_ST | GBABAR } + A6 = { B6_ST | GBABAR } + A7 = { B7_ST | GBABAR } + A8 = { B8_ST | GBABAR } + B1 = { A1_ST | GABBAR } + B2 = { A2_ST | GABBAR } + B3 = { A3_ST | GABBAR } + B4 = { A4_ST | GABBAR } + B5 = { A5_ST | GABBAR } + B6 = { A6_ST | GABBAR } + B7 = { A7_ST | GABBAR } + B8 = { A8_ST | GABBAR } * ULS621DLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1_ST A2_ST A3_ST A4_ST A5_ST A6_ST A7_ST A8_ST B1_ST B2_ST B3_ST B4_ST B5_ST B6_ST B7_ST B8_ST + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(-1,34NS,50NS), + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(-1,23NS,40NS), + A_OUTPUT & TRN_LH, DELAY(-1,17NS,25NS), + A_OUTPUT & TRN_HL, DELAY(-1,16NS,25NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(-1,35NS,51NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(-1,37NS,50NS), + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(-1,25NS,40NS), + B_OUTPUT & TRN_LH, DELAY(-1,17NS,25NS), + B_OUTPUT & TRN_HL, DELAY(-1,16NS,25NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(-1,38NS,51NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS622 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * KN 8/28/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS622 GBABAR_I GAB_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUF BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + A1_ST A2_ST A3_ST A4_ST A5_ST A6_ST A7_ST A8_ST + B1_ST B2_ST B3_ST B4_ST B5_ST B6_ST B7_ST B8_ST + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS622LOG LOGICEXP(18,18) DPWR DGND + GBABAR_I GAB_I A1_ST A2_ST A3_ST A4_ST A5_ST A6_ST A7_ST A8_ST + B1_ST B2_ST B3_ST B4_ST B5_ST B6_ST B7_ST B8_ST + GBABAR GAB A1 A2 A3 A4 A5 A6 A7 A8 + B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER: + GBABAR = { GBABAR_I } + GBA = { ~GBABAR } + GAB = { GAB_I } + * OUTPUT ASSIGNMENTS + A1 = { ~(B1_ST & GBA) } + A2 = { ~(B2_ST & GBA) } + A3 = { ~(B3_ST & GBA) } + A4 = { ~(B4_ST & GBA) } + A5 = { ~(B5_ST & GBA) } + A6 = { ~(B6_ST & GBA) } + A7 = { ~(B7_ST & GBA) } + A8 = { ~(B8_ST & GBA) } + B1 = { ~(A1_ST & GAB) } + B2 = { ~(A2_ST & GAB) } + B3 = { ~(A3_ST & GAB) } + B4 = { ~(A4_ST & GAB) } + B5 = { ~(A5_ST & GAB) } + B6 = { ~(A6_ST & GAB) } + B7 = { ~(A7_ST & GAB) } + B8 = { ~(A8_ST & GAB) } * ULS622DLY PINDLY (16,0,18) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBABAR GAB A1_ST A2_ST A3_ST A4_ST A5_ST A6_ST A7_ST A8_ST B1_ST B2_ST B3_ST B4_ST B5_ST B6_ST B7_ST B8_ST + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_OUTPUT = { (GBABAR!='1 & GAB!='1) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + B_OUTPUT = { (GBABAR!='0 & GAB!='0) | (GBABAR!='1 & GAB!='0) | + (GBABAR!='0 & GAB!='1) } + GBABAR_CHANGE = { CHANGED(GBABAR,0) } + GAB_CHANGE = { CHANGED(GAB,0) } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_OUTPUT & GBABAR_CHANGE & TRN_HL, DELAY(-1,43NS,60NS), + A_OUTPUT & GBABAR_CHANGE & TRN_LH, DELAY(-1,26NS,40NS), + A_OUTPUT & TRN_LH, DELAY(-1,19NS,25NS), + A_OUTPUT & TRN_HL, DELAY(-1,14NS,25NS), + B_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(-1,44NS,61NS) ;DEFAULT + ) + } + + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_OUTPUT & GAB_CHANGE & TRN_HL, DELAY(-1,39NS,60NS), + B_OUTPUT & GAB_CHANGE & TRN_LH, DELAY(-1,28NS,40NS), + B_OUTPUT & TRN_LH, DELAY(-1,19NS,25NS), + B_OUTPUT & TRN_HL, DELAY(-1,14NS,25NS), + A_OUTPUT, DELAY(0NS,0NS,0NS), + DELAY(-1,40NS,61NS) ;DEFAULT + ) + } * .ENDS * *$ *---------- * 74LS623 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74LS623 GBABAR_I GAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUF DPWR DGND + GAB_I GAB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + GBABAR_I GBA + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * U3 BUF3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + GAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_LS623 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U4 BUF3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_LS623 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_LS623 UTGATE ( + TPLHTY= 8NS TPLHMX=15NS + TPHLTY=11NS TPHLMX=15NS + TPZHTY=26NS TPZHMX=40NS + TPZLTY=31NS TPZLMX=40NS + TPHZTY=15NS TPHZMX=25NS + TPLZTY=15NS TPLZMX=25NS + ) * .ENDS * *$ *--------- * 74LS638 BUS TRANSCEIVERS OCTAL WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS * * THE TTL DATA BOOK, 1988, TI * TC 09/11/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74LS638 GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 ULS638LOG LOGICEXP(18,35) DPWR DGND + GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O ENB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ENA = { ~(GBAR | DIR) } + ENB = { ~GBAR & DIR } + A1_O = { ~(ENA & B1) } + A2_O = { ~(ENA & B2) } + A3_O = { ~(ENA & B3) } + A4_O = { ~(ENA & B4) } + A5_O = { ~(ENA & B5) } + A6_O = { ~(ENA & B6) } + A7_O = { ~(ENA & B7) } + A8_O = { ~(ENA & B8) } + B1_O = { ~A1 } + B2_O = { ~A2 } + B3_O = { ~A3 } + B4_O = { ~A4 } + B5_O = { ~A5 } + B6_O = { ~A6 } + B7_O = { ~A7 } + B8_O = { ~A8 } ULS638DLY_1 PINDLY(8,0,9) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBAR B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + ENABLE & TRN_HL, DELAY(-1,43NS,60NS), + ENABLE & TRN_LH, DELAY(-1,26NS,40NS), + BUS_B & TRN_LH, DELAY(-1,17NS,25NS), + BUS_B & TRN_HL, DELAY(-1,14NS,25NS), + DELAY(-1,44NS,61NS) + ) + } ULS638DLY_2 PINDLY(8,1,8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O + ENB + A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A & TRN_LH, DELAY(-1,6NS,10NS), + BUS_A & TRN_HL, DELAY(-1,8NS,15NS), + TRN_ZH, DELAY(-1,23NS,40NS), + TRN_ZL, DELAY(-1,31NS,40NS), + TRN_$Z, DELAY(-1,15NS,25NS), + DELAY(-1,32NS,41NS) + ) + } .ENDS *$ *--------- * 74LS639 BUS TRANSCEIVERS OCTAL WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS * * THE TTL DATA BOOK, 1988, TI * TC 09/11/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES .SUBCKT 74LS639 GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 ULS639LOG LOGICEXP(18,35) DPWR DGND + GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O ENB + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + DIR = { DIR_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ENA = { ~(GBAR | DIR) } + ENB = { ~GBAR & DIR } + A1_O = { ~(ENA & ~B1) } + A2_O = { ~(ENA & ~B2) } + A3_O = { ~(ENA & ~B3) } + A4_O = { ~(ENA & ~B4) } + A5_O = { ~(ENA & ~B5) } + A6_O = { ~(ENA & ~B6) } + A7_O = { ~(ENA & ~B7) } + A8_O = { ~(ENA & ~B8) } + B1_O = { A1 } + B2_O = { A2 } + B3_O = { A3 } + B4_O = { A4 } + B5_O = { A5 } + B6_O = { A6 } + B7_O = { A7 } + B8_O = { A8 } ULS639DLY_1 PINDLY(8,0,9) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBAR B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_B = { CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0) | + CHANGED(B5,0) | CHANGED(B6,0) | CHANGED(B7,0) | CHANGED(B8,0) } + ENABLE = { CHANGED(GBAR,0) } + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + ENABLE & TRN_LH, DELAY(-1,23NS,40NS), + ENABLE & TRN_HL, DELAY(-1,34NS,50NS), + BUS_B & TRN_LH, DELAY(-1,19NS,25NS), + BUS_B & TRN_HL, DELAY(-1,16NS,25NS), + DELAY(-1,35NS,51NS) + ) + } ULS639DLY_2 PINDLY(8,1,8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O + ENB + A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + BUS_A = { CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) | + CHANGED(A5,0) | CHANGED(A6,0) | CHANGED(A7,0) | CHANGED(A8,0) } + TRISTATE: + ENABLE HI ENB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + BUS_A & TRN_LH, DELAY(-1,8NS,15NS), + BUS_A & TRN_HL, DELAY(-1,11NS,15NS), + TRN_ZH, DELAY(-1,26NS,40NS), + TRN_ZL, DELAY(-1,31NS,40NS), + TRN_$Z, DELAY(-1,15NS,25NS), + DELAY(-1,32NS,41NS) + ) + } .ENDS *$ *---------- * 74LS640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 9-3-92 UPDATE TIMING * .SUBCKT 74LS640 GBAR_I DIR_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(2) DPWR DGND + GBAR_I DIR_I + GBAR DIR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} U2 INV DPWR DGND + DIR DIRBAR + D0_GATE IO_LS U3 NORA(2,2) DPWR DGND + DIRBAR GBAR DIR GBAR + ENABLEAB ENABLEBA + D0_GATE IO_LS * U4 INV3A(8) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + ENABLEAB + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + D_LS640 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U5 INV3A(8) DPWR DGND + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + ENABLEBA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + D_LS640 IO_LS_ST + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} * .MODEL D_LS640 UTGATE ( + TPLHTY= 6NS TPLHMX=10NS + TPHLTY= 8NS TPHLMX=15NS + TPZHTY=23NS TPZHMX=40NS + TPZLTY=31NS TPZLMX=40NS + TPHZTY=15NS TPHZMX=25NS + TPLZTY=15NS TPLZMX=25NS + ) * .ENDS * *$ *--------- * 74LS641 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS641 GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS641LOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 + ATOB BTOA + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + IA1 = { ~(~B1 & BTOA) } + IA2 = { ~(~B2 & BTOA) } + IA3 = { ~(~B3 & BTOA) } + IA4 = { ~(~B4 & BTOA) } + IA5 = { ~(~B5 & BTOA) } + IA6 = { ~(~B6 & BTOA) } + IA7 = { ~(~B7 & BTOA) } + IA8 = { ~(~B8 & BTOA) } + IB1 = { ~(~A1 & ATOB) } + IB2 = { ~(~A2 & ATOB) } + IB3 = { ~(~A3 & ATOB) } + IB4 = { ~(~A4 & ATOB) } + IB5 = { ~(~A5 & ATOB) } + IB6 = { ~(~A6 & ATOB) } + IB7 = { ~(~A7 & ATOB) } + IB8 = { ~(~A8 & ATOB) } * ULS641DLY PINDLY (16,0,4) DPWR DGND + IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(-1,34NS,50NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,34NS,50NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,23NS,40NS), + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(-1,23NS,40NS), + A_EN & TRN_LH, DELAY(-1,17NS,25NS), + A_EN & TRN_HL, DELAY(-1,16NS,25NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(38NS,-1,51NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(-1,37NS,50NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,37NS,50NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,25NS,40NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(-1,25NS,40NS), + B_EN & TRN_LH, DELAY(-1,17NS,25NS), + B_EN & TRN_HL, DELAY(-1,16NS,25NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(38NS,-1,51NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS642 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS642 GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS642LOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 + ATOB BTOA + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + IA1 = { ~(B1 & BTOA) } + IA2 = { ~(B2 & BTOA) } + IA3 = { ~(B3 & BTOA) } + IA4 = { ~(B4 & BTOA) } + IA5 = { ~(B5 & BTOA) } + IA6 = { ~(B6 & BTOA) } + IA7 = { ~(B7 & BTOA) } + IA8 = { ~(B8 & BTOA) } + IB1 = { ~(A1 & ATOB) } + IB2 = { ~(A2 & ATOB) } + IB3 = { ~(A3 & ATOB) } + IB4 = { ~(A4 & ATOB) } + IB5 = { ~(A5 & ATOB) } + IB6 = { ~(A6 & ATOB) } + IB7 = { ~(A7 & ATOB) } + IB8 = { ~(A8 & ATOB) } * ULS642DLY PINDLY (16,0,4) DPWR DGND + IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,43NS,60NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(-1,43NS,60NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,26NS,40NS), + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(-1,26NS,40NS), + A_EN & TRN_LH, DELAY(-1,19NS,25NS), + A_EN & TRN_HL, DELAY(-1,14NS,25NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(40NS,-1,61NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,39NS,60NS), + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(-1,39NS,60NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,28NS,40NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(-1,28NS,40NS), + B_EN & TRN_LH, DELAY(-1,19NS,25NS), + B_EN & TRN_HL, DELAY(-1,14NS,25NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(40NS,-1,61NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS * * THE TTL DATA BOOK, VOL 2, 1985, TI * ATL 9/8/89 UPDATE INTERFACE AND MODEL NAMES * KC 9/1/92 * .SUBCKT 74LS643 GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 UBUF BUF DPWR DGND + DIR DR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UINV INVA(2) DPWR DGND + DR GBAR DRB G + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UEN ANDA(2,2) DPWR DGND + DR G DRB G EAB EBA + D0_GATE IO_LS UA BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + EBA + A1 A2 A3 A4 A5 A6 A7 A8 + D_LS643_1 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} UB INV3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + EAB + B1 B2 B3 B4 B5 B6 B7 B8 + D_LS643_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS * .MODEL D_LS643_1 UTGATE ( + TPLHTY=8NS TPLHMX=15NS + TPHLTY=11NS TPHLMX=15NS + TPZHTY=27NS TPZHMX=40NS + TPZLTY=32NS TPZLMX=45NS + TPHZTY=15NS TPHZMX=25NS + TPLZTY=15NS TPLZMX=25NS + ) .MODEL D_LS643_2 UTGATE ( + TPLHTY=6NS TPLHMX=10NS + TPHLTY=9NS TPHLMX=15NS + TPZHTY=23NS TPZHMX=40NS + TPZLTY=32NS TPZLMX=45NS + TPHZTY=15NS TPHZMX=25NS + TPLZTY=15NS TPLZMX=25NS + ) * *$ *--------- * 74LS644 OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS644 GBAR_I DIR_I A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(16) DPWR DGND + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS644LOG LOGICEXP(18,20) DPWR DGND + GBAR_I DIR_I A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + GBAR DIR IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 + ATOB BTOA + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: + * BUFFER + GBAR = { GBAR_I } + DIR = { DIR_I } + * OUTPUT ASSIGNMENTS + ATOB = { ~GBAR & DIR } + BTOA = { ~GBAR & ~DIR } + IA1 = { ~(~B1 & BTOA) } + IA2 = { ~(~B2 & BTOA) } + IA3 = { ~(~B3 & BTOA) } + IA4 = { ~(~B4 & BTOA) } + IA5 = { ~(~B5 & BTOA) } + IA6 = { ~(~B6 & BTOA) } + IA7 = { ~(~B7 & BTOA) } + IA8 = { ~(~B8 & BTOA) } + IB1 = { ~(A1 & ATOB) } + IB2 = { ~(A2 & ATOB) } + IB3 = { ~(A3 & ATOB) } + IB4 = { ~(A4 & ATOB) } + IB5 = { ~(A5 & ATOB) } + IB6 = { ~(A6 & ATOB) } + IB7 = { ~(A7 & ATOB) } + IB8 = { ~(A8 & ATOB) } * ULS644DLY PINDLY (16,0,4) DPWR DGND + IA1 IA2 IA3 IA4 IA5 IA6 IA7 IA8 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 + GBAR DIR ATOB BTOA + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B + B5_B B6_B B7_B B8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + A_EN = { BTOA!='0 } + B_EN = { ATOB!='0 } + + PINDLY: + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,43NS,60NS), + A_EN & CHANGED(DIR,0) & TRN_HL, DELAY(-1,43NS,60NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,26NS,40NS), + A_EN & CHANGED(DIR,0) & TRN_LH, DELAY(-1,26NS,40NS), + A_EN & TRN_LH, DELAY(-1,19NS,25NS), + A_EN & TRN_HL, DELAY(-1,16NS,25NS), + B_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(44NS,-1,61NS) ;DEFAULT + ) + } + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,37NS,50NS), + B_EN & CHANGED(DIR,0) & TRN_HL, DELAY(-1,37NS,50NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,25NS,40NS), + B_EN & CHANGED(DIR,0) & TRN_LH, DELAY(-1,25NS,40NS), + B_EN & TRN_LH, DELAY(-1,17NS,25NS), + B_EN & TRN_HL, DELAY(-1,14NS,25NS), + A_EN & CHANGED(DIR,0), DELAY(0,0,0), + DELAY(38NS,-1,51NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS645 OCTAL BUS TRANSCEIVERS * * THE TTL DATA BOOK, VOL 2, 1985, TI * ATL 7/24/89 UPDATE INTERFACE AND MODEL NAMES * .SUBCKT 74LS645 GBAR DIR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UBUFF BUFA(2) DPWR DGND + GBAR DIR GBAR_BUF DIR_BUF + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} UA NOR(2) DPWR DGND + GBAR_BUF DIR_BUF T1 + D0_GATE IO_LS UB INV DPWR DGND + GBAR_BUF RE1 + D0_GATE IO_LS UC AND(2) DPWR DGND + RE1 DIR_BUF T2 + D0_GATE IO_LS U1 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 + T2 + B1 B2 B3 B4 B5 B6 B7 B8 + D_LS645 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} U2 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 + T1 + A1 A2 A3 A4 A5 A6 A7 A8 + D_LS645 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .ENDS * .MODEL D_LS645 UTGATE ( + TPLHTY=8NS TPLHMX=15NS + TPHLTY=11NS TPHLMX=15NS + TPZHTY=26NS TPZHMX=40NS + TPZLTY=31NS TPZLMX=40NS + TPHZTY=15NS TPHZMX=25NS + TPLZTY=15NS TPLZMX=25NS + ) * *$ *--------- * 74LS646 OCTAL BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS * * High-Speed CMOS Logic Data Book, 1991, PHILIPS SEMICONDUCTORS * JSW 8/31/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS646 GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U_NO_HYST BUFA(2) DPWR DGND + GBAR_I DIR_I + GBAR DIR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * ULS646LOG1 LOGICEXP(38,38) DPWR DGND + GBAR DIR CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT + B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} + LOGIC: + CBA = { CBA_I } + SBA = { SBA_I } + SBABAR = { ~SBA } + CAB = { CAB_I } + SAB = { SAB_I } + SABBAR = { ~SAB } + ENA = { ~DIR & ~GBAR } + ENB = { DIR & ~GBAR } + A1 = { A1_B } + B1 = { B1_B } + A2 = { A2_B } + B2 = { B2_B } + A3 = { A3_B } + B3 = { B3_B } + A4 = { A4_B } + B4 = { B4_B } + A5 = { A5_B } + B5 = { B5_B } + A6 = { A6_B } + B6 = { B6_B } + A7 = { A7_B } + B7 = { B7_B } + A8 = { A8_B } + B8 = { B8_B } + A1_OUT = { ~((~B1 & SBABAR) | (SBA & QB1)) } + B1_OUT = { ~((~A1 & SABBAR) | (SAB & QA1)) } + A2_OUT = { ~((~B2 & SBABAR) | (SBA & QB2)) } + B2_OUT = { ~((~A2 & SABBAR) | (SAB & QA2)) } + A3_OUT = { ~((~B3 & SBABAR) | (SBA & QB3)) } + B3_OUT = { ~((~A3 & SABBAR) | (SAB & QA3)) } + A4_OUT = { ~((~B4 & SBABAR) | (SBA & QB4)) } + B4_OUT = { ~((~A4 & SABBAR) | (SAB & QA4)) } + A5_OUT = { ~((~B5 & SBABAR) | (SBA & QB5)) } + B5_OUT = { ~((~A5 & SABBAR) | (SAB & QA5)) } + A6_OUT = { ~((~B6 & SBABAR) | (SBA & QB6)) } + B6_OUT = { ~((~A6 & SABBAR) | (SAB & QA6)) } + A7_OUT = { ~((~B7 & SBABAR) | (SBA & QB7)) } + B7_OUT = { ~((~A7 & SABBAR) | (SAB & QA7)) } + A8_OUT = { ~((~B8 & SBABAR) | (SBA & QB8)) } + B8_OUT = { ~((~A8 & SABBAR) | (SAB & QA8)) } * UAREG DFF(8) DPWR DGND $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + D0_EFF IO_LS * UBREG DFF(8) DPWR DGND $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + D0_EFF IO_LS * ULS646DLY PINDLY (16,2,23) DPWR DGND + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 CAB CBA SAB SBA GBAR DIR DIR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + TRISTATE: + ENABLE HI ENA + A1_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B1,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B1,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B1!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B1!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A2_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B2,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B2,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B2!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B2!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A3_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B3,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B3,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B3!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B3!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A4_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B4,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B4,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B4!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B4!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A5_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B5,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B5,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B5!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B5!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A6_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B6,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B6,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B6!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B6!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A7_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B7,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B7,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B7!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B7!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,23NS,35NS), + CHANGED(B8,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B8,0) & TRN_HL & SBA!='1, DELAY(-1,13NS,20NS), + CHANGED(SBA,0) & B8!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & B8!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A1,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A1,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A1!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A1!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B2_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A2,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A2,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A2!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A2!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B3_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A3,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A3,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A3!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A3!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B4_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A4,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A4,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A4!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A4!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B5_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A5,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A5,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A5!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A5!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B6_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A6,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A6,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A6!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A6!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B7_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A7,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A7,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A7!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A7!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,23NS,35NS), + CHANGED(A8,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A8,0) & TRN_HL & SAB!='1, DELAY(-1,13NS,20NS), + CHANGED(SAB,0) & A8!='0 & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & A8!='0 & TRN_HL, DELAY(-1,21NS,35NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,33NS,50NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,33NS,55NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,42NS,65NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,23NS,35NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,28NS,45NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,39NS,60NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,20NS,30NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,40NS,66NS) + ) + } + WIDTH: + NODE = CAB + MIN_HI = 15NS + MIN_LO = 30NS + WIDTH: + NODE = CBA + MIN_HI = 15NS + MIN_LO = 30NS + WIDTH: + NODE = A1 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A2 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A3 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A4 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A5 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A6 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A7 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A8 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = B1 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B2 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B3 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B4 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B5 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B6 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B7 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B8 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 15NS + WHEN = { DIR!='0 } + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 15NS + WHEN = { DIR!='1 } * .ENDS * *$ *--------- * 74LS648 OCTAL BUS TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS * * High-Speed CMOS Logic Data Book, 1991, PHILIPS SEMICONDUCTORS * JSW 9/7/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS648 GBAR_I DIR_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U_NO_HYST BUFA(2) DPWR DGND GBAR_I DIR_I GBAR DIR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} * ULS648LOG1 LOGICEXP(38,38) DPWR DGND + GBAR DIR CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT + B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} + LOGIC: + CBA = { CBA_I } + SBA = { SBA_I } + SBABAR = { ~SBA } + CAB = { CAB_I } + SAB = { SAB_I } + SABBAR = { ~SAB } + ENA = { ~DIR & ~GBAR } + ENB = { DIR & ~GBAR } + A1 = { A1_B } + B1 = { B1_B } + A2 = { A2_B } + B2 = { B2_B } + A3 = { A3_B } + B3 = { B3_B } + A4 = { A4_B } + B4 = { B4_B } + A5 = { A5_B } + B5 = { B5_B } + A6 = { A6_B } + B6 = { B6_B } + A7 = { A7_B } + B7 = { B7_B } + A8 = { A8_B } + B8 = { B8_B } + A1_OUT = { ~((B1 & SBABAR) | (SBA & QB1)) } + B1_OUT = { ~((A1 & SABBAR) | (SAB & QA1)) } + A2_OUT = { ~((B2 & SBABAR) | (SBA & QB2)) } + B2_OUT = { ~((A2 & SABBAR) | (SAB & QA2)) } + A3_OUT = { ~((B3 & SBABAR) | (SBA & QB3)) } + B3_OUT = { ~((A3 & SABBAR) | (SAB & QA3)) } + A4_OUT = { ~((B4 & SBABAR) | (SBA & QB4)) } + B4_OUT = { ~((A4 & SABBAR) | (SAB & QA4)) } + A5_OUT = { ~((B5 & SBABAR) | (SBA & QB5)) } + B5_OUT = { ~((A5 & SABBAR) | (SAB & QA5)) } + A6_OUT = { ~((B6 & SBABAR) | (SBA & QB6)) } + B6_OUT = { ~((A6 & SABBAR) | (SAB & QA6)) } + A7_OUT = { ~((B7 & SBABAR) | (SBA & QB7)) } + B7_OUT = { ~((A7 & SABBAR) | (SAB & QA7)) } + A8_OUT = { ~((B8 & SBABAR) | (SBA & QB8)) } + B8_OUT = { ~((A8 & SABBAR) | (SAB & QA8)) } * UAREG DFF(8) DPWR DGND $D_HI $D_HI CAB + A1 A2 A3 A4 A5 A6 A7 A8 + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * UBREG DFF(8) DPWR DGND $D_HI $D_HI CBA + B1 B2 B3 B4 B5 B6 B7 B8 + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * ULS648DLY PINDLY (16,2,23) DPWR DGND + A1_OUT A2_OUT A3_OUT A4_OUT A5_OUT A6_OUT A7_OUT A8_OUT B1_OUT B2_OUT B3_OUT B4_OUT B5_OUT B6_OUT B7_OUT B8_OUT + ENA ENB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 CAB CBA SAB SBA GBAR DIR DIR + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + TRISTATE: + ENABLE HI ENA + A1_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B1,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B1,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B1!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B1!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A2_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B2,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B2,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B2!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B2!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A3_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B3,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B3,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B3!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B3!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A4_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B4,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B4,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B4!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B4!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A5_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B5,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B5,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B5!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B5!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A6_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B6,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B6,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B6!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B6!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A7_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B7,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B7,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B7!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B7!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + A8_B = { + CASE( + CHANGED(CBA,0) & TRN_LH & SBA=='1, DELAY(-1,15NS,25NS), + CHANGED(CBA,0) & TRN_HL & SBA=='1, DELAY(-1,24NS,40NS), + CHANGED(B8,0) & TRN_LH & SBA!='1, DELAY(-1,12NS,18NS), + CHANGED(B8,0) & TRN_HL & SBA!='1, DELAY(-1,15NS,25NS), + CHANGED(SBA,0) & B8!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SBA,0) & B8!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SBA,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SBA,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + TRISTATE: + ENABLE HI ENB + B1_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A1,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A1,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A1!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A1!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B2_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A2,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A2,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A2!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A2!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B3_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A3,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A3,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A3!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A3!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B4_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A4,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A4,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A4!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A4!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B5_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A5,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A5,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A5!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A5!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B6_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A6,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A6,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A6!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A6!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B7_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A7,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A7,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A7!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A7!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + B8_B = { + CASE( + CHANGED(CAB,0) & TRN_LH & SAB=='1, DELAY(-1,15NS,25NS), + CHANGED(CAB,0) & TRN_HL & SAB=='1, DELAY(-1,24NS,40NS), + CHANGED(A8,0) & TRN_LH & SAB!='1, DELAY(-1,12NS,18NS), + CHANGED(A8,0) & TRN_HL & SAB!='1, DELAY(-1,15NS,25NS), + CHANGED(SAB,0) & A8!='0 & TRN_LH, DELAY(-1,37NS,55NS), + CHANGED(SAB,0) & A8!='0 & TRN_HL, DELAY(-1,24NS,40NS), + CHANGED(SAB,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(SAB,0) & TRN_HL, DELAY(-1,23NS,40NS), + CHANGED(GBAR,0) & TRN_ZH, DELAY(-1,30NS,50NS), + CHANGED(GBAR,0) & TRN_ZL, DELAY(-1,37NS,55NS), + CHANGED(GBAR,0) & TRN_HZ, DELAY(-1,28NS,45NS), + CHANGED(GBAR,0) & TRN_LZ, DELAY(-1,22NS,35NS), + CHANGED(DIR,0) & TRN_ZH, DELAY(-1,23NS,40NS), + CHANGED(DIR,0) & TRN_ZL, DELAY(-1,30NS,45NS), + CHANGED(DIR,0) & TRN_HZ, DELAY(-1,24NS,35NS), + CHANGED(DIR,0) & TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,38NS,56NS) + ) + } + WIDTH: + NODE = CAB + MIN_HI = 15NS + MIN_LO = 30NS + WIDTH: + NODE = CBA + MIN_HI = 15NS + MIN_LO = 30NS + WIDTH: + NODE = A1 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A2 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A3 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A4 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A5 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A6 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A7 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = A8 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='0 } + WIDTH: + NODE = B1 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B2 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B3 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B4 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B5 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B6 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B7 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + WIDTH: + NODE = B8 + MIN_HI = 30NS + MIN_LO = 30NS + WHEN = { DIR!='1 } + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 15NS + WHEN = { DIR!='0 } + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 15NS + WHEN = { DIR!='1 } * .ENDS *--------- * 74LS651 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH INVERTED 3-STATE OUTPUTS * * THE TTL DATA BOOK, 1988, TI * JSW 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74LS651 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I A1_B A2_B A3_B A4_B + A5_B A6_B A7_B A8_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS * U3 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS * U4 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS * U5 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS * U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS * ULS651LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I A1_B A2_B A3_B A4_B A5_B A6_B + A7_B A8_B B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B QA1 QA2 QA3 + QA4 QA5 QA6 QA7 QA8 QB1 QB2 QB3 QB4 QB5 + QB6 QB7 QB8 + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O B1_O B2_O B3_O B4_O B5_O B6_O + B7_O B8_O IGAB IGBABAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) } + A8_O = { ~((SBA & QA8) | (ISBA & B8)) } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } + B8_O = { ~((SAB & QB8) | (ISAB & A8)) } * ULS651DLY PINDLY (16,2,22) DPWR DGND + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GBABAR GAB + CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_BA = { CHANGED(SBA,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE LO GBABAR + A1_B = { + CASE( + CHANGED(B1,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B1,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B1=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B1=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B1=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B1=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A2_B = { + CASE( + CHANGED(B2,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B2,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B2=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B2=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B2=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B2=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A3_B = { + CASE( + CHANGED(B3,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B3,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B3=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B3=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B3=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B3=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A4_B = { + CASE( + CHANGED(B4,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B4,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B4=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B4=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B4=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B4=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A5_B = { + CASE( + CHANGED(B5,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B5,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B5=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B5=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B5=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B5=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A6_B = { + CASE( + CHANGED(B6,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B6,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B6=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B6=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B6=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B6=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A7_B = { + CASE( + CHANGED(B7,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B7,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B7=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B7=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B7=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B7=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + A8_B = { + CASE( + CHANGED(B8,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(B8,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_BA & B8=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_BA & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_BA & B8=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_BA & B8=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_BA & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,29NS,44NS), + SEL_BA & B8=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,40NS,60NS), + DELAY(-1,41NS,61NS) + ) + } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + CHANGED(A1,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A1,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A1=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B2_B = { + CASE( + CHANGED(A2,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A2,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A2=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B3_B = { + CASE( + CHANGED(A3,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A3,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A3=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A3=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B4_B = { + CASE( + CHANGED(A4,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A4,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A4=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B5_B = { + CASE( + CHANGED(A5,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A5,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A5=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B6_B = { + CASE( + CHANGED(A6,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A6,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A6=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B7_B = { + CASE( + CHANGED(A7,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A7,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A7=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + B8_B = { + CASE( + CHANGED(A8,0) & TRN_LH, DELAY(-1,9NS,18NS), + CHANGED(A8,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(-1,19NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,24NS), + TRN_LZ, DELAY(-1,19NS,30NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(-1,31NS,47NS), + CLOCK_AB & TRN_HL, DELAY(-1,23NS,35NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_ZH, DELAY(-1,19NS,29NS), + SEL_AB & A8=='0 & TRN_LH, DELAY(-1,23NS,35NS), + TRN_ZL, DELAY(-1,26NS,40NS), + DELAY(-1,32NS,48NS) + ) + } + WIDTH: + NODE = CBA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CAB + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A1 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A2 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A3 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A4 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A5 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A6 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A7 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A8 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B1 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B2 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B3 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B4 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B5 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B6 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B7 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B8 + MIN_LO = 15NS + MIN_HI = 15NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 15NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 15NS * .ENDS * *$ *--------- * 74LS652 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH 3-STATE OUTPUTS * * THE TTL DATA BOOK, 1988, TI * TC 09/04/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC WAS ADDED TO MODEL THE BIDIRECTIONAL PINS OF THIS * DEVICE. * .SUBCKT 74LS652 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + D0_EFF IO_LS * U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + D0_EFF IO_LS * U3 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS * U4 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS * U5 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS * U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS * ULS652LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) } + A8_O = { ~((SBA & QA8BAR) | (ISBA & ~B8)) } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } + B8_O = { ~((SAB & QB8BAR) | (ISAB & ~A8)) } * ULS652DLY PINDLY (16,2,22) DPWR DGND + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GBABAR GAB + CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_BA = { CHANGED(SBA,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE LO GBABAR + A1_B = { + CASE( + SEL_BA & B1=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B1=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B1=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B1=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B1,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B1,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A2_B = { + CASE( + SEL_BA & B2=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B2=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B2=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B2=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B2,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B2,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A3_B = { + CASE( + SEL_BA & B3=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B3=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B3=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B3=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B3,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B3,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A4_B = { + CASE( + SEL_BA & B4=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B4=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B4=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B4=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B4,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B4,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A5_B = { + CASE( + SEL_BA & B5=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B5=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B5=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B5=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B5,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B5,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A6_B = { + CASE( + SEL_BA & B6=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B6=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B6=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B6=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B6,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B6,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A7_B = { + CASE( + SEL_BA & B7=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B7=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B7=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B7=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B7,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B7,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + A8_B = { + CASE( + SEL_BA & B8=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + SEL_BA & B8=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B8=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_BA & TRN_LH, DELAY(-1,15NS,25NS), + SEL_BA & B8=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(B8,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(B8,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,30NS,45NS), + TRN_ZL, DELAY(-1,36NS,54NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,37NS,55NS) + ) + } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + SEL_AB & A1=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A1,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A1,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B2_B = { + CASE( + SEL_AB & A2=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A2,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A2,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B3_B = { + CASE( + SEL_AB & A3=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A3=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A3,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A3,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B4_B = { + CASE( + SEL_AB & A4=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A4,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A4,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B5_B = { + CASE( + SEL_AB & A5=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A5,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A5,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B6_B = { + CASE( + SEL_AB & A6=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A6,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A6,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B7_B = { + CASE( + SEL_AB & A7=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A7,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A7,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + B8_B = { + CASE( + SEL_AB & A8=='0 & TRN_LH, DELAY(-1,33NS,50NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(-1,23NS,35NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(-1,21NS,32NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,25NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(-1,15NS,23NS), + CHANGED(A8,0) & TRN_HL, DELAY(-1,13NS,20NS), + CHANGED(A8,0) & TRN_LH, DELAY(-1,12NS,18NS), + TRN_ZH, DELAY(-1,20NS,30NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,25NS,38NS), + TRN_LZ, DELAY(-1,19NS,30NS), + DELAY(-1,34NS,51NS) + ) + } + WIDTH: + NODE = CBA + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = CAB + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A1 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A2 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A3 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A4 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A5 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A6 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A7 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = A8 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B1 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B2 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B3 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B4 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B5 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B6 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B7 + MIN_LO = 15NS + MIN_HI = 15NS + WIDTH: + NODE = B8 + MIN_LO = 15NS + MIN_HI = 15NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 15NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 15NS * .ENDS * *$ *--------- * 74LS653 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH OPEN-COLLECTOR OUTPUTS * * THE TTL DATA BOOK, 1988, TI * TC 09/08/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC IS ADDED TO MODEL THE BIDIRECTIONAL PINS AND THE * FUNCTION OF GBABAR IN CONTROLLING THE OPEN-COLLECTOR A BUS. .SUBCKT 74LS653 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + D0_EFF IO_LS U3 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS U4 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS U5 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS ULS653LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 + GBABAR GAB CBA SBA CAB SAB + A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1) | (ISBA & B1)) | GBABAR } + A2_O = { ~((SBA & QA2) | (ISBA & B2)) | GBABAR } + A3_O = { ~((SBA & QA3) | (ISBA & B3)) | GBABAR } + A4_O = { ~((SBA & QA4) | (ISBA & B4)) | GBABAR } + A5_O = { ~((SBA & QA5) | (ISBA & B5)) | GBABAR } + A6_O = { ~((SBA & QA6) | (ISBA & B6)) | GBABAR } + A7_O = { ~((SBA & QA7) | (ISBA & B7)) | GBABAR } + A8_O = { ~((SBA & QA8) | (ISBA & B8)) | GBABAR } + B1_O = { ~((SAB & QB1) | (ISAB & A1)) } + B2_O = { ~((SAB & QB2) | (ISAB & A2)) } + B3_O = { ~((SAB & QB3) | (ISAB & A3)) } + B4_O = { ~((SAB & QB4) | (ISAB & A4)) } + B5_O = { ~((SAB & QB5) | (ISAB & A5)) } + B6_O = { ~((SAB & QB6) | (ISAB & A6)) } + B7_O = { ~((SAB & QB7) | (ISAB & A7)) } + B8_O = { ~((SAB & QB8) | (ISAB & A8)) } ULS653DLY_1 PINDLY(8,0,11) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBABAR CBA SBA B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + ENABLE = { CHANGED(GBABAR,0) } + SEL_BA = { CHANGED(SBA,0) } + PINDLY: + A1_B = { + CASE( + SEL_BA & B1=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B1=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B1=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B1=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B1,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B1,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A2_B = { + CASE( + SEL_BA & B2=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B2=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B2=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B2=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B2,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B2,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A3_B = { + CASE( + SEL_BA & B3=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B3=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B3=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B3=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B3,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B3,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A4_B = { + CASE( + SEL_BA & B4=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B4=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B4=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B4=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B4,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B4,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A5_B = { + CASE( + SEL_BA & B5=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B5=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B5=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B5=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B5,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B5,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A6_B = { + CASE( + SEL_BA & B6=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B6=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B6=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B6=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B6,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B6,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A7_B = { + CASE( + SEL_BA & B7=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B7=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B7=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B7=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B7,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B7,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } + A8_B = { + CASE( + SEL_BA & B8=='1 & TRN_LH, DELAY(-1,38NS,57NS), + ENABLE & TRN_HL, DELAY(-1,37NS,55NS), + SEL_BA & B8=='0 & TRN_LH, DELAY(-1,34NS,51NS), + SEL_BA & B8=='1 & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_HL, DELAY(-1,26NS,39NS), + CLOCK_BA & TRN_LH, DELAY(-1,25NS,38NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + SEL_BA & B8=='0 & TRN_HL, DELAY(-1,23NS,35NS), + CHANGED(B8,0) & TRN_LH, DELAY(-1,21NS,32NS), + CHANGED(B8,0) & TRN_HL, DELAY(-1,16NS,24NS), + DELAY(-1,39NS,58NS) + ) + } ULS653DLY_2 PINDLY(8,1,10) DPWR DGND + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GAB + CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + SEL_AB & A1=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A1=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A1,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A1,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B2_B = { + CASE( + SEL_AB & A2=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A2=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A2,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A2,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B3_B = { + CASE( + SEL_AB & A3=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A3=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A3,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A3,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B4_B = { + CASE( + SEL_AB & A4=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A4=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A4,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A4,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B5_B = { + CASE( + SEL_AB & A5=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A5=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A5,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A5,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B6_B = { + CASE( + SEL_AB & A6=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A6=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A6,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A6,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B7_B = { + CASE( + SEL_AB & A7=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A7=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A7,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A7,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } + B8_B = { + CASE( + SEL_AB & A8=='1 & TRN_LH, DELAY(-1,32NS,48NS), + SEL_AB & A8=='0 & TRN_LH, DELAY(-1,24NS,36NS), + CLOCK_AB & TRN_HL, DELAY(-1,24NS,36NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(-1,22NS,33NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(-1,20NS,30NS), + CHANGED(A8,0) & TRN_HL, DELAY(-1,20NS,30NS), + CLOCK_AB & TRN_LH, DELAY(-1,15NS,23NS), + CHANGED(A8,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,25NS,38NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,33NS,49NS) + ) + } ULS653CON CONSTRAINT(18) DPWR DGND + CAB CBA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + IO_LS + WIDTH: + NODE = CAB + MIN_LO = 30NS + MIN_HI = 15NS + WIDTH: + NODE = CBA + MIN_LO = 30NS + MIN_HI = 15NS + WIDTH: + NODE = A1 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A2 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A3 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A4 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A5 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A6 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A7 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A8 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B1 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B2 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B3 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B4 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B5 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B6 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B7 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B8 + MIN_LO = 30NS + MIN_HI = 30NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 15NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 15NS .ENDS *$ *--------- * 74LS654 BUS TRANSCEIVERS AND REGISTERS OCTAL WITH OPEN-COLLECTOR OUTPUTS * * THE TTL DATA BOOK, VOL 2, 1985, TI * TC 09/10/92 REMODELED USING LOGICEXP, PINDLY, & CONSTRAINT DEVICES * * NOTE: ADDITIONAL LOGIC IS ADDED TO MODEL THE BIDIRECTIONAL PINS AND THE * FUNCTION OF GBABAR IN CONTROLLING THE OPEN-COLLECTOR A BUS. .SUBCKT 74LS654 GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 U1 DFF(8) DPWR DGND $D_HI $D_HI CAB + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + D0_EFF IO_LS U2 DFF(8) DPWR DGND $D_HI $D_HI CBA + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC $D_NC + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + D0_EFF IO_LS U3 BUF3A(8) DPWR DGND + A1 A2 A3 A4 A5 A6 A7 A8 GBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS U4 BUF3A(8) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O IGBABAR + A1_IO A2_IO A3_IO A4_IO A5_IO A6_IO A7_IO A8_IO + D0_TGATE IO_LS U5 BUF3A(8) DPWR DGND + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O GAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS U6 BUF3A(8) DPWR DGND + B1 B2 B3 B4 B5 B6 B7 B8 IGAB + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + D0_TGATE IO_LS ULS654LOG LOGICEXP(38,40) DPWR DGND + GBABAR_I GAB_I CBA_I SBA_I CAB_I SAB_I + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + QA1BAR QA2BAR QA3BAR QA4BAR QA5BAR QA6BAR QA7BAR QA8BAR + QB1BAR QB2BAR QB3BAR QB4BAR QB5BAR QB6BAR QB7BAR QB8BAR + GBABAR GAB CBA SBA CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + B1_O B2_O B3_O B4_O B5_O B6_O B7_O B8_O IGAB IGBABAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBABAR = { GBABAR_I } + GAB = { GAB_I } + CBA = { CBA_I } + SBA = { SBA_I } + CAB = { CAB_I } + SAB = { SAB_I } + A1 = { A1_B } + A2 = { A2_B } + A3 = { A3_B } + A4 = { A4_B } + A5 = { A5_B } + A6 = { A6_B } + A7 = { A7_B } + A8 = { A8_B } + B1 = { B1_B } + B2 = { B2_B } + B3 = { B3_B } + B4 = { B4_B } + B5 = { B5_B } + B6 = { B6_B } + B7 = { B7_B } + B8 = { B8_B } + ISAB = { ~SAB } + ISBA = { ~SBA } + IGAB = { ~GAB } + IGBABAR = { ~GBABAR } + A1_O = { ~((SBA & QA1BAR) | (ISBA & ~B1)) | GBABAR } + A2_O = { ~((SBA & QA2BAR) | (ISBA & ~B2)) | GBABAR } + A3_O = { ~((SBA & QA3BAR) | (ISBA & ~B3)) | GBABAR } + A4_O = { ~((SBA & QA4BAR) | (ISBA & ~B4)) | GBABAR } + A5_O = { ~((SBA & QA5BAR) | (ISBA & ~B5)) | GBABAR } + A6_O = { ~((SBA & QA6BAR) | (ISBA & ~B6)) | GBABAR } + A7_O = { ~((SBA & QA7BAR) | (ISBA & ~B7)) | GBABAR } + A8_O = { ~((SBA & QA8BAR) | (ISBA & ~B8)) | GBABAR } + B1_O = { ~((SAB & QB1BAR) | (ISAB & ~A1)) } + B2_O = { ~((SAB & QB2BAR) | (ISAB & ~A2)) } + B3_O = { ~((SAB & QB3BAR) | (ISAB & ~A3)) } + B4_O = { ~((SAB & QB4BAR) | (ISAB & ~A4)) } + B5_O = { ~((SAB & QB5BAR) | (ISAB & ~A5)) } + B6_O = { ~((SAB & QB6BAR) | (ISAB & ~A6)) } + B7_O = { ~((SAB & QB7BAR) | (ISAB & ~A7)) } + B8_O = { ~((SAB & QB8BAR) | (ISAB & ~A8)) } ULS654DLY_1 PINDLY(8,0,11) DPWR DGND + A1_O A2_O A3_O A4_O A5_O A6_O A7_O A8_O + GBABAR CBA SBA B1 B2 B3 B4 B5 B6 B7 B8 + A1_B A2_B A3_B A4_B A5_B A6_B A7_B A8_B + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_BA = { CHANGED_LH(CBA,0) } + ENABLE = { CHANGED(GBABAR,0) } + SEL_BA = { CHANGED(SBA,0) } + PINDLY: + A1_B = { + CASE( + SEL_BA & B1=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B1=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B1=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B1=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B1,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B1,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A2_B = { + CASE( + SEL_BA & B2=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B2=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B2=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B2=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B2,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B2,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A3_B = { + CASE( + SEL_BA & B3=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B3=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B3=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B3=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B3,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B3,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A4_B = { + CASE( + SEL_BA & B4=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B4=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B4=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B4=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B4,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B4,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A5_B = { + CASE( + SEL_BA & B5=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B5=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B5=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B5=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B5,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B5,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A6_B = { + CASE( + SEL_BA & B6=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B6=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B6=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B6=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B6,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B6,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A7_B = { + CASE( + SEL_BA & B7=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B7=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B7=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B7=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B7,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B7,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } + A8_B = { + CASE( + SEL_BA & B8=='0 & TRN_LH, DELAY(-1,36NS,54NS), + ENABLE & TRN_HL, DELAY(-1,35NS,53NS), + SEL_BA & B8=='1 & TRN_LH, DELAY(-1,32NS,48NS), + CLOCK_BA & TRN_HL, DELAY(-1,24NS,36NS), + ENABLE & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_BA & TRN_LH, DELAY(-1,22NS,33NS), + SEL_BA & B8=='1 & TRN_HL, DELAY(-1,21NS,32NS), + SEL_BA & B8=='0 & TRN_HL, DELAY(-1,19NS,29NS), + CHANGED(B8,0) & TRN_LH, DELAY(-1,18NS,27NS), + CHANGED(B8,0) & TRN_HL, DELAY(-1,14NS,21NS), + DELAY(-1,37NS,55NS) + ) + } ULS654DLY_2 PINDLY(8,1,10) DPWR DGND + B1_IO B2_IO B3_IO B4_IO B5_IO B6_IO B7_IO B8_IO + GAB + CAB SAB A1 A2 A3 A4 A5 A6 A7 A8 + B1_B B2_B B3_B B4_B B5_B B6_B B7_B B8_B + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK_AB = { CHANGED_LH(CAB,0) } + SEL_AB = { CHANGED(SAB,0) } + TRISTATE: + ENABLE HI GAB + B1_B = { + CASE( + SEL_AB & A1=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A1=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A1,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A1=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A1=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A1,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B2_B = { + CASE( + SEL_AB & A2=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A2=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A2,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A2=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A2=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A2,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B3_B = { + CASE( + SEL_AB & A3=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A3=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A3,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A3=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A3=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A3,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B4_B = { + CASE( + SEL_AB & A4=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A4=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A4,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A4=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A4=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A4,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B5_B = { + CASE( + SEL_AB & A5=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A5=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A5,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A5=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A5=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A5,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B6_B = { + CASE( + SEL_AB & A6=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A6=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A6,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A6=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A6=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A6,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B7_B = { + CASE( + SEL_AB & A7=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A7=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A7,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A7=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A7=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A7,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } + B8_B = { + CASE( + SEL_AB & A8=='0 & TRN_LH, DELAY(-1,30NS,45NS), + SEL_AB & A8=='1 & TRN_LH, DELAY(-1,23NS,35NS), + CLOCK_AB & TRN_HL, DELAY(-1,22NS,33NS), + CHANGED(A8,0) & TRN_HL, DELAY(-1,20NS,30NS), + SEL_AB & A8=='1 & TRN_HL, DELAY(-1,18NS,27NS), + SEL_AB & A8=='0 & TRN_HL, DELAY(-1,14NS,21NS), + CLOCK_AB & TRN_LH, DELAY(-1,14NS,21NS), + CHANGED(A8,0) & TRN_LH, DELAY(-1,10NS,18NS), + TRN_ZH, DELAY(-1,19NS,29NS), + TRN_ZL, DELAY(-1,22NS,33NS), + TRN_HZ, DELAY(-1,26NS,39NS), + TRN_LZ, DELAY(-1,19NS,29NS), + DELAY(-1,31NS,46NS) + ) + } ULS654CON CONSTRAINT(18) DPWR DGND + CAB CBA A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 + IO_LS + WIDTH: + NODE = CAB + MIN_LO = 30NS + MIN_HI = 15NS + WIDTH: + NODE = CBA + MIN_LO = 30NS + MIN_HI = 15NS + WIDTH: + NODE = A1 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A2 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A3 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A4 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A5 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A6 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A7 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = A8 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B1 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B2 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B3 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B4 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B5 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B6 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B7 + MIN_LO = 30NS + MIN_HI = 30NS + WIDTH: + NODE = B8 + MIN_LO = 30NS + MIN_HI = 30NS + SETUP_HOLD: + DATA(8) = A1 A2 A3 A4 A5 A6 A7 A8 + CLOCK LH = CAB + SETUPTIME = 15NS + SETUP_HOLD: + DATA(8) = B1 B2 B3 B4 B5 B6 B7 B8 + CLOCK LH = CBA + SETUPTIME = 15NS .ENDS *$ *--------------------------------------------------------------------------- * 74LS668 Synchronous 4-bit Decade Counters * * The LS Data Book, 1988, TI * JSW 7/1/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS668 CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS668LOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA QB QC QD QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D RCOBAR DA DB DC DD IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } ;Buffering + U/DBAR = { U/DBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + ENP = { ~ENPBAR } + ENT = { ~ENTBAR } + LOADBAR = { LOADBAR_I } + UD = { ~U/DBAR } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + LOAD = { ~LOADBAR } ;Logic expressions + IEN = { ENP & ENT & LOADBAR } + IA1 = { ~((UD & QA) | (U/DBAR & QABAR)) } + IB1 = { ~((UD & QB) | (U/DBAR & QBBAR)) } + IC1 = { ~((UD & QC) | (U/DBAR & QCBAR)) } + ID1 = { ~((UD & QD) | (U/DBAR & QDBAR)) } + IB2 = { ~(ID1 & U/DBAR) } + IB3 = { ~(UD & IA1 & IB1 & IC1 & ID1) } + DA = { (QA & ~IEN & LOADBAR) | (IEN & QABAR) | (A & LOAD) } + DB = { (~(IEN & IA1) & LOADBAR & QB) | + (IA1 & IEN & IB2 & IB3 & QBBAR) | (B & LOAD) } + DC = { (~(IEN & IA1 & IB1) & LOADBAR & QC) | + (IEN & IB3 & IA1 & IB1 & QCBAR) | (C & LOAD) } + DD = { (~(IEN & IA1) & LOADBAR & QD) | + (IEN & IA1 & IB1 & IC1 & QDBAR) | (D & LOAD) } + RCOBAR = { ~((ID1 & IA1 & U/DBAR & ENT) | ( ID1 & IC1 & IB1 & IA1 & + UD & ENT)) } * UDFF DFF(4) DPWR DGND $D_HI $D_HI CLK DA DB DC DD + QA QB QC QD QABAR QBBAR QCBAR QDBAR D0_EFF IO_LS * ULS668DLY PINDLY (5,0,10) DPWR DGND + RCOBAR QA QB QC QD + CLK U/DBAR ENTBAR ENPBAR LOADBAR A B C D IEN + RCOBAR_O QA_O QB_O QC_O QD_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + CNTENT = { CHANGED(ENTBAR,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { DELAY(-1,18NS,27NS) } + RCOBAR_O = { + CASE( + CNTENT & TRN_LH, DELAY(-1,11NS,17NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(-1,22NS,35NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(-1,26NS,40NS), + CLOCK & TRN_LH, DELAY(-1,26NS,40NS), + CNTENT & TRN_HL, DELAY(-1,29NS,45NS), + CLOCK & TRN_HL, DELAY(-1,40NS,60NS), + DELAY(-1,40NS,60NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 30NS + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 40NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CHANGED(IEN,40NS) } + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 45NS + WHEN = { IEN!='0 ^ CHANGED(IEN,0) } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS669 Synchronous 4-Bit Up/Down Binary Counter * * THE TTL LOGIC DATA BOOK, 1988, TI * tc 07/20/92 Remodeled using LOGICEXP, PINDLY, & CONSTRAINT devices * .SUBCKT 74LS669 CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CLK + DA DB DC DD QA QB QC QD QABAR QBBAR QCBAR QDBAR + D0_EFF IO_LS * ULS699LOG LOGICEXP(17,15) DPWR DGND + CLK_I U/DBAR_I ENPBAR_I ENTBAR_I LOADBAR_I A_I B_I C_I D_I QA QB QC QD + QABAR QBBAR QCBAR QDBAR + CLK U/DBAR ENPBAR ENTBAR LOADBAR A B C D DA DB DC DD RCOBAR IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + CLK = { CLK_I } + U/DBAR = { U/DBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + LOADBAR = { LOADBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + ILD = { ~LOADBAR } + IEN = { LOADBAR & ~ENPBAR & ~ENTBAR } + IUD1 = { ~U/DBAR } + IUD2 = { ~((QA & IUD1) | (U/DBAR & QABAR)) } + IUD3 = { ~((QB & IUD1) | (U/DBAR & QBBAR)) } + IUD4 = { ~((QC & IUD1) | (U/DBAR & QCBAR)) } + IUD5 = { ~((QD & IUD1) | (U/DBAR & QDBAR)) } + IA1 = { QA & ~IEN & LOADBAR } + IA2 = { IEN & QABAR } + IB1 = { QB & LOADBAR & ~(IEN & IUD2) } + IB2 = { IUD2 & IEN & QBBAR } + IC1 = { QC & LOADBAR & ~(IEN & IUD2 & IUD3) } + IC2 = { IEN & IUD3 & IUD2 & QCBAR } + ID1 = { QD & LOADBAR & ~(IEN & IUD2 & IUD3 & IUD4) } + ID2 = { IEN & IUD4 & IUD3 & IUD2 & QDBAR } + DA = { IA1 | IA2 | (ILD & A) } + DB = { IB1 | IB2 | (ILD & B) } + DC = { IC1 | IC2 | (ILD & C) } + DD = { ID1 | ID2 | (ILD & D) } + RCOBAR = { ~(IUD5 & IUD4 & IUD3 & IUD2 & ~ENTBAR) } * ULS669DLY PINDLY (5,0,10) DPWR DGND + QA QB QC QD RCOBAR + CLK ENTBAR U/DBAR A B C D ENPBAR LOADBAR IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CLOCK = { CHANGED_LH(CLK,0) } + PINDLY: + QA_O QB_O QC_O QD_O = { DELAY(-1,18NS,27NS) } + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0) & TRN_LH, DELAY(-1,11NS,17NS), + CHANGED(U/DBAR,0) & TRN_LH, DELAY(-1,22NS,35NS), + CHANGED(U/DBAR,0) & TRN_HL, DELAY(-1,26NS,40NS), + CHANGED_LH(CLK,0) & TRN_LH, DELAY(-1,26NS,40NS), + CHANGED(ENTBAR,0) & TRN_HL, DELAY(-1,29NS,45NS), + CHANGED_LH(CLK,0) & TRN_HL, DELAY(-1,40NS,60NS), + DELAY(-1,40NS,60NS) + ) + } + FREQ: + NODE = CLK + MAXFREQ = 25MEG + WIDTH: + NODE = CLK + MIN_LO = 20NS + MIN_HI = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CLK + SETUPTIME = 25NS + WHEN = { LOADBAR!='1 ^ CHANGED(LOADBAR,0) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CLK + SETUPTIME = 40NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CHANGED(IEN,40NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CLK + SETUPTIME = 30NS + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CLK + SETUPTIME = 45NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } * .ENDS * *$ *--------- * 74LS670 REGISTER FILES 4X4 WITH 3-STATE OUTPUTS * * TTL LOGIC STANDARD TTL, S, LS DATA BOOK, APR 1988, TI * JLS 7-14-92 REMODELED USING LOGICEXP, PINDLY, AND CONSTRAINT DEVICES * .SUBCKT 74LS670 GWBAR_I GRBAR_I WA_I WB_I RA_I RB_I D1_I D2_I D3_I D4_I + Q1_O Q2_O Q3_O Q4_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * UA DLTCH(4) DPWR DGND + $D_HI $D_HI GATEA + D1 D2 D3 D4 + AQ1 AQ2 AQ3 AQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS UB DLTCH(4) DPWR DGND + $D_HI $D_HI GATEB + D1 D2 D3 D4 + BQ1 BQ2 BQ3 BQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS UC DLTCH(4) DPWR DGND + $D_HI $D_HI GATEC + D1 D2 D3 D4 + CQ1 CQ2 CQ3 CQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS UD DLTCH(4) DPWR DGND + $D_HI $D_HI GATED + D1 D2 D3 D4 + DQ1 DQ2 DQ3 DQ4 + $D_NC $D_NC $D_NC $D_NC + D0_GFF IO_LS * ULS670LOG LOGICEXP (26,18) DPWR DGND + GWBAR_I GRBAR_I WA_I WB_I RA_I RB_I D1_I D2_I D3_I D4_I + AQ1 AQ2 AQ3 AQ4 BQ1 BQ2 BQ3 BQ4 CQ1 CQ2 CQ3 CQ4 DQ1 DQ2 DQ3 DQ4 + GWBAR GRBAR WA WB RA RB D1 D2 D3 D4 + GATEA GATEB GATEC GATED Q1 Q2 Q3 Q4 + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + + LOGIC: + GWBAR = { GWBAR_I } + GRBAR = { GRBAR_I } + WA = { WA_I } + WB = { WB_I } + RA = { RA_I } + RB = { RB_I } + D1 = { D1_I } + D2 = { D2_I } + D3 = { D3_I } + D4 = { D4_I } + ENABLE2 = { ~(GWBAR | WB) } + ENABLE1 = { ~(GWBAR | ENABLE2) } + GATEA = { ENABLE2 & ~WA } + GATEB = { ENABLE2 & WA } + GATEC = { ENABLE1 & ~WA } + GATED = { ENABLE1 & WA } + Q1 = { (AQ1 & ~RA & ~RB) | + (BQ1 & RA & ~RB) | + (CQ1 & ~RA & RB) | + (DQ1 & RA & RB) + } + Q2 = { (AQ2 & ~RA & ~RB) | + (BQ2 & RA & ~RB) | + (CQ2 & ~RA & RB) | + (DQ2 & RA & RB) + } + Q3 = { (AQ3 & ~RA & ~RB) | + (BQ3 & RA & ~RB) | + (CQ3 & ~RA & RB) | + (DQ3 & RA & RB) + } + Q4 = { (AQ4 & ~RA & ~RB) | + (BQ4 & RA & ~RB) | + (CQ4 & ~RA & RB) | + (DQ4 & RA & RB) + } * ULS670DLY PINDLY (4,1,9) DPWR DGND + Q1 Q2 Q3 Q4 + GRBAR + GWBAR RA RB D1 D2 D3 D4 WA WB + Q1_O Q2_O Q3_O Q4_O + IO_LS + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + WRITEEN = { CHANGED(GWBAR,0) } + READ = { CHANGED(RA,0) | CHANGED(RB,0) } + DATA = { CHANGED(D1,0) | CHANGED(D2,0) | + CHANGED(D3,0) | CHANGED(D4,0) } + + TRISTATE: + ENABLE LO GRBAR + Q1_O Q2_O Q3_O Q4_O = { + CASE ( + TRN_ZH, DELAY(-1,15NS,35NS), + TRN_ZL, DELAY(-1,22NS,40NS), + TRN_HZ, DELAY(-1,30NS,50NS), + TRN_LZ, DELAY(-1,16NS,35NS), + DATA & TRN_HL, DELAY(-1,23NS,40NS), + READ & TRN_LH, DELAY(-1,23NS,40NS), + DATA & TRN_LH, DELAY(-1,25NS,45NS), + READ & TRN_HL, DELAY(-1,25NS,45NS), + WRITEEN & TRN_LH, DELAY(-1,26NS,45NS), + WRITEEN & TRN_HL, DELAY(-1,28NS,50NS), + DELAY(-1,28NS,50NS) + ) + } + + WIDTH: + NODE = GWBAR + MIN_LO = 25NS + WIDTH: + NODE = GRBAR + MIN_LO = 25NS + SETUP_HOLD: + DATA(4) = D1 D2 D3 D4 + CLOCK LH = GWBAR + SETUPTIME = 10NS + HOLDTIME = 15NS + SETUP_HOLD: + DATA(2) = WA WB + CLOCK HL = GWBAR + SETUPTIME = 15NS + HOLDTIME = .1NS ;WA,WB MUST BE STABLE WHILE GWBAR IS LOW + SETUP_HOLD: + DATA(2) = WA WB + CLOCK LH = GWBAR + SETUPTIME = .1NS ;WA,WB MUST BE STABLE WHILE GWBAR IS LOW + HOLDTIME = 5NS + GENERAL: + WHEN = { GWBAR!='1 & (CHANGED(WA,0NS) | CHANGED(WB,0NS)) } + MESSAGE = "WA AND WB MUST BE STABLE WHILE GWBAR IS LOW" * .ENDS * *$ *------------------------------------------------------------------------- * 74LS671 4-BIT SHIFT REGISTERS/LATCHES WITH 3-STATE OUTPUTS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 8-10-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS671 GBAR_I R/SBAR_I SRCK_I SRCLRBAR_I RCK_I + S0_I S1_I SERR_I A_I B_I C_I D_I SERL_I + QA_O QB_O QC_O QD_O CASC_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS671LOG LOGICEXP(25,22) DPWR DGND + GBAR_I R/SBAR_I SRCK_I SRCLRBAR_I RCK_I S0_I S1_I SERR_I A_I B_I C_I D_I + SERL_I + Q1A Q1B Q1C Q1D Q1ABAR Q1BBAR Q1CBAR Q1DBAR Q2ABAR Q2BBAR Q2CBAR Q2DBAR + + GBAR R/SBAR SRCK SRCLRBAR RCK + SERR S0 S1 SERL + A B C D + D1A D1B D1C D1D QA QB QC QD CASC + + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: * BUFFERING + R/SBAR = { R/SBAR_I } + S0 = { S0_I } + S1 = { S1_I } + SERR = { SERR_I } + SERL = { SERL_I } + SRCLRBAR = { SRCLRBAR_I } + SRCK = { SRCK_I } + RCK = { RCK_I } + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERMS: + /S1/S0 = { ~S1 & ~S0 } + /S1S0 = { ~S1 & S0 } + S1/S0 = { S1 & ~S0 } + S1S0 = { S1 & S0 } + + D1A = { (S1S0 & A) | (S1/S0 & Q1B ) | (/S1S0 & SERR) | (/S1/S0 & Q1A) } + D1B = { (S1S0 & B) | (S1/S0 & Q1C ) | (/S1S0 & Q1A ) | (/S1/S0 & Q1B) } + D1C = { (S1S0 & C) | (S1/S0 & Q1D ) | (/S1S0 & Q1B ) | (/S1/S0 & Q1C) } + D1D = { (S1S0 & D) | (S1/S0 & SERL) | (/S1S0 & Q1C ) | (/S1/S0 & Q1D) } + * OUTPUT ASSIGNMENT: + QA = { ~((Q2ABAR & R/SBAR) | (Q1ABAR & ~R/SBAR)) } + QB = { ~((Q2BBAR & R/SBAR) | (Q1BBAR & ~R/SBAR)) } + QC = { ~((Q2CBAR & R/SBAR) | (Q1CBAR & ~R/SBAR)) } + QD = { ~((Q2DBAR & R/SBAR) | (Q1DBAR & ~R/SBAR)) } + CASC = { ~((Q1DBAR & /S1S0 ) | (Q1ABAR & S1/S0 )) } * * U1 DFF(4) DPWR DGND $D_HI SRCLRBAR SRCK + D1A D1B D1C D1D + Q1A Q1B Q1C Q1D + Q1ABAR Q1BBAR Q1CBAR Q1DBAR + D0_EFF IO_LS * U2 DFF(4) DPWR DGND $D_HI $D_HI RCK + Q1A Q1B Q1C Q1D + Q2A Q2B Q2C Q2D + Q2ABAR Q2BBAR Q2CBAR Q2DBAR + D0_EFF IO_LS * ULS671DLY PINDLY (5,1,18) DPWR DGND + QA QB QC QD CASC + GBAR + GBAR SRCK SRCLRBAR RCK S1 S0 R/SBAR R/SBAR SERR SERL Q1A Q1B Q1C Q1D A B C D + QA_O QB_O QC_O QD_O CASC_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + SHIFT = { ((S0 != '0) & (S1 != '1)) | ((S0 != '1) & (S1 != '0)) } + LOAD = { (S1 != '0) & (S0 != '0) } + + PINDLY: + CASC_O = { + CASE( + CHANGED(S0,0) | CHANGED(S1,0) & SRCLRBAR!='0, DELAY(-1,11NS,20NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,19NS,30NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_LH, DELAY(-1,31NS,45NS), + DELAY(-1,32NS,46NS) + ) + } + + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + TRN_ZH, DELAY(-1,16NS,25NS), + TRN_ZL, DELAY(-1,19NS,30NS), + TRN_HZ, DELAY(-1,16NS,25NS), + TRN_LZ, DELAY(-1,16NS,25NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_LH, DELAY(-1,10NS,20NS), + CHANGED_LH(SRCK,0) & LOAD & TRN_LH, DELAY(-1,10NS,20NS), + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,10NS,20NS), + CHANGED_LH(R/SBAR,0) & TRN_LH, DELAY(-1,12NS,25NS), + CHANGED_LH(SRCK,0) & LOAD & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED_LH(RCK,0) & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED_LH(R/SBAR,0) & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_HL, DELAY(-1,16NS,25NS), + CHANGED_HL(R/SBAR,0) & TRN_HL, DELAY(-1,16NS,25NS), + CHANGED_HL(R/SBAR,0) & TRN_LH, DELAY(-1,17NS,25NS), + CHANGED_HL(SRCLRBAR,0) & TRN_HL, DELAY(-1,21NS,30NS), + DELAY(-1,22NS,31NS) ;DEFAULT + ) + } + + BOOLEAN: + SH_LEFT = { (S1!='0 ^ CHANGED(S1,0)) & + (S0!='1 ^ CHANGED(S0,0)) } + SH_RIGHT= { (S1!='1 ^ CHANGED(S1,0)) & + (S0!='0 ^ CHANGED(S0,0)) } + LOADING = { (S1!='0 ^ CHANGED(S1,0)) & + (S0!='0 ^ CHANGED(S0,0)) } + WIDTH: + NODE = SRCK + MIN_HI = 30NS + MIN_LO = 30NS + + WIDTH: + NODE = RCK + MIN_HI = 30NS + + WIDTH: + NODE = SRCLRBAR + MIN_LO = 30NS + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + RELEASETIME_LH = 30NS + + SETUP_HOLD: + DATA(2) = S0 S1 + CLOCK LH = SRCK + SETUPTIME = 45NS + WHEN = { SRCLRBAR != '0 } + + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = SRCK + SETUPTIME = 30NS + WHEN = { SRCLRBAR != '0 & LOADING } + + SETUP_HOLD: ;SRCK RISE BEFORE RCK RISE SETUP TIME + DATA(4) = Q1A Q1B Q1C Q1D + CLOCK LH = RCK + SETUPTIME = 30NS + WHEN = { SRCLRBAR != '0 } + MESSAGE = "SETUPTIME VIOLATION OF SRCK BEFORE RCK" + + SETUP_HOLD: + DATA(1) = SERR + CLOCK LH = SRCK + SETUPTIME = 35NS + WHEN = { SRCLRBAR != '0 & SH_RIGHT } + + SETUP_HOLD: + DATA(1) = SERL + CLOCK LH = SRCK + SETUPTIME = 35NS + WHEN = { SRCLRBAR != '0 & SH_LEFT } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS672 4-BIT SHIFT REGISTERS/LATCHES WITH 3-STATE OUTPUTS * * THE TTL DATA BOOK, VOL 2, 1985, TI * KN 8-10-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS672 GBAR_I R/SBAR_I SRCK_I SRCLRBAR_I RCK_I S0_I S1_I + SERR_I A_I B_I C_I D_I SERL_I + QA_O QB_O QC_O QD_O CASC_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS672LOG LOGICEXP(25,22) DPWR DGND + GBAR_I R/SBAR_I SRCK_I SRCLRBAR_I RCK_I S0_I S1_I SERR_I A_I B_I C_I D_I + SERL_I + Q1A Q1B Q1C Q1D Q1ABAR Q1BBAR Q1CBAR Q1DBAR Q2ABAR Q2BBAR Q2CBAR Q2DBAR + + GBAR R/SBAR SRCK SRCLRBAR RCK SERR S0 S1 SERL + A B C D + D1A D1B D1C D1D QA QB QC QD CASC + + D0_GATE IO_LS + IO_LEVEL={IO_LEVEL} + LOGIC: * BUFFERING + R/SBAR = { R/SBAR_I } + S0 = { S0_I } + S1 = { S1_I } + SERR = { SERR_I } + SERL = { SERL_I } + SRCLRBAR = { SRCLRBAR_I } + SRCK = { SRCK_I } + RCK = { RCK_I } + GBAR = { GBAR_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + * INTERMEDIATE TERMS: + /S1/S0 = { ~S1 & ~S0 } + /S1S0 = { ~S1 & S0 } + S1/S0 = { S1 & ~S0 } + S1S0 = { S1 & S0 } + * OUTPUT ASSIGNMENT: + D1A = { (S1S0 & A & SRCLRBAR) | (S1/S0 & Q1B & SRCLRBAR) | + (/S1S0 & SERR & SRCLRBAR) | (/S1/S0 & Q1A & SRCLRBAR) } + D1B = { (S1S0 & B & SRCLRBAR) | (S1/S0 & Q1C & SRCLRBAR) | + (/S1S0 & Q1A & SRCLRBAR) | (/S1/S0 & Q1B & SRCLRBAR) } + D1C = { (S1S0 & C & SRCLRBAR) | (S1/S0 & Q1D & SRCLRBAR) | + (/S1S0 & Q1B & SRCLRBAR) | (/S1/S0 & Q1C & SRCLRBAR) } + D1D = { (S1S0 & D & SRCLRBAR) | (S1/S0 & SERL & SRCLRBAR) | + (/S1S0 & Q1C & SRCLRBAR) | (/S1/S0 & Q1D & SRCLRBAR) } + + QA = { ~((Q2ABAR & R/SBAR) | (Q1ABAR & ~R/SBAR)) } + QB = { ~((Q2BBAR & R/SBAR) | (Q1BBAR & ~R/SBAR)) } + QC = { ~((Q2CBAR & R/SBAR) | (Q1CBAR & ~R/SBAR)) } + QD = { ~((Q2DBAR & R/SBAR) | (Q1DBAR & ~R/SBAR)) } + CASC = { ~((Q1DBAR & /S1S0 ) | (Q1ABAR & S1/S0 )) } * * U1 DFF(4) DPWR DGND $D_HI $D_HI SRCK + D1A D1B D1C D1D + Q1A Q1B Q1C Q1D + Q1ABAR Q1BBAR Q1CBAR Q1DBAR + D0_EFF IO_LS * U2 DFF(4) DPWR DGND $D_HI $D_HI RCK + Q1A Q1B Q1C Q1D + Q2A Q2B Q2C Q2D + Q2ABAR Q2BBAR Q2CBAR Q2DBAR + D0_EFF IO_LS * ULS672DLY PINDLY (5,1,18) DPWR DGND + QA QB QC QD CASC + GBAR + GBAR SRCK SRCLRBAR RCK S1 S0 R/SBAR R/SBAR SERR SERL Q1A Q1B Q1C Q1D A B C D + QA_O QB_O QC_O QD_O CASC_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + SHIFT = { ((S0 != '1) & (S1 != '0)) | ((S0 != '0) & (S1 != '1)) } + LOAD = { (S1 != '0) & (S0 != '0) } + CLEAR = { SRCLRBAR == '0 } + R = { R/SBAR == '1 } + S = { R/SBAR == '0 } + + PINDLY: + CASC_O = { + CASE( + CHANGED(S0,0) | CHANGED(S1,0), DELAY(-1,12NS,20NS), + CHANGED_LH(SRCK,0) & SHIFT & ~CLEAR & TRN_HL, DELAY(-1,14NS,25NS), + CHANGED_LH(SRCK,0) & CLEAR & TRN_HL, DELAY(-1,19NS,30NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_LH, DELAY(-1,31NS,45NS), + DELAY(-1,32NS,46NS) + ) + } + + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + TRN_ZH, DELAY(-1,16NS,25NS), + TRN_ZL, DELAY(-1,19NS,30NS), + TRN_HZ, DELAY(-1,16NS,25NS), + TRN_LZ, DELAY(-1,16NS,25NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_LH, DELAY(-1,10NS,20NS), + CHANGED_LH(SRCK,0) & LOAD & TRN_LH, DELAY(-1,10NS,20NS), + CHANGED_LH(RCK,0) & TRN_LH, DELAY(-1,10NS,20NS), + CHANGED_LH(R/SBAR,0) & TRN_LH, DELAY(-1,13NS,25NS), + CHANGED_LH(SRCK,0) & LOAD & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED_LH(RCK,0) & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED_LH(R/SBAR,0) & TRN_HL, DELAY(-1,15NS,25NS), + CHANGED_LH(SRCK,0) & SHIFT & TRN_HL, DELAY(-1,16NS,25NS), + CHANGED_HL(R/SBAR,0) & TRN_HL, DELAY(-1,16NS,25NS), + CHANGED_HL(R/SBAR,0) & TRN_LH, DELAY(-1,17NS,25NS), + CHANGED_LH(SRCK,0) & CLEAR & TRN_HL, DELAY(-1,17NS,30NS), + DELAY(-1,20NS,31NS) ;DEFAULT + ) + } + + BOOLEAN: + NOT_CLEARING = { (SRCLRBAR!='0 ^ CHANGED(SRCLRBAR,0)) } + SH_LEFT = { (S1!='0 ^ CHANGED(S1,0)) & + (S0!='1 ^ CHANGED(S0,0)) } + SH_RIGHT= { (S1!='1 ^ CHANGED(S1,0)) & + (S0!='0 ^ CHANGED(S0,0)) } + LOADING = { (S1!='0 ^ CHANGED(S1,0)) & + (S0!='0 ^ CHANGED(S0,0)) } + + WIDTH: + NODE = SRCK + MIN_HI = 30NS + MIN_LO = 30NS + + WIDTH: + NODE = RCK + MIN_HI = 30NS + + SETUP_HOLD: + DATA(2) = S0 S1 + CLOCK LH = SRCK + SETUPTIME = 45NS + WHEN = { NOT_CLEARING } + + SETUP_HOLD: + DATA(1) = SRCLRBAR + CLOCK LH = SRCK + SETUPTIME_LO = 25NS + + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = SRCK + SETUPTIME = 30NS + WHEN = { NOT_CLEARING & LOADING } + + SETUP_HOLD: ;SRCK RISE BEFORE RCK RISE SETUP TIME + DATA(4) = Q1A Q1B Q1C Q1D ;USED INTERNAL NODES TO DETECT VIOLATION + CLOCK LH = RCK + SETUPTIME = 30NS + MESSAGE = " SETUPTIME VIOLATION OF SRCK BEFORE RCK" + + SETUP_HOLD: + DATA(1) = SERR + CLOCK LH = SRCK + SETUPTIME = 35NS + WHEN = { NOT_CLEARING & SH_RIGHT } + + SETUP_HOLD: + DATA(1) = SERL + CLOCK LH = SRCK + SETUPTIME = 35NS + WHEN = { NOT_CLEARING & SH_LEFT } * .ENDS * *$ *--------- * 74LS684 8-BIT MAGNITUDE COMPARATORS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-20-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS684 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I PEQBAR_O PGQBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS684LOG LOGICEXP(16,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I + Q0_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 PEQBAR PGQBAR + D0_GATE + IO_LS_ST IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + * INTERMEDIATE TERMS: + PQ7 = { ~(P7 ^ Q7) } + PQ6 = { ~(P6 ^ Q6) } + PQ5 = { ~(P5 ^ Q5) } + PQ4 = { ~(P4 ^ Q4) } + PQ3 = { ~(P3 ^ Q3) } + PQ2 = { ~(P2 ^ Q2) } + PQ1 = { ~(P1 ^ Q1) } + PQ0 = { ~(P0 ^ Q0) } + PQ67 = { PQ6 & PQ7 } + PQ57 = { PQ5 & PQ67 } + PQ47 = { PQ4 & PQ57 } + PQ37 = { PQ3 & PQ47 } + PQ27 = { PQ2 & PQ37 } + PQ17 = { PQ1 & PQ27 } + * OUTPUT ASSIGNMENTS: + PEQBAR = { ~(PQ7 & PQ6 & PQ5 & PQ4 & PQ3 & PQ2 & PQ1 & PQ0) } + PGQBAR = { ~((PQ17 & ~Q0 & P0) | (PQ27 & ~Q1 & P1) | (PQ37 & ~Q2 & P2) | + (PQ47 & ~Q3 & P3) | (PQ57 & ~Q4 & P4) | (PQ67 & ~Q5 & P5) | + (PQ7 & ~Q6 & P6) | (~Q7 & P7)) } * ULS684DLY PINDLY (2,0,16) DPWR DGND + PEQBAR PGQBAR + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O PGQBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + P_CHANGE = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) + | CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + Q_CHANGE = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) + | CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + + PINDLY: + PEQBAR_O = { + CASE( + P_CHANGE & TRN_HL, DELAY(-1,17NS,25NS), + Q_CHANGE & TRN_HL, DELAY(-1,15NS,25NS), + Q_CHANGE & TRN_LH, DELAY(-1,16NS,25NS), + P_CHANGE & TRN_LH, DELAY(-1,15NS,25NS), + DELAY(-1,18NS,26NS) ;DEFAULT + ) + } + + PGQBAR_O = { + CASE( + Q_CHANGE & TRN_HL, DELAY(-1,20NS,30NS), + P_CHANGE & TRN_HL, DELAY(-1,17NS,30NS), + Q_CHANGE & TRN_LH, DELAY(-1,24NS,30NS), + P_CHANGE & TRN_LH, DELAY(-1,22NS,30NS), + DELAY(-1,25NS,31NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS685 8-BIT MAGNITUDE/IDENTITY COMPARATOR WITH OPEN-COLLECTOR OUTPUTS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-20-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS685 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I PEQBAR_O PGQBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * ULS685LOG LOGICEXP(16,18) DPWR DGND + P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I Q3_I + Q2_I Q1_I Q0_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 PEQBAR PGQBAR + D0_GATE + IO_LS_ST IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFERS: + P7 = { P7_I } + P6 = { P6_I } + P5 = { P5_I } + P4 = { P4_I } + P3 = { P3_I } + P2 = { P2_I } + P1 = { P1_I } + P0 = { P0_I } + Q7 = { Q7_I } + Q6 = { Q6_I } + Q5 = { Q5_I } + Q4 = { Q4_I } + Q3 = { Q3_I } + Q2 = { Q2_I } + Q1 = { Q1_I } + Q0 = { Q0_I } + * INTERMEDIATE TERMS: + PQ7 = { ~(P7 ^ Q7) } + PQ6 = { ~(P6 ^ Q6) } + PQ5 = { ~(P5 ^ Q5) } + PQ4 = { ~(P4 ^ Q4) } + PQ3 = { ~(P3 ^ Q3) } + PQ2 = { ~(P2 ^ Q2) } + PQ1 = { ~(P1 ^ Q1) } + PQ0 = { ~(P0 ^ Q0) } + PQ67 = { PQ6 & PQ7 } + PQ57 = { PQ5 & PQ67 } + PQ47 = { PQ4 & PQ57 } + PQ37 = { PQ3 & PQ47 } + PQ27 = { PQ2 & PQ37 } + PQ17 = { PQ1 & PQ27 } + * OUTPUT ASSIGNMENTS: + PEQBAR = { ~PQ17 } + PGQBAR = { ~((PQ17 & ~Q0 & P0) | (PQ27 & ~Q1 & P1) | (PQ37 & ~Q2 & P2) | + (PQ47 & ~Q3 & P3) | (PQ57 & ~Q4 & P4) | (PQ67 & ~Q5 & P5) | + (PQ7 & ~Q6 & P6) | (~Q7 & P7)) } * ULS685DLY PINDLY (2,0,16) DPWR DGND + PEQBAR PGQBAR + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O PGQBAR_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + P_CHANGE = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) + | CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + Q_CHANGE = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) + | CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + + PINDLY: + PEQBAR_O = { + CASE( + P_CHANGE & TRN_LH, DELAY(-1,30NS,45NS), + Q_CHANGE & TRN_LH, DELAY(-1,24NS,45NS), + Q_CHANGE & TRN_HL, DELAY(-1,23NS,35NS), + P_CHANGE & TRN_HL, DELAY(-1,19NS,35NS), + DELAY(-1,31NS,46NS) ;DEFAULT + ) + } + PGQBAR_O = { + CASE( + P_CHANGE & TRN_LH, DELAY(-1,32NS,45NS), + Q_CHANGE & TRN_LH, DELAY(-1,30NS,45NS), + Q_CHANGE & TRN_HL, DELAY(-1,20NS,35NS), + P_CHANGE & TRN_HL, DELAY(-1,16NS,35NS), + DELAY(-1,33NS,46NS) ;DEFAULT + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS686 8-BIT MAGNITUDE COMPARATORS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-24-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS686 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I G1BAR_I G2BAR_I + PEQBAR_O PGQBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(16) DPWR DGND P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I + Q4_I Q3_I Q2_I Q1_I Q0_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + D0_GATE IO_LS_ST IO_LEVEL={IO_LEVEL} * ULS686LOG LOGICEXP(18,4) DPWR DGND + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 G1BAR_I G2BAR_I + G1BAR G2BAR PEQBAR PGQBAR + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + + LOGIC: * BUFFER: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + * INTERMEDIATE TERMS: + PQ7 = { ~(P7 ^ Q7) } + PQ6 = { ~(P6 ^ Q6) } + PQ5 = { ~(P5 ^ Q5) } + PQ4 = { ~(P4 ^ Q4) } + PQ3 = { ~(P3 ^ Q3) } + PQ2 = { ~(P2 ^ Q2) } + PQ1 = { ~(P1 ^ Q1) } + PQ0 = { ~(P0 ^ Q0) } + PQG76 = { PQ7 & PQ6 & ~G2BAR } + PQG75 = { PQG76 & PQ5 } + PQG74 = { PQG75 & PQ4 } + PQG73 = { PQG74 & PQ3 } + PQG72 = { PQG73 & PQ2 } + PQG71 = { PQG72 & PQ1 } + * OUTPUT ASSIGNMENTS: + PEQBAR = { ~(PQ7 & PQ6 & PQ5 & PQ4 & PQ3 & PQ2 & PQ1 & PQ0 & ~G1BAR) } + PGQBAR = { ~((PQG71 & ~Q0 & P0) | (PQG72 & ~Q1 & P1) | + (PQG73 & ~Q2 & P2) | (PQG74 & ~Q3 & P3) | + (PQG75 & ~Q4 & P4) | (PQG76 & ~Q5 & P5) | + (PQ7 & ~G2BAR & ~Q6 & P6) | (~G2BAR & ~Q7 & P7)) } * ULS686DLY PINDLY (2,0,18) DPWR DGND + PEQBAR PGQBAR + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 G1BAR G2BAR + PEQBAR_O PGQBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + P_CHANGE = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) + | CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + Q_CHANGE = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) + | CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + G1_CHANGE = { CHANGED(G1BAR,0) } + G2_CHANGE = { CHANGED(G2BAR,0) } + + PINDLY: + PEQBAR_O = { + CASE( + Q_CHANGE & TRN_HL, DELAY(-1,21NS,30NS), + P_CHANGE & TRN_HL, DELAY(-1,20NS,30NS), + G1_CHANGE & TRN_HL, DELAY(-1,19NS,30NS), + (P_CHANGE | Q_CHANGE) & TRN_LH, DELAY(-1,13NS,25NS), + G1_CHANGE & TRN_LH, DELAY(-1,11NS,20NS), + DELAY(-1,22NS,31NS) ;DEFAULT + ) + } + + PGQBAR_O = { + CASE( + G2_CHANGE & TRN_LH, DELAY(-1,21NS,30NS), + Q_CHANGE & TRN_HL, DELAY(-1,19NS,30NS), + P_CHANGE & TRN_LH, DELAY(-1,19NS,30NS), + Q_CHANGE & TRN_LH, DELAY(-1,18NS,30NS), + P_CHANGE & TRN_HL, DELAY(-1,15NS,30NS), + G2_CHANGE & TRN_HL, DELAY(-1,16NS,25NS), + DELAY(-1,22NS,31NS) ;DEFAULT + ) + } * .ENDS * *$ *-------------------------------------------------------------------------- * 74LS687 8-BIT MAGNITUDE/IDENTITY COMPARATORS WITH OPEN-COLLECTOR OUTPUTS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATABOOK, 1988, TI * KN 8-19-92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS687 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I + Q7_I Q6_I Q5_I Q4_I Q3_I Q2_I Q1_I Q0_I G1BAR_I G2BAR_I + PEQBAR_O PGQBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 BUFA(16) DPWR DGND P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I + Q4_I Q3_I Q2_I Q1_I Q0_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + D0_GATE IO_LS_ST IO_LEVEL = {IO_LEVEL} * ULS687LOG LOGICEXP(18,4) DPWR DGND + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 G1BAR_I G2BAR_I + G1BAR G2BAR PEQBAR PGQBAR + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: * BUFFER: + G1BAR = { G1BAR_I } + G2BAR = { G2BAR_I } + * INTERMEDIATE TERMS: + PQ7 = { ~(~P7 ^ ~Q7) } + PQ6 = { ~(~P6 ^ ~Q6) } + PQ5 = { ~(~P5 ^ ~Q5) } + PQ4 = { ~(~P4 ^ ~Q4) } + PQ3 = { ~(~P3 ^ ~Q3) } + PQ2 = { ~(~P2 ^ ~Q2) } + PQ1 = { ~(~P1 ^ ~Q1) } + PQ0 = { ~(~P0 ^ ~Q0) } + PQG76 = { PQ7 & PQ6 & ~G2BAR } + PQG75 = { PQG76 & PQ5 } + PQG74 = { PQG75 & PQ4 } + PQG73 = { PQG74 & PQ3 } + PQG72 = { PQG73 & PQ2 } + PQG71 = { PQG72 & PQ1 } + * OUTPUT ASSIGNMENTS: + PEQBAR = { ~(PQ7 & PQ6 & PQ5 & PQ4 & PQ3 & PQ2 & PQ1 & PQ0 & ~G1BAR) } + PGQBAR = { ~((PQG71 & ~Q0 & P0) | (PQG72 & ~Q1 & P1) | + (PQG73 & ~Q2 & P2) | (PQG74 & ~Q3 & P3) | + (PQG75 & ~Q4 & P4) | (PQG76 & ~Q5 & P5) | + (PQ7 & ~G2BAR & ~Q6 & P6) | (~G2BAR & ~Q7 & P7)) } * ULS687DLY PINDLY (2,0,18) DPWR DGND + PEQBAR PGQBAR + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 G1BAR G2BAR + PEQBAR_O PGQBAR_O + IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + + BOOLEAN: + P_CHANGE = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) + | CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + Q_CHANGE = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) + | CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + PQ_CHANGE = { Q_CHANGE | P_CHANGE } + G1_CHANGE = { CHANGED(G1BAR,0) } + G2_CHANGE = { CHANGED(G2BAR,0) } + + PINDLY: + PEQBAR_O = { + CASE( + PQ_CHANGE & TRN_LH, DELAY(-1,24NS,35NS), + G1_CHANGE & TRN_LH, DELAY(-1,21NS,35NS), + PQ_CHANGE & TRN_HL, DELAY(-1,20NS,30NS), + G1_CHANGE & TRN_HL, DELAY(-1,18NS,30NS), + DELAY(-1,25NS,36NS) ;DEFAULT + ) + } + + PGQBAR_O = { + CASE( + (G2_CHANGE | PQ_CHANGE) & TRN_LH, DELAY(-1,24NS,35NS), + PQ_CHANGE & TRN_HL, DELAY(-1,16NS,30NS), + G2_CHANGE & TRN_HL, DELAY(-1,15NS,30NS), + DELAY(-1,25NS,36NS) ;DEFAULT + ) + } * .ENDS * *$ *--------- * 74LS688 8-BIT IDENTITY COMPARATORS * * TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS688 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * U1 BUFA(16) DPWR DGND P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I + Q4_I Q3_I Q2_I Q1_I Q0_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + D0_GATE IO_LS_ST IO_LEVEL = {IO_LEVEL} * ULS688LOG LOGICEXP(17,2) DPWR DGND + GBAR_I P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + GBAR PEQBAR + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * ULS688DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_LS MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(-1,17NS,23NS), + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,13NS,20NS), + TRN_LH, DELAY(-1,12NS,18NS), + DELAY(-1,18NS,24NS) + ) + } * .ENDS * *$ *--------- * 74LS689 8-BIT IDENTITY COMPARATORS * * THE TTL DATA BOOK, VOL 2, STANDARD, S, LS, TTL, 1985, TI * NH 8/21/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS689 P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I Q4_I + Q3_I Q2_I Q1_I Q0_I GBAR_I PEQBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * U1 BUFA(16) DPWR DGND P7_I P6_I P5_I P4_I P3_I P2_I P1_I P0_I Q7_I Q6_I Q5_I + Q4_I Q3_I Q2_I Q1_I Q0_I + P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + D0_GATE IO_LS_ST IO_LEVEL = {IO_LEVEL} * ULS689LOG LOGICEXP(17,2) DPWR DGND + GBAR_I P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + GBAR PEQBAR + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + + GBAR = { GBAR_I } + + PEQ7 = { ~(~P7 ^ ~Q7) } + PEQ6 = { ~(~P6 ^ ~Q6) } + PEQ5 = { ~(~P5 ^ ~Q5) } + PEQ4 = { ~(~P4 ^ ~Q4) } + PEQ3 = { ~(~P3 ^ ~Q3) } + PEQ2 = { ~(~P2 ^ ~Q2) } + PEQ1 = { ~(~P1 ^ ~Q1) } + PEQ0 = { ~(~P0 ^ ~Q0) } + + PEQBAR = { ~(PEQ7 & PEQ6 & PEQ5 & PEQ4 & PEQ3 & PEQ2 & PEQ1 & PEQ0 & ~GBAR) } * ULS689DLY PINDLY (1,0,17) DPWR DGND + PEQBAR + GBAR P7 P6 P5 P4 P3 P2 P1 P0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 + PEQBAR_O + IO_LS_OC MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + ANY_CH_P = { CHANGED(P7,0) | CHANGED(P6,0) | CHANGED(P5,0) | CHANGED(P4,0) | + CHANGED(P3,0) | CHANGED(P2,0) | CHANGED(P1,0) | CHANGED(P0,0) } + ANY_CH_Q = { CHANGED(Q7,0) | CHANGED(Q6,0) | CHANGED(Q5,0) | CHANGED(Q4,0) | + CHANGED(Q3,0) | CHANGED(Q2,0) | CHANGED(Q1,0) | CHANGED(Q0,0) } + ENABLE = { GBAR!='1 } + + PINDLY: + PEQBAR_O = { + CASE( + CHANGED(GBAR,0) & TRN_HL, DELAY(-1,19NS,30NS), + CHANGED(GBAR,0) & TRN_LH, DELAY(-1,22NS,35NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_HL, DELAY(-1,22NS,35NS), + (ANY_CH_P | ANY_CH_Q) & ENABLE & TRN_LH, DELAY(-1,24NS,40NS), + DELAY(-1,25NS,41NS) + ) + } * .ENDS * *$ *------------------------------------------------------------------------- * 74LS690 Sync. Counter w/ Output Registers & Mux. 3-State Outputs * * THE TTL DATA BOOK, 1988, TI * JSW 07/21/92 Remodeled using LOGICEXP, PINDLY, CONSTRAINT Devices * .SUBCKT 74LS690 GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I + ENT_I CCK_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CCLRBAR CCK + DA DB DC DD CA CB CC CD CABAR CBBAR CCBAR CDBAR + D0_EFF IO_LS U2 DFF(4) DPWR DGND $D_HI RCLRBAR RCK + CA CB CC CD $D_NC $D_NC $D_NC $D_NC RABAR RBBAR RCBAR RDBAR + D0_EFF IO_LS * ULS690LOG LOGICEXP(25,23) DPWR DGND + GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I ENT_I CCK_I A_I + B_I C_I D_I CA CB CC CD CABAR CBBAR CCBAR CDBAR RABAR RBBAR RCBAR RDBAR + GBAR R/CBAR RCLRBAR RCK CCLRBAR LOADBAR ENP ENT CCK A B C D + DA DB DC DD QA QB QC QD RCO IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCLRBAR = { RCLRBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + LOADBAR = { LOADBAR_I } + ENP = { ENP_I } + ENT = { ENT_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + IA1 = { CA & IEN } + IA2 = { ~IEN & LOADBAR & CABAR } + IB1 = { CB & IEN & ~CABAR } + IB2 = { (~IEN | CABAR) & LOADBAR & CBBAR } + IB3 = { IEN & ~CABAR & CCBAR & ~CDBAR } + IC1 = { CC & IEN & ~CABAR & ~CBBAR } + IC2 = { (~IEN | CABAR | CBBAR) & LOADBAR & CCBAR } + IC3 = { IEN & ~CABAR & ~CBBAR & ~CDBAR } + ID1 = { CD & IEN & ~CABAR } + ID2 = { (~IEN | CABAR | CBBAR | CCBAR) & LOADBAR & CDBAR } + DA = { ~(IA1 | IA2 | ~(LOADBAR | A)) } + DB = { ~(IB1 | IB2 | IB3 | ~(LOADBAR | B)) } + DC = { ~(IC1 | IC2 | IC3 | ~(LOADBAR | C)) } + DD = { ~(ID1 | ID2 | ~(LOADBAR | D)) } + QA = { ~((R/CBAR & RABAR) | (~R/CBAR & CABAR)) } + QB = { ~((R/CBAR & RBBAR) | (~R/CBAR & CBBAR)) } + QC = { ~((R/CBAR & RCBAR) | (~R/CBAR & CCBAR)) } + QD = { ~((R/CBAR & RDBAR) | (~R/CBAR & CDBAR)) } + RCO = { ~(~ENT | CABAR | CDBAR) } * ULS690DLY PINDLY (5,1,17) DPWR DGND + QA QB QC QD RCO + GBAR + CCK RCK ENT CCLRBAR RCLRBAR R/CBAR LOADBAR A B C D ENP IEN CA CB CC CD + QA_O QB_O QC_O QD_O RCO_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + RCLEAR = { CHANGED_HL(RCLRBAR,0) } + ENABLE = { CHANGED_HL(GBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,13NS,20NS), + DELAY(-1,23NS,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CCLOCK | RCLOCK) & TRN_LH, DELAY(-1,12NS,20NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + (CCLOCK | RCLOCK) & TRN_HL, DELAY(-1,17NS,25NS), + DISABLE, DELAY(-1,17NS,30NS), + ENABLE, DELAY(-1,19NS,30NS), + RCLEAR, DELAY(-1,20NS,30NS), + DELAY(-1,23NS,40NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + WIDTH: + NODE = RCLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 + & CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CCK + SETUPTIME_LO = 30NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(4) = CA CB CC CD + CLOCK LH = RCK + SETUPTIME = 30NS + WHEN = { CCLRBAR!='0 & RCLRBAR!='0 } + MESSAGE = "Invalid SETUP TIME from CCK to RCK." + SETUP_HOLD: + DATA(1) = RCLRBAR + CLOCK LH = RCK + RELEASETIME_LH = 25NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS691 Sync. Counter w/ Output Registers & Mux. 3-State Outputs * * THE TTL DATA BOOK, 1988, TI * tc 07/10/92 Remodeled using LOGICEXP, PINDLY, CONSTRAINT Devices * .SUBCKT 74LS691 GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I + ENT_I CCK_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CCLRBAR CCK + DA DB DC DD CA CB CC CD CABAR CBBAR CCBAR CDBAR + D0_EFF IO_LS U2 DFF(4) DPWR DGND $D_HI RCLRBAR RCK + CA CB CC CD $D_NC $D_NC $D_NC $D_NC RABAR RBBAR RCBAR RDBAR + D0_EFF IO_LS * ULS691LOG LOGICEXP(25,23) DPWR DGND + GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I ENT_I CCK_I + A_I B_I C_I D_I CA CB CC CD CABAR CBBAR CCBAR CDBAR RABAR RBBAR RCBAR RDBAR + GBAR R/CBAR RCLRBAR RCK CCLRBAR LOADBAR ENP ENT CCK A B C D + DA DB DC DD QA QB QC QD RCO IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCLRBAR = { RCLRBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + LOADBAR = { LOADBAR_I } + ENP = { ENP_I } + ENT = { ENT_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + IA1 = { CA & IEN } + IA2 = { ~IEN & LOADBAR & CABAR } + IB1 = { CB & IEN & ~CABAR } + IB2 = { (~IEN | CABAR) & LOADBAR & CBBAR } + IC1 = { CC & IEN & ~CABAR & ~CBBAR } + IC2 = { (~IEN | CABAR | CBBAR) & LOADBAR & CCBAR } + ID1 = { CD & IEN & ~CABAR & ~CBBAR & ~CCBAR } + ID2 = { (~IEN | CABAR | CBBAR | CCBAR) & LOADBAR & CDBAR } + DA = { ~(IA1 | IA2 | ~(LOADBAR | A)) } + DB = { ~(IB1 | IB2 | ~(LOADBAR | B)) } + DC = { ~(IC1 | IC2 | ~(LOADBAR | C)) } + DD = { ~(ID1 | ID2 | ~(LOADBAR | D)) } + QA = { ~((R/CBAR & RABAR) | (~R/CBAR & CABAR)) } + QB = { ~((R/CBAR & RBBAR) | (~R/CBAR & CBBAR)) } + QC = { ~((R/CBAR & RCBAR) | (~R/CBAR & CCBAR)) } + QD = { ~((R/CBAR & RDBAR) | (~R/CBAR & CDBAR)) } + RCO = { ~(~ENT | CABAR | CBBAR | CCBAR | CDBAR) } * ULS691DLY PINDLY (5,1,17) DPWR DGND + QA QB QC QD RCO + GBAR + CCK RCK ENT CCLRBAR RCLRBAR R/CBAR LOADBAR A B C D ENP IEN CA CB CC CD + QA_O QB_O QC_O QD_O RCO_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + PINDLY: + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,13NS,20NS), + DELAY(-1,23NS,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CCLOCK | RCLOCK) & TRN_LH, DELAY(-1,12NS,20NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + (CCLOCK | RCLOCK) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED_LH(GBAR,0), DELAY(-1,17NS,30NS), + CHANGED_HL(GBAR,0), DELAY(-1,19NS,30NS), + CHANGED_HL(RCLRBAR,0), DELAY(-1,20NS,30NS), + CHANGED_HL(CCLRBAR,0), DELAY(-1,23NS,40NS), + DELAY(-1,23NS,40NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + WIDTH: + NODE = RCLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 & + CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CCK + SETUPTIME_LO = 30NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(4) = CA CB CC CD + CLOCK LH = RCK + SETUPTIME_HI = 30NS + WHEN = { RCLRBAR!='0 & CCLRBAR!='0 } + MESSAGE = "SETUPTIME VIOLATION CCK BEFORE RCK" + SETUP_HOLD: + DATA(1) = RCLRBAR + CLOCK LH = RCK + RELEASETIME_LH = 25NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS692 Sync. Counter w/ Output Registers & Mux. 3-State Outputs * * THE TTL DATA BOOK, 1985, TI * JSW 07/21/92 Remodeled using LOGICEXP, PINDLY, CONSTRAINT Devices * .SUBCKT 74LS692 GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I + ENT_I CCK_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CCK + DA DB DC DD IQA IQB IQC IQD IQABAR IQBBAR IQCBAR IQDBAR + D0_EFF IO_LS U2 DFF(4) DPWR DGND $D_HI $D_HI RCK + CA CB CC CD $D_NC $D_NC $D_NC $D_NC RABAR RBBAR RCBAR RDBAR + D0_EFF IO_LS * ULS692LOG LOGICEXP(25,27) DPWR DGND + GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I ENT_I CCK_I A_I + B_I C_I D_I IQA IQB IQC IQD IQABAR IQBBAR IQCBAR IQDBAR RABAR RBBAR RCBAR + RDBAR + GBAR R/CBAR RCLRBAR RCK CCLRBAR LOADBAR ENP ENT CCK A B C D + DA DB DC DD CA CB CC CD QA QB QC QD RCO IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCLRBAR = { RCLRBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + LOADBAR = { LOADBAR_I } + ENP = { ENP_I } + ENT = { ENT_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + ICL = { ~CCLRBAR } + IA1 = { IQA & IEN } + IA2 = { ~IEN & LOADBAR & IQABAR } + IA3 = { ICL | ~(LOADBAR | A) } + IB1 = { IQB & IEN & ~IQABAR } + IB2 = { (~IEN | IQABAR) & LOADBAR & IQBBAR } + IB3 = { ICL | ~(LOADBAR | B) } + IB4 = { IEN & ~IQABAR & IQCBAR & ~IQDBAR } + IC1 = { IQC & IEN & ~IQABAR & ~IQBBAR } + IC2 = { (~IEN | IQABAR | IQBBAR) & LOADBAR & IQCBAR } + IC3 = { ICL | ~(LOADBAR | C) } + IC4 = { IEN & ~IQABAR & ~IQBBAR & ~IQDBAR } + ID1 = { IQD & IEN & ~IQABAR } + ID2 = { (~IEN | IQABAR | IQBBAR | IQCBAR) & LOADBAR & IQDBAR } + ID3 = { ICL | ~(LOADBAR | D) } + DA = { ~(IA1 | IA2 | IA3) } + DB = { ~(IB1 | IB2 | IB3 | IB4) } + DC = { ~(IC1 | IC2 | IC3 | IC4) } + DD = { ~(ID1 | ID2 | ID3) } + CA = { IQA & RCLRBAR } + CB = { IQB & RCLRBAR } + CC = { IQC & RCLRBAR } + CD = { IQD & RCLRBAR } + QA = { ~((R/CBAR & RABAR) | (~R/CBAR & IQABAR)) } + QB = { ~((R/CBAR & RBBAR) | (~R/CBAR & IQBBAR)) } + QC = { ~((R/CBAR & RCBAR) | (~R/CBAR & IQCBAR)) } + QD = { ~((R/CBAR & RDBAR) | (~R/CBAR & IQDBAR)) } + RCO = { ~(~ENT | IQABAR | IQDBAR) } * ULS692DLY PINDLY (5,1,17) DPWR DGND + QA QB QC QD RCO + GBAR + CCK RCK ENT CCLRBAR RCLRBAR R/CBAR LOADBAR A B C D ENP IEN CA CB CC CD + QA_O QB_O QC_O QD_O RCO_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + RCLEAR = { CHANGED_HL(RCLRBAR,0) } + DISABLE = { CHANGED_LH(GBAR,0) } + PINDLY: + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,13NS,20NS), + DELAY(-1,23NS,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CCLOCK | RCLOCK) & TRN_LH, DELAY(-1,12NS,20NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + (CCLOCK | RCLOCK) & TRN_HL, DELAY(-1,17NS,25NS), + DISABLE, DELAY(-1,17NS,30NS), + DELAY(-1,19NS,30NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 + & CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CCK + SETUPTIME_LO = 30NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + SETUPTIME_LO = 40NS + SETUP_HOLD: + DATA(4) = CA CB CC CD + CLOCK LH = RCK + SETUPTIME = 30NS + MESSAGE = "Invalid SETUP TIME from CCK to RCK." + SETUP_HOLD: + DATA(1) = RCLRBAR + CLOCK LH = RCK + SETUPTIME_LO = 20NS * .ENDS * *$ *------------------------------------------------------------------------- * 74LS693 Sync. Counter w/ Output Registers & Mux. 3-State Outputs * * THE TTL DATA BOOK, 1988, TI * tc 07/14/92 Remodeled using LOGICEXP, PINDLY, CONSTRAINT Devices * .SUBCKT 74LS693 GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I + ENT_I CCK_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCO_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CCK + DA DB DC DD IQA IQB IQC IQD IQABAR IQBBAR IQCBAR IQDBAR + D0_EFF IO_LS U2 DFF(4) DPWR DGND $D_HI $D_HI RCK + CA CB CC CD $D_NC $D_NC $D_NC $D_NC RABAR RBBAR RCBAR RDBAR + D0_EFF IO_LS * ULS693LOG LOGICEXP(25,27) DPWR DGND + GBAR_I R/CBAR_I RCLRBAR_I RCK_I CCLRBAR_I LOADBAR_I ENP_I ENT_I CCK_I + A_I B_I C_I D_I IQA IQB IQC IQD IQABAR IQBBAR IQCBAR IQDBAR + RABAR RBBAR RCBAR RDBAR + GBAR R/CBAR RCLRBAR RCK CCLRBAR LOADBAR ENP ENT CCK A B C D DA DB DC DD + CA CB CC CD QA QB QC QD RCO IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCLRBAR = { RCLRBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + LOADBAR = { LOADBAR_I } + ENP = { ENP_I } + ENT = { ENT_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + IEN = { LOADBAR & ENP & ENT } + ICL = { ~CCLRBAR } + IA1 = { IQA & IEN } + IA2 = { ~IEN & LOADBAR & IQABAR } + IA3 = { ICL | ~(LOADBAR | A) } + IB1 = { IQB & IEN & ~IQABAR } + IB2 = { (~IEN | IQABAR) & LOADBAR & IQBBAR } + IB3 = { ICL | ~(LOADBAR | B) } + IC1 = { IQC & IEN & ~IQABAR & ~IQBBAR } + IC2 = { (~IEN | IQABAR | IQBBAR) & LOADBAR & IQCBAR } + IC3 = { ICL | ~(LOADBAR | C) } + ID1 = { IQD & IEN & ~IQABAR & ~IQBBAR & ~IQCBAR } + ID2 = { (~IEN | IQABAR | IQBBAR | IQCBAR) & LOADBAR & IQDBAR } + ID3 = { ICL | ~(LOADBAR | D) } + DA = { ~(IA1 | IA2 | IA3) } + DB = { ~(IB1 | IB2 | IB3) } + DC = { ~(IC1 | IC2 | IC3) } + DD = { ~(ID1 | ID2 | ID3) } + CA = { IQA & RCLRBAR } + CB = { IQB & RCLRBAR } + CC = { IQC & RCLRBAR } + CD = { IQD & RCLRBAR } + QA = { ~((R/CBAR & RABAR) | (~R/CBAR & IQABAR)) } + QB = { ~((R/CBAR & RBBAR) | (~R/CBAR & IQBBAR)) } + QC = { ~((R/CBAR & RCBAR) | (~R/CBAR & IQCBAR)) } + QD = { ~((R/CBAR & RDBAR) | (~R/CBAR & IQDBAR)) } + RCO = { ~(~ENT | IQABAR | IQBBAR | IQCBAR | IQDBAR) } * ULS693DLY PINDLY (5,1,17) DPWR DGND + QA QB QC QD RCO + GBAR + CCK RCK ENT R/CBAR CCLRBAR RCLRBAR LOADBAR A B C D ENP IEN CA CB CC CD + QA_O QB_O QC_O QD_O RCO_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + PINDLY: + RCO_O = { + CASE( + CHANGED(ENT,0), DELAY(-1,13NS,20NS), + DELAY(-1,23NS,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CCLOCK | RCLOCK) & TRN_LH, DELAY(-1,12NS,20NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + (CCLOCK | RCLOCK) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED_LH(GBAR,0), DELAY(-1,17NS,30NS), + CHANGED_HL(GBAR,0), DELAY(-1,19NS,30NS), + DELAY(-1,19NS,30NS) + ) + } + BOOLEAN: + NOT_CLEARING = { CCLRBAR!='0 ^ CHANGED(CCLRBAR,0) } + + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & NOT_CLEARING } + SETUP_HOLD: + DATA(2) = ENP ENT + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + NOT_CLEARING & CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CCK + SETUPTIME_LO = 30NS + WHEN = { NOT_CLEARING } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + SETUPTIME_LO = 40NS + SETUP_HOLD: + DATA(4) = CA CB CC CD + CLOCK LH = RCK + SETUPTIME_HI = 30NS + MESSAGE = "SETUPTIME VIOLATIONS CCK BEFORE RCK" + SETUP_HOLD: + DATA(1) = RCLRBAR + CLOCK LH = RCK + SETUPTIME_LO = 20NS * .ENDS * *$ *------------------------------------------------------------------------------ * 74LS696 SYNCHRONOUS UP/DOWN COUNTER WITH OUTPUT REGISTERS AND MULTILEXED * 3-STATE OUTPUTS * * THE TTL LOGIC STANDARD TTL, SCHOTTKY, LOW-POWER SCHOTTKY DATA BOOK, 1988, TI * NH 7/31/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS696 GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I ENPBAR_I + ENTBAR_I CCK_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS696LOG LOGICEXP(25,23) DPWR DGND + GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I ENPBAR_I ENTBAR_I CCK_I + A_I B_I C_I D_I LA LB LC LD LABAR LBBAR LCBAR LDBAR OUTA OUTB OUTC OUTD + GBAR R/CBAR RCK CCLRBAR U/DBAR LOADBAR ENPBAR ENTBAR CCK + A B C D DA DB DC DD RCOBAR QA QB QC QD EN + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } * * INTERMEDIATE TERM + + LOADA = { ~(LOADBAR | A) } + LOADB = { ~(LOADBAR | B) } + LOADC = { ~(LOADBAR | C) } + LOADD = { ~(LOADBAR | D) } + U/DA = { ~((LA & ~U/DBAR) | (U/DBAR & LABAR)) } + U/DB = { ~((LB & ~U/DBAR) | (U/DBAR & LBBAR)) } + U/DC = { ~((LC & ~U/DBAR) | (U/DBAR & LCBAR)) } + U/DD = { ~((LD & ~U/DBAR) | (U/DBAR & LDBAR)) } + EN = { (LOADBAR & ~ENPBAR & ~ENTBAR) } * * OUTPUT + DA = { ~((LA & EN) | (~EN & LOADBAR & LABAR) | LOADA) } + DB = { ~((LB & EN & U/DA) | (LCBAR & EN & U/DA & U/DD) | + ((~EN | ~U/DA) & LOADBAR & LBBAR) | LOADB) } + DC = { ~((LC & EN & U/DA & U/DB) | (EN & U/DA & U/DB & U/DD) | + ((~EN | ~U/DA | ~U/DB) & LOADBAR & LCBAR) | LOADC) } + DD = { ~((LD & EN & U/DA) | ((~EN | ~U/DA | ~U/DB | ~U/DC) & LOADBAR & LDBAR) + | LOADD) } + RCOBAR = { ~((U/DBAR & U/DA & U/DD & ~ENTBAR) | + (~ENTBAR & U/DA & U/DB & U/DC & U/DD & ~U/DBAR))} + QA = { ~((R/CBAR & OUTA) | (~R/CBAR & LABAR)) } + QB = { ~((R/CBAR & OUTB) | (~R/CBAR & LBBAR)) } + QC = { ~((R/CBAR & OUTC) | (~R/CBAR & LCBAR)) } + QD = { ~((R/CBAR & OUTD) | (~R/CBAR & LDBAR)) } * U1 DFF(4) DPWR DGND + $D_HI CCLRBAR CCK DA DB DC DD LA LB LC LD LABAR LBBAR LCBAR LDBAR + D0_EFF IO_STD * U2 DFF(4) DPWR DGND + $D_HI $D_HI RCK LA LB LC LD $D_NC $D_NC $D_NC $D_NC OUTA OUTB OUTC OUTD + D0_EFF IO_STD * ULS696DLY PINDLY (5,1,17) DPWR DGND + RCOBAR QA QB QC QD + GBAR + CCK RCK ENTBAR CCLRBAR R/CBAR A B C D ENPBAR LOADBAR U/DBAR LA LB LC LD EN + RCOBAR_O QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + CLOCK_RCK = { CHANGED_LH(RCK,0) & R/CBAR!='0 } + CLOCK_CCK = { CHANGED_LH(CCK,0) & R/CBAR!='1 } + + PINDLY: + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0) , DELAY(-1,13NS,20NS), + CHANGED_LH(CCK,0) , DELAY(-1,23NS,40NS), + DELAY(-1,24NS,41NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CLOCK_RCK | CLOCK_CCK) & TRN_LH, DELAY(-1,12NS,20NS), + (CLOCK_RCK | CLOCK_CCK) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + CHANGED_LH(GBAR,0), DELAY(-1,17NS,30NS), + CHANGED_HL(GBAR,0), DELAY(-1,19NS,30NS), + CHANGED_HL(CCLRBAR,0), DELAY(-1,23NS,40NS), + DELAY(-1,24NS,41NS) + ) + } + BOOLEAN: + NOTCLEAR = { CCLRBAR!='0 } + NOTLOAD = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + + FREQ: + NODE = CCK + MAXFREQ = 20MEG + + FREQ: + NODE = RCK + MAXFREQ = 20MEG + + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + + SETUP_HOLD: + DATA(1) LOADBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { NOTCLEAR } + + SETUP_HOLD: + DATA(2) ENPBAR ENTBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { NOTCLEAR & NOTLOAD & CHANGED(EN,30) } + + SETUP_HOLD: + DATA(1) U/DBAR + CLOCK LH = CCK + SETUPTIME = 35NS + WHEN = { NOTCLEAR & NOTLOAD + & (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) + & (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } + + SETUP_HOLD: + DATA(4) A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { NOTCLEAR & (LOADBAR!='1 ^ CHANGED_LH(LOADBAR,0)) } + + SETUP_HOLD: + DATA(1) CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 25NS + + SETUP_HOLD: + DATA(4) LA LB LC LD + CLOCK LH = RCK + SETUPTIME_HI = 30NS + WHEN = { NOTCLEAR } + MESSAGE = "Invalid SETUP TIME from CCK to RCK." * .ENDS * *$ *------------------------------------------------------------------------- * 74LS697 Sync. Up/Down Counter (Output Registers & Mux. 3-State Outputs) * * THE TTL DATA BOOK, 1988, TI * tc 07/31/92 Remodeled using LOGICEXP, PINDLY, CONSTRAINT Devices * .SUBCKT 74LS697 GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I + ENPBAR_I ENTBAR_I CCK_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI CCLRBAR CCK + DA DB DC DD CA CB CC CD CABAR CBBAR CCBAR CDBAR + D0_EFF IO_LS U2 DFF(4) DPWR DGND $D_HI $D_HI RCK + CA CB CC CD $D_NC $D_NC $D_NC $D_NC RABAR RBBAR RCBAR RDBAR + D0_EFF IO_LS * ULS697LOG LOGICEXP(25,23) DPWR DGND + GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I ENPBAR_I ENTBAR_I CCK_I + A_I B_I C_I D_I CA CB CC CD CABAR CBBAR CCBAR CDBAR RABAR RBBAR RCBAR RDBAR + GBAR R/CBAR RCK CCLRBAR U/DBAR LOADBAR ENPBAR ENTBAR CCK A B C D + DA DB DC DD QA QB QC QD RCOBAR IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UP = { U/DBAR } + DN = { ~U/DBAR } + IEN = { ~(~LOADBAR | ENPBAR | ENTBAR) } + IRC = { ~R/CBAR } + IA1 = { CA & IEN } + IA2 = { ~IEN & LOADBAR & CABAR } + IA3 = { ~((CA & DN) | (UP & CABAR)) } + IB1 = { CB & IEN & IA3 } + IB2 = { ~(IEN & IA3) & LOADBAR & CBBAR } + IB3 = { ~((CB & DN) | (UP & CBBAR)) } + IC1 = { CC & IEN & IA3 & IB3 } + IC2 = { ~(IEN & IA3 & IB3) & LOADBAR & CCBAR } + IC3 = { ~((CC & DN) | (UP & CCBAR)) } + ID1 = { CD & IEN & IA3 & IB3 & IC3 } + ID2 = { ~(IEN & IA3 & IB3 & IC3 ) & LOADBAR & CDBAR } + ID3 = { ~((CD & DN) | (UP & CDBAR)) } + DA = { ~(IA1 | IA2 | ~(LOADBAR | A)) } + DB = { ~(IB1 | IB2 | ~(LOADBAR | B)) } + DC = { ~(IC1 | IC2 | ~(LOADBAR | C)) } + DD = { ~(ID1 | ID2 | ~(LOADBAR | D)) } + QA = { ~((R/CBAR & RABAR) | (IRC & CABAR)) } + QB = { ~((R/CBAR & RBBAR) | (IRC & CBBAR)) } + QC = { ~((R/CBAR & RCBAR) | (IRC & CCBAR)) } + QD = { ~((R/CBAR & RDBAR) | (IRC & CDBAR)) } + RCOBAR = { ~(~ENTBAR & IA3 & IB3 & IC3 & ID3) } * ULS697DLY PINDLY (5,1,13) DPWR DGND + QA QB QC QD RCOBAR + GBAR + CCK RCK ENTBAR CCLRBAR R/CBAR LOADBAR U/DBAR A B C D ENPBAR IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + PINDLY: + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0), DELAY(-1,13NS,20NS), + DELAY(-1,23NS,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CCLOCK | RCLOCK) & TRN_LH, DELAY(-1,12NS,20NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + (CCLOCK | RCLOCK) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED_LH(GBAR,0), DELAY(-1,17NS,30NS), + CHANGED_HL(GBAR,0), DELAY(-1,19NS,30NS), + CHANGED_HL(CCLRBAR,0), DELAY(-1,23NS,40NS), + DELAY(-1,23NS,40NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = CCLRBAR + MIN_LO = 20NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 & + CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CCK + SETUPTIME = 35NS + WHEN = { (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) & + (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & CCLRBAR!='0 } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + RELEASETIME_LH = 25NS + SETUP_HOLD: + DATA(1) = CCK + CLOCK LH = RCK + SETUPTIME_HI = 30NS * .ENDS * *$ *------------------------------------------------------------------------------ * 74LS698 SYNCHRONOUS UP/DOWN COUNTER WITH OUTPUT REGISTERS AND MULTILEXED * 3-STATE OUTPUTS * * THE TTL DATA BOOK, VOL2, STANDARD, S, LS, TTL, 1985, TI * NH 8/3/92 REMODELED USING LOGICEXP, PINDLY, CONSTRAINT DEVICES * .SUBCKT 74LS698 GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I ENPBAR_I + ENTBAR_I CCK_I A_I B_I C_I D_I + QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR = $G_DPWR DGND = $G_DGND + PARAMS: MNTYMXDLY = 0 IO_LEVEL = 0 * ULS698LOG LOGICEXP(25,23) DPWR DGND + GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I ENPBAR_I ENTBAR_I + CCK_I A_I B_I C_I D_I LA LB LC LD LABAR LBBAR LCBAR LDBAR OUTA OUTB OUTC + OUTD + GBAR R/CBAR RCK CCLRBAR U/DBAR LOADBAR ENPBAR ENTBAR CCK + A B C D DA DB DC DD RCOBAR QA QB QC QD EN + D0_GATE IO_LS IO_LEVEL = {IO_LEVEL} + + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } * * INTERMEDIATE TERM + + LOADA = { ~(LOADBAR | A) | ~CCLRBAR } + LOADB = { ~(LOADBAR | B) | ~CCLRBAR } + LOADC = { ~(LOADBAR | C) | ~CCLRBAR } + LOADD = { ~(LOADBAR | D) | ~CCLRBAR } + U/DA = { ~((LA & ~U/DBAR) | (U/DBAR & LABAR)) } + U/DB = { ~((LB & ~U/DBAR) | (U/DBAR & LBBAR)) } + U/DC = { ~((LC & ~U/DBAR) | (U/DBAR & LCBAR)) } + U/DD = { ~((LD & ~U/DBAR) | (U/DBAR & LDBAR)) } + EN = { LOADBAR & ~ENPBAR & ~ENTBAR } * * OUTPUT + DA = { ~((LA & EN) | (~EN & LOADBAR & LABAR) | LOADA) } + DB = { ~((LB & EN & U/DA) | (LCBAR & EN & U/DA & U/DD) | + ((~EN | ~U/DA) & LOADBAR & LBBAR) | LOADB) } + DC = { ~((LC & EN & U/DA & U/DB) | (EN & U/DA & U/DB & U/DD) | + ((~EN | ~U/DA | ~U/DB) & LOADBAR & LCBAR) | LOADC) } + DD = { ~((LD & EN & U/DA) | ((~EN | ~U/DA | ~U/DB | ~U/DC) & LOADBAR & LDBAR) + | LOADD) } + RCOBAR = { ~((U/DBAR & U/DA & U/DD & ~ENTBAR) | + (~ENTBAR & U/DA & U/DB & U/DC & U/DD & ~U/DBAR)) } + QA = { ~((R/CBAR & OUTA) | (~R/CBAR & LABAR)) } + QB = { ~((R/CBAR & OUTB) | (~R/CBAR & LBBAR)) } + QC = { ~((R/CBAR & OUTC) | (~R/CBAR & LCBAR)) } + QD = { ~((R/CBAR & OUTD) | (~R/CBAR & LDBAR)) } * U1 DFF(4) DPWR DGND + $D_HI $D_HI CCK DA DB DC DD LA LB LC LD LABAR LBBAR LCBAR LDBAR + D0_EFF IO_LS * U2 DFF(4) DPWR DGND + $D_HI $D_HI RCK LA LB LC LD $D_NC $D_NC $D_NC $D_NC OUTA OUTB OUTC OUTD + D0_EFF IO_LS * ULS698DLY PINDLY (5,1,17) DPWR DGND + RCOBAR QA QB QC QD + GBAR + CCK RCK ENTBAR R/CBAR CCLRBAR A B C D ENPBAR LOADBAR U/DBAR LA LB LC LD EN + RCOBAR_O QA_O QB_O QC_O QD_O + IO_LS + MNTYMXDLY = {MNTYMXDLY} IO_LEVEL = {IO_LEVEL} + + BOOLEAN: + CLOCK_RCK = { CHANGED_LH(RCK,0) & R/CBAR!='0 } + CLOCK_CCK = { CHANGED_LH(CCK,0) & R/CBAR!='1 } + + PINDLY: + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0) , DELAY(-1,13NS,20NS), + CHANGED_LH(CCK,0) , DELAY(-1,23NS,40NS), + DELAY(-1,24NS,41NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CLOCK_RCK | CLOCK_CCK) & TRN_LH, DELAY(-1,12NS,20NS), + (CLOCK_RCK | CLOCK_CCK) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + CHANGED_LH(GBAR,0), DELAY(-1,17NS,30NS), + CHANGED_HL(GBAR,0), DELAY(-1,19NS,30NS), + DELAY(-1,20NS,31NS) + ) + } + BOOLEAN: + NOTCLEAR = { CCLRBAR!='0 ^ CHANGED(CCLRBAR,0) } + NOTLOAD = { LOADBAR!='0 ^ CHANGED(LOADBAR,0) } + + FREQ: + NODE = CCK + MAXFREQ = 20MEG + + FREQ: + NODE = RCK + MAXFREQ = 20MEG + + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + + SETUP_HOLD: + DATA(1) LOADBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { NOTCLEAR } + + SETUP_HOLD: + DATA(2) ENPBAR ENTBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { NOTCLEAR & NOTLOAD & CHANGED(EN,30NS) } + + SETUP_HOLD: + DATA(1) U/DBAR + CLOCK LH = CCK + SETUPTIME = 35NS + WHEN = { NOTCLEAR & NOTLOAD + & (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) + & (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) } + + SETUP_HOLD: + DATA(4) A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { NOTCLEAR & (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) } + + SETUP_HOLD: + DATA(1) CCLRBAR + CLOCK LH = CCK + SETUPTIME = 30NS + + SETUP_HOLD: + DATA(4) LA LB LC LD + CLOCK LH = RCK + SETUPTIME_HI = 30NS + MESSAGE = "Invalid SETUP TIME from CCK to RCK." * .ENDS * *$ *------------------------------------------------------------------------- * 74LS699 Sync. Up/Down Counter (Output Registers & Mux. 3-State Outputs) * * THE TTL DATA BOOK, 1988, TI * tc 07/31/92 Remodeled using LOGICEXP, PINDLY, CONSTRAINT devices * .SUBCKT 74LS699 GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I + ENPBAR_I ENTBAR_I CCK_I A_I B_I C_I D_I QA_O QB_O QC_O QD_O RCOBAR_O + OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND + PARAMS: MNTYMXDLY=0 IO_LEVEL=0 * U1 DFF(4) DPWR DGND $D_HI $D_HI CCK + DA DB DC DD CA CB CC CD CABAR CBBAR CCBAR CDBAR + D0_EFF IO_LS U2 DFF(4) DPWR DGND $D_HI $D_HI RCK + CA CB CC CD $D_NC $D_NC $D_NC $D_NC RABAR RBBAR RCBAR RDBAR + D0_EFF IO_LS * ULS699LOG LOGICEXP(25,23) DPWR DGND + GBAR_I R/CBAR_I RCK_I CCLRBAR_I U/DBAR_I LOADBAR_I ENPBAR_I ENTBAR_I + CCK_I A_I B_I C_I D_I CA CB CC CD CABAR CBBAR CCBAR CDBAR + RABAR RBBAR RCBAR RDBAR + GBAR R/CBAR RCK CCLRBAR U/DBAR LOADBAR ENPBAR ENTBAR CCK A B C D + DA DB DC DD QA QB QC QD RCOBAR IEN + D0_GATE IO_LS IO_LEVEL={IO_LEVEL} + LOGIC: + GBAR = { GBAR_I } + R/CBAR = { R/CBAR_I } + RCK = { RCK_I } + CCLRBAR = { CCLRBAR_I } + U/DBAR = { U/DBAR_I } + LOADBAR = { LOADBAR_I } + ENPBAR = { ENPBAR_I } + ENTBAR = { ENTBAR_I } + CCK = { CCK_I } + A = { A_I } + B = { B_I } + C = { C_I } + D = { D_I } + UP = { U/DBAR } + DN = { ~U/DBAR } + IEN = { ~(~LOADBAR | ENPBAR | ENTBAR) } + ICL = { ~CCLRBAR } + IRC = { ~R/CBAR } + IA1 = { CA & IEN } + IA2 = { ~IEN & LOADBAR & CABAR } + IA3 = { ~((CA & DN) | (UP & CABAR)) } + IB1 = { CB & IEN & IA3 } + IB2 = { ~(IEN & IA3) & LOADBAR & CBBAR } + IB3 = { ~((CB & DN) | (UP & CBBAR)) } + IC1 = { CC & IEN & IA3 & IB3 } + IC2 = { ~(IEN & IA3 & IB3) & LOADBAR & CCBAR } + IC3 = { ~((CC & DN) | (UP & CCBAR)) } + ID1 = { CD & IEN & IA3 & IB3 & IC3 } + ID2 = { ~(IEN & IA3 & IB3 & IC3 ) & LOADBAR & CDBAR } + ID3 = { ~((CD & DN) | (UP & CDBAR)) } + DA = { ~(IA1 | IA2 | ~(LOADBAR | A) | ICL) } + DB = { ~(IB1 | IB2 | ~(LOADBAR | B) | ICL) } + DC = { ~(IC1 | IC2 | ~(LOADBAR | C) | ICL) } + DD = { ~(ID1 | ID2 | ~(LOADBAR | D) | ICL) } + QA = { ~((R/CBAR & RABAR) | (IRC & CABAR)) } + QB = { ~((R/CBAR & RBBAR) | (IRC & CBBAR)) } + QC = { ~((R/CBAR & RCBAR) | (IRC & CCBAR)) } + QD = { ~((R/CBAR & RDBAR) | (IRC & CDBAR)) } + RCOBAR = { ~(~ENTBAR & IA3 & IB3 & IC3 & ID3) } * ULS699DLY PINDLY (5,1,13) DPWR DGND + QA QB QC QD RCOBAR + GBAR + CCK RCK ENTBAR R/CBAR CCLRBAR LOADBAR U/DBAR A B C D ENPBAR IEN + QA_O QB_O QC_O QD_O RCOBAR_O + IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} + BOOLEAN: + CCLOCK = { CHANGED_LH(CCK,0) } + RCLOCK = { CHANGED_LH(RCK,0) } + PINDLY: + RCOBAR_O = { + CASE( + CHANGED(ENTBAR,0), DELAY(-1,13NS,20NS), + DELAY(-1,23NS,40NS) + ) + } + TRISTATE: + ENABLE LO GBAR + QA_O QB_O QC_O QD_O = { + CASE( + (CCLOCK | RCLOCK) & TRN_LH, DELAY(-1,12NS,20NS), + CHANGED(R/CBAR,0), DELAY(-1,16NS,25NS), + (CCLOCK | RCLOCK) & TRN_HL, DELAY(-1,17NS,25NS), + CHANGED_LH(GBAR,0), DELAY(-1,17NS,30NS), + CHANGED_HL(GBAR,0), DELAY(-1,19NS,30NS), + DELAY(-1,19NS,30NS) + ) + } + FREQ: + NODE = CCK + MAXFREQ = 20MEG + FREQ: + NODE = RCK + MAXFREQ = 20MEG + WIDTH: + NODE = CCK + MIN_LO = 25NS + MIN_HI = 25NS + WIDTH: + NODE = RCK + MIN_LO = 25NS + MIN_HI = 25NS + SETUP_HOLD: + DATA(4) = A B C D + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='1 ^ CHANGED(LOADBAR,0)) & + (CCLRBAR!='0 ^ CHANGED(CCLRBAR,0)) } + SETUP_HOLD: + DATA(2) = ENPBAR ENTBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) + & (CCLRBAR!='0 ^ CHANGED(CCLRBAR,0)) & CHANGED(IEN,30NS) } + SETUP_HOLD: + DATA(1) = LOADBAR + CLOCK LH = CCK + SETUPTIME = 30NS + WHEN = { CCLRBAR!='0 ^ CHANGED(CCLRBAR,0) } + SETUP_HOLD: + DATA(1) = U/DBAR + CLOCK LH = CCK + SETUPTIME = 35NS + WHEN = { (ENPBAR!='1 ^ CHANGED(ENPBAR,0)) & + (ENTBAR!='1 ^ CHANGED(ENTBAR,0)) & + (LOADBAR!='0 ^ CHANGED(LOADBAR,0)) & + (CCLRBAR!='0 ^ CHANGED(CCLRBAR,0)) } + SETUP_HOLD: + DATA(1) = CCLRBAR + CLOCK LH = CCK + SETUPTIME = 30NS + SETUP_HOLD: + DATA(1) = CCK + CLOCK LH = RCK + SETUPTIME_HI = 30NS * .ENDS * *$